/***************************************************************************//** * @brief dds_set_phase *******************************************************************************/ int32_t dds_set_phase(uint32_t chan, uint32_t phase) { uint32_t pcore_version; uint64_t val64; uint32_t reg; dac_read(DAC_REG_VERSION, &pcore_version); if(DAC_PCORE_VERSION_MAJOR(pcore_version) < 8) { dac_write(DAC_REG_CNTRL_1, 0); } dac_read(DAC_REG_CHAN_CNTRL_2_IIOCHAN(chan), ®); reg &= ~DAC_DDS_INIT(~0); val64 = (uint64_t) phase * 0x10000ULL + (360000 / 2); val64 = val64 / 360000; reg |= DAC_DDS_INIT(val64); dac_write(DAC_REG_CHAN_CNTRL_2_IIOCHAN(chan), reg); if(DAC_PCORE_VERSION_MAJOR(pcore_version) < 8) { dac_write(DAC_REG_CNTRL_1, DAC_ENABLE); } else { dac_write(DAC_REG_CNTRL_1, DAC_SYNC); } return 0; }
/***************************************************************************//** * @brief dds_set_phase *******************************************************************************/ void dds_set_phase(struct ad9361_rf_phy *phy, uint32_t chan, uint32_t phase) { uint64_t val64; uint32_t reg; dds_st[phy->id_no].cached_phase[chan] = phase; dac_stop(phy); dac_read(phy, DAC_REG_CHAN_CNTRL_2_IIOCHAN(chan), ®); reg &= ~DAC_DDS_INIT(~0); val64 = (uint64_t) phase * 0x10000ULL + (360000 / 2); do_div(&val64, 360000); reg |= DAC_DDS_INIT(val64); dac_write(phy, DAC_REG_CHAN_CNTRL_2_IIOCHAN(chan), reg); dac_start_sync(phy, 0); }
int32_t dds_set_phase(dac_core *core, uint32_t chan, uint32_t phase) { uint64_t val64; uint32_t reg; dac_write(core, DAC_REG_SYNC_CONTROL, 0); dac_read(core, DAC_REG_DDS_INIT_INCR(chan), ®); val64 = (uint64_t) phase * 0x10000ULL + (360000 / 2); val64 = val64 / 360000; reg = (reg & ~DAC_DDS_INIT(~0)) | DAC_DDS_INIT(val64); dac_write(core, DAC_REG_DDS_INIT_INCR(chan), reg); dac_write(core, DAC_REG_SYNC_CONTROL, DAC_SYNC); return 0; }