const DC3Error_t FLASH_eraseSector( const uint32_t sectorAddr )
{
DC3Error_t status = ERR_NONE;
/* These flags have to be cleared before any operation can be done on the
* flash memory */
// DBG_printf("Clearing flash flags. Status before clear: %x\n",FLASH->SR );
FLASH_ClearFlag(
FLASH_FLAG_PGSERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGAERR |
FLASH_FLAG_WRPERR | FLASH_FLAG_OPERR | FLASH_FLAG_EOP
);
// DBG_printf("Status after clear: %x\n",FLASH->SR );
WRN_printf("*** Erasing Flash sector addr 0x%08x ***\n", sectorAddr);
/*Look up the STM32 value of the sector given the sector address */
uint16_t sector = FLASH_sectorAddrToFlashSect( sectorAddr );
DBG_printf("Erasing sector (0x%04x) with base addr: 0x%08x...\n",
sector, sectorAddr);
/* This is a blocking operation but it's only for a single sector so should
* not take that long */
FLASH_Status flash_status = FLASH_EraseSector(sector, VoltageRange_3);
status = FLASH_statusToErrorCode( flash_status );
if (ERR_NONE != status) {
ERR_printf("Flash error %d ( error 0x%08x) while erasing sector "
"0x%04x (base addr: 0x%08x)\n",
flash_status, status, sector, sectorAddr);
DBG_printf("FLASH SR:%lx\n", FLASH->SR);
}
return( status );
}
int * table_to_mem(TABLE *t) {
int len,long_count; int k,i,rows;int * buff;
Triple Qin,*Qout;char tmp[9];
Code stmt;
start_table(t,pop_operator);
stmt = get_ready_stmt();
// peek at the header
i = machine_step_fetch(&Qin,0);
rows = Qin.pointer;
buff = (int *) G_malloc(rows*sizeof(Triple)+8);
long_count=3*rows; //three fixed longs per row
Qout = (Triple *) (buff+2);
for(i=0;i<rows;i++) {
if(i) machine_step_fetch(&Qin,0);
len = machine_key_len(stmt);
k =1+ (len+3) /4; // count longs, word count and key keys have bytes countsdata
if(k==0) printf("error\n");
// make this append (qin,qout);
*Qout = Qin;
Qout->key = (char *) G_malloc(4*k+1);
long_count += k;
Qout->key[len+4]=0;
sprintf(Qout->key,"%4d",len);
memcpy(Qout->key+4,Qin.key,len);
DBG_printf("TM%s%c%3d\n",Qout->key,Qin.link,Qout->pointer);
Qout++;
}
sprintf(tmp,"%8d",long_count);
memcpy(buff,tmp,8);
return buff;
}
void EP932Controller_Initial(PEP932C_REGISTER_MAP pEP932C_RegMap, EP932C_CALLBACK IntCall)
{
// Save the Logical Hardware Assignment
pEP932C_Registers = pEP932C_RegMap;
EP932C_GenerateInt = IntCall;
// EP932 Reset Control
EP_EP932M_Reset();
EP932_EnableHPInit();
// Initial IIC
EP932_If_Initial();
// Reset Variables
// bit
is_Cap_HDMI = 0;
is_Cap_YCC444 = is_Cap_YCC422 = 0;
is_Connected = 0;
is_VideoChanging = 0;
is_AudioChanging = 0;
// data
TX_State = TXS_Search_EDID;
HTP_TimeCount = 0;
Process_Dispatch_ID = 0;
VideoChg_TimeCount = 0;
AudioChg_TimeCount = 0;
ReadEDID_TimeCount = 0;
HP_ChangeCount = 0;
RSEN_ChangeCount = 0;
memset(Gamut_Packet_Header_Backup, 0, 3);
// Reset all EP932C registers
memset(pEP932C_Registers, 0, sizeof(EP932C_REGISTER_MAP));
pEP932C_Registers->Video_Interface[0] = 0x80;
pEP932C_Registers->Power_Control = EP932E_Power_Control__PD_HDMI;
pEP932C_Registers->Audio_Interface = 0x10; // 2 Channel audio
// Update Version Registers
pEP932C_Registers->VendorID = 0x177A;
pEP932C_Registers->DeviceID = 0x0932;
pEP932C_Registers->Version_Major = VERSION_MAJOR;
pEP932C_Registers->Version_Minor = VERSION_MINOR;
DBG_printf(("Version %d.%d\r\n", (int)VERSION_MAJOR, (int)VERSION_MINOR ));
// Initial HDCP Info
memset(pEP932C_Registers->HDCP_AKSV, 0x00, sizeof(pEP932C_Registers->HDCP_AKSV));
memset(pEP932C_Registers->HDCP_BKSV, 0x00, sizeof(pEP932C_Registers->HDCP_BKSV));
// Update Configuration Registers
EP932_Reg_Read(EP932_Configuration, DDC_Data, 1);
pEP932C_Registers->Configuration = DDC_Data[0];
// Set Revocation List address
HDCP_Extract_BKSV_BCAPS3(pEP932C_Registers->HDCP_BKSV);
HDCP_Extract_FIFO((unsigned char*)pEP932C_Registers->HDCP_KSV_FIFO, sizeof(pEP932C_Registers->HDCP_KSV_FIFO));
HDCP_Stop();
// Reset EP932 Control Program
EP932Controller_Reset();
}
/**
* Закрыть сокет сервера во время нормального выхода из программы.
*/
void close_server_socfd_on_exit(void)
{
TRACE;
printf("\nAll connects: %lld\n", connections_count);
pthread_mutex_unlock(&connections_lock);
pthread_mutex_unlock(&init_connection_lock);
fprintf(stderr, "\nWaiting for close connections...");
int remain = 10; /* Время для ожидания */
do {
pthread_mutex_lock(&connections_lock);
if (0 == connections) {
printf(" done\n");
return;
}
pthread_mutex_unlock(&connections_lock);
sleep(1);
fprintf(stderr, "%d ", --remain);
}
while (remain > 0);
fprintf(stderr, "\n");
DBG_printf("Connections at start freeing: %d\n", connections);
/* Для корректного закрытия в середине инициализации соединения */
pthread_mutex_lock(&init_connection_lock);
close_server_sockfd();
pthread_mutex_unlock(&init_connection_lock);
pthread_mutex_lock(&connections_lock);
free_all_conn();
pthread_mutex_unlock(&connections_lock);
DBG_printf("Connections at close: %d\n", connections);
if (0 != connections) {
fprintf(stderr, "Not all connections were closed (%d)",
connections);
}
}
void TXS_RollBack_HDCP(void)
{
DBG_printf(("\r\nState Rollback: Stop HDCP -> [TXS_Stream]\r\n"));
HDCP_Stop();
pEP932C_Registers->HDCP_Status = 0;
pEP932C_Registers->HDCP_State = 0;
}
void TXS_RollBack_Stream(void)
{
DBG_printf(("\r\nState Rollback: Power Down -> [TXS_Wait_Upstream]\r\n"));
// Power Down
HDMI_Tx_Power_Down();
// Reset HDCP Info
memset(pEP932C_Registers->HDCP_BKSV, 0x00, sizeof(pEP932C_Registers->HDCP_BKSV));
is_HDCP_Info_BKSV_Rdy = 0;
}
void TXS_RollBack_Wait_Upstream(void)
{
DBG_printf(("\r\nState Rollback: Reset EDID -> [TXS_Search_EDID]\r\n"));
// Reset EDID
memset(pEP932C_Registers->Readed_EDID, 0xFF, 256);
// Report EDID Change
pEP932C_Registers->Interrupt_Flags |= EP932E_Interrupt_Flags__EDID_CHG;
if(EP932C_GenerateInt && (pEP932C_Registers->Interrupt_Enable & EP932E_Interrupt_Enable__EDID_CHG) ) EP932C_GenerateInt();
ReadEDID_TimeCount = 0;
}
/*${AOs::FlashMgr::SM::Active::Idle} .......................................*/
static QState FlashMgr_Idle(FlashMgr * const me, QEvt const * const e) {
QState status_;
switch (e->sig) {
/* ${AOs::FlashMgr::SM::Active::Idle} */
case Q_ENTRY_SIG: {
/* Clear out all the variables on entry to Idle state. By this point, any error
* feedback should have already happened. */
me->errorCode = ERR_NONE;
me->msgRoute = _DC3_NoRoute;
me->reqProg = false;
memset(&me->fwFlashMetadata, 0, sizeof(me->fwFlashMetadata));
me->currRamTest = _DC3_RAM_TEST_NONE;
me->currRamAddr = 0;
status_ = Q_HANDLED();
break;
}
/* ${AOs::FlashMgr::SM::Active::Idle::FLASH_OP_START} */
case FLASH_OP_START_SIG: {
DBG_printf("FLASH_OP_START\n");
/* Get the metadata and record it. Ignore the status */
me->fwFlashMetadata._imageCrc = ((FWMetaEvt const *)e)->imageCRC;
me->fwFlashMetadata._imageMaj = ((FWMetaEvt const *)e)->imageMaj;
me->fwFlashMetadata._imageMin = ((FWMetaEvt const *)e)->imageMin;
me->fwFlashMetadata._imageSize = ((FWMetaEvt const *)e)->imageSize;
me->fwFlashMetadata._imageType = ((FWMetaEvt const *)e)->imageType;
me->fwFlashMetadata._imageNumPackets = ((FWMetaEvt const *)e)->imageNumPackets;
me->fwFlashMetadata._imageDatetime_len = ((FWMetaEvt const *)e)->imageDatetimeLen;
MEMCPY(
me->fwFlashMetadata._imageDatetime,
((FWMetaEvt const *)e)->imageDatetime,
me->fwFlashMetadata._imageDatetime_len
);
status_ = Q_TRAN(&FlashMgr_PrepFlash);
break;
}
/* ${AOs::FlashMgr::SM::Active::Idle::RAM_TEST_START} */
case RAM_TEST_START_SIG: {
status_ = Q_TRAN(&FlashMgr_DataBusTest);
break;
}
default: {
status_ = Q_SUPER(&FlashMgr_Active);
break;
}
}
return status_;
}
int mem_to_table(TABLE* table,int * buff,int mode) {
int rows,total; int i;Triple *data;
Triple * Qson;
start_table((TABLE *) table,append_operator);
data = &(table)->operators[append_data];
Qson = (Triple *) (buff+2);
rows = Qson[0].pointer; total = 0;
for(i=0;i<rows;i++) {
*data = Qson[i];
DBG_printf("MT%s%c%3d\n",Qson[i].key,Qson[i].link,Qson[i].pointer);
//len = (int) Qson.key; // for blob bind
machine_reset(table->stmt);
bind_code(&(table)->operators[append_operator],table->stmt);
machine_step(table->stmt);
}
return rows;
}
/*${AOs::FlashMgr::SM::Active::BusyRam::DataBusTest} .......................*/
static QState FlashMgr_DataBusTest(FlashMgr * const me, QEvt const * const e) {
QState status_;
switch (e->sig) {
/* ${AOs::FlashMgr::SM::Active::BusyRam::DataBusTest} */
case Q_ENTRY_SIG: {
me->currRamTest = _DC3_RAM_TEST_DATA_BUS;
me->currRamAddr = 0;
me->errorCode = ERR_SDRAM_DATA_BUS_TEST_TIMEOUT;
QEvt *evt = Q_NEW(QEvt, RAM_OP_START_SIG);
QACTIVE_POST(AO_FlashMgr, (QEvt *)(evt), AO_FlashMgr);
status_ = Q_HANDLED();
break;
}
/* ${AOs::FlashMgr::SM::Active::BusyRam::DataBusTest::RAM_OP_START} */
case RAM_OP_START_SIG: {
me->currRamTest = _DC3_RAM_TEST_DATA_BUS;
me->currRamAddr = SDRAM_testDataBus( 0 );
/* ${AOs::FlashMgr::SM::Active::BusyRam::DataBusTest::RAM_OP_START::[Error?]} */
if (0 != me->currRamAddr) {
me->errorCode = ERR_SDRAM_DATA_BUS;
ERR_printf(
"RAM data bus test failed at addr: 0x%08x on pattern: 0x%08x. Error: 0x%08x\n",
SDRAM_BANK_ADDR + 0, me->currRamAddr, me->errorCode
);
status_ = Q_TRAN(&FlashMgr_Idle);
}
/* ${AOs::FlashMgr::SM::Active::BusyRam::DataBusTest::RAM_OP_START::[else]} */
else {
DBG_printf("No RAM Data bus error found.\n");
status_ = Q_TRAN(&FlashMgr_AddrBusTest);
}
break;
}
default: {
status_ = Q_SUPER(&FlashMgr_BusyRam);
break;
}
}
return status_;
}
/*${AOs::FlashMgr::SM::Active::BusyRam::DeviceTest} ........................*/
static QState FlashMgr_DeviceTest(FlashMgr * const me, QEvt const * const e) {
QState status_;
switch (e->sig) {
/* ${AOs::FlashMgr::SM::Active::BusyRam::DeviceTest} */
case Q_ENTRY_SIG: {
me->currRamTest = _DC3_RAM_TEST_DEV_INT;
me->currRamAddr = 0;
me->errorCode = ERR_SDRAM_DEVICE_INTEGRITY_TEST_TIMEOUT;
QEvt *evt = Q_NEW(QEvt, RAM_OP_START_SIG);
QACTIVE_POST(AO_FlashMgr, (QEvt *)(evt), AO_FlashMgr);
status_ = Q_HANDLED();
break;
}
/* ${AOs::FlashMgr::SM::Active::BusyRam::DeviceTest::RAM_OP_START} */
case RAM_OP_START_SIG: {
me->currRamAddr = SDRAM_testDevice(0, RAM_TEST_BLOCK_SIZE );
/* ${AOs::FlashMgr::SM::Active::BusyRam::DeviceTest::RAM_OP_START::[Error?]} */
if (0 != me->currRamAddr) {
me->errorCode = ERR_SDRAM_DEVICE_INTEGRITY;
ERR_printf(
"RAM device bus test failed at addr: 0x%08x. Error: 0x%08x\n",
me->currRamAddr, me->errorCode
);
status_ = Q_TRAN(&FlashMgr_Idle);
}
/* ${AOs::FlashMgr::SM::Active::BusyRam::DeviceTest::RAM_OP_START::[else]} */
else {
me->errorCode = ERR_NONE;
DBG_printf("No RAM device errors found.\n");
status_ = Q_TRAN(&FlashMgr_Idle);
}
break;
}
default: {
status_ = Q_SUPER(&FlashMgr_BusyRam);
break;
}
}
return status_;
}
int mem_to_net(int fd,int *buff,int protocol) {
int rows,len,total; int i;Triple *Qson; char dest[20];
char * key_value;
Qson = (Triple *) (buff+2);
sendx(fd,buff,8,0);
rows = Qson[0].pointer; total = 0;
for(i=0;i<rows;i++) {
key_value = Qson[i].key;
sscanf(key_value,"%4d",&len);
sprintf(dest,"%c%3d%4d",Qson[i].link,Qson[i].pointer,len);
sendx(fd,dest,8,0);
if(protocol = Qson_IO) {
sendx(fd,key_value+4,len/4,0);
if (total = (len & 0x3))
sendx(fd,"___",4-total,0); // keep at four byte boudary
}
else
sendx(fd,key_value+4,len,0);
DBG_printf("MN%s%c%3d%\n",key_value,Qson->link,Qson->pointer);
}
closesocketx(fd);
return 0;
}
int mem_to_file( FILE * dest,int * buff,int mode){
int rows,len,total; int i;Triple *Qson;
char * key_value;
Qson = (Triple *)(buff+2);
fwrite((char *) buff,1,8,dest); // total count
rows = Qson[0].pointer; total = 0;
printf("link again %c\n",Qson[0].link);
for(i=0;i<rows;i++) {
key_value = Qson[i].key;
sscanf(key_value,"%4d",&len);
printf("Link here %d\n",Qson[i].link);
fprintf(dest,"%c%3d%4d",Qson[i].link,Qson[i].pointer,len);
fwrite(key_value,1,len+4,dest);
if (total = (len & 0x3))
fwrite("___",1,4-total,dest); // keep at four byte boudary
if(mode != AF_CONSOLE)
DBG_printf("MF%s%c%3d%\n",key_value,Qson->link,Qson->pointer);
}
if(mode == AF_FILE)
fclose(dest);
return 0;
}
// Simple text file format
int * file_to_mem(FILE *fd) {
int len,rows,i=0,*buff; char * key_value;
char link_pointer[12],total[8];Triple * Qson;
fread(total,1,8,fd);
fread(link_pointer,1,12,fd);
sscanf(link_pointer+1,"%3d",&rows);
buff = (int *) G_malloc(rows*sizeof(Triple)+8);
memcpy(buff,total,8);
Qson = (Triple *) (buff+2);
for(i=0;i<rows;i++) {
if(i)
fread(link_pointer,1,12,fd);
sscanf(link_pointer,"%c%3d%4d",&Qson->link,&Qson->pointer,&len);
key_value = (char *) G_malloc(len+5);
sprintf(key_value,"%4d",len);
fread(key_value+4,1,len,fd); // bytes (from fixed length key values
Qson->key = key_value;
//Qson->key[len+4]=0;
DBG_printf("FM%s%c%3d\n",Qson->key,Qson->link,Qson->pointer);
Qson++;
}
return buff;
}
int table_to_Json(TABLE *t,IO_Structure * to) {
// set some stuf up to restore Json brackets
struct {int count;int total;} brk[8];int cur; char prev;
int len; int i,rows;
Triple Qin;char tmp[9];
Code stmt;
cur = 0;
start_table(t,select_operator);
stmt = get_ready_stmt();
// peek at the header
i = machine_step_fetch(&Qin,0);
rows = Qin.pointer;
prev=Qin.link;
brk[cur].total = Qin.pointer; brk[cur].count = 0;
for(i=0;i<rows;i++) {
if(i) machine_step_fetch(&Qin,0);
len = machine_key_len(stmt);
// mke a stream json
send_(Qin.key,len,to);
send_(tmp,sprintf(tmp,"%c",Qin.link),to);
// restor brckets
brk[cur].count++;
while(brk[cur].count == brk[cur].total) {
cur--;brk[cur].count += brk[cur+1].count;
send_("}",1,to);
}
if((Qin.pointer > 1) && (prev != '.') && ( prev != ',')) {
cur++; brk[cur].count = 0;brk[cur].total = Qin.pointer;
send_("{",1,to);
}
prev=Qin.link;
}
DBG_printf("TJ%s%c%3d\n",Qin.key,Qin.link,Qin.pointer);
return 0;
}
void Udp::setLogging( LogStub *log )
{
this->m_pLog = log;
DBG_printf(this->m_pLog,"Logging setup successful.");
}
/*${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::ErasingSector} ........*/
static QState FlashMgr_ErasingSector(FlashMgr * const me, QEvt const * const e) {
QState status_;
switch (e->sig) {
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::ErasingSector} */
case Q_ENTRY_SIG: {
QTimeEvt_rearm( /* Re-arm timer on entry */
&me->flashOpTimerEvt,
SEC_TO_TICKS( LL_MAX_TOUT_SEC_FLASH_SECTOR_ERASE )
);
DBG_printf("Attempting to erase sector addr 0x%08x\n",
me->flashSectorsToErase[ me->flashSectorsToEraseIndex ]);
/* Use a separate status variable so if a timeout occurs, the timeout error won't get
* overwritten */
me->errorCode = FLASH_eraseSector(
me->flashSectorsToErase[ me->flashSectorsToEraseIndex ]
);
/* Post event to move to the next step only AFTER the blocking call to
* FLASH_eraseSector() returns */
QEvt *evt = Q_NEW(QEvt, FLASH_NEXT_STEP_SIG);
QACTIVE_POST(AO_FlashMgr, (QEvt *)(evt), AO_FlashMgr);
status_ = Q_HANDLED();
break;
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::ErasingSector} */
case Q_EXIT_SIG: {
QTimeEvt_disarm(&me->flashOpTimerEvt); /* Disarm timer on exit */
status_ = Q_HANDLED();
break;
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::ErasingSector::FLASH_NEXT_STEP} */
case FLASH_NEXT_STEP_SIG: {
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::ErasingSector::FLASH_NEXT_STEP::[EraseOK?]} */
if (ERR_NONE == me->errorCode) {
DBG_printf("Successfully erased sector addr 0x%08x\n",
me->flashSectorsToErase[ me->flashSectorsToEraseIndex ]);
me->flashSectorsToEraseIndex += 1; /* increment the index into the erase array */
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::ErasingSector::FLASH_NEXT_STEP::[EraseOK?]::[MoreToErase?]} */
if (me->flashSectorsToEraseIndex < me->flashSectorsToEraseNum) {
status_ = Q_TRAN(&FlashMgr_ErasingSector);
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::ErasingSector::FLASH_NEXT_STEP::[EraseOK?]::[else]} */
else {
status_ = Q_TRAN(&FlashMgr_WaitingForFWData);
}
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::ErasingSector::FLASH_NEXT_STEP::[else]} */
else {
WRN_printf("Failed to erase flash sector 0x%08x\n", me->flashSectorsToErase[ me->flashSectorsToEraseIndex ]);
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::ErasingSector::FLASH_NEXT_STEP::[else]::[retry?]} */
if (me->retryCurr < MAX_FLASH_RETRIES) {
me->retryCurr += 1; /* Increment retry counter */
WRN_printf("Attempting operation again (retry %d out of %d)...\n", me->retryCurr, MAX_FLASH_RETRIES);
status_ = Q_TRAN(&FlashMgr_ErasingSector);
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::ErasingSector::FLASH_NEXT_STEP::[else]::[else]} */
else {
ERR_printf("No more retries, aborting with error: 0x%08x\n", me->errorCode);
status_ = Q_TRAN(&FlashMgr_Idle);
}
}
break;
}
default: {
status_ = Q_SUPER(&FlashMgr_PrepFlash);
break;
}
}
return status_;
}
/**
* Цикл обработки входящий соединений.
*
* @param[in] server_sockfd сокет, принимающий входящие соединения.
* @param[in] handler обработчик соединения.
* @param статус завершения.
*/
int
connections_loop(IN int server_sockfd,
IN void * (*_handler)(struct connection_vars_t*))
{
int status = 0;
while (true) {
TRACE;
#ifdef DEBUG
pthread_mutex_lock(&connections_lock);
printf("Connections: %d\n", connections);
printf("Free places: %d\n", get_free_places());
if (HANDLE_CONNS_COUNT != (connections + get_free_places())) {
fprintf(stderr, "Something went wrong\n");
TRACE;
dump_connections();
pthread_mutex_unlock(&connections_lock);
return -EINVAL;
}
pthread_mutex_unlock(&connections_lock);
#endif
struct sockaddr_in client_addr;
memset(&client_addr, 0, sizeof(struct sockaddr_in));
socklen_t client_addr_size = sizeof(struct sockaddr_in);
int client_sockfd = accept(
server_sockfd,
(struct sockaddr*) &client_addr,
&client_addr_size
);
CHECK_ERRNO(client_sockfd, "Accept connection");
/* Проверка лимита соединений для IP */
pthread_mutex_lock(&connections_lock);
int ip_conn = get_ip_conn(client_addr.sin_addr.s_addr);
pthread_mutex_unlock(&connections_lock);
if (ip_conn > MAX_IP_CONN) {
TRACE;
/* Отправка клиенту сообщение о лимите */
send(client_sockfd, IP_CONN_LIMIT_MSG,
sizeof(IP_CONN_LIMIT_MSG), 0);
shutdown(client_sockfd, SHUT_RDWR);
close(client_sockfd);
continue;
}
/* Проверка общего лимита соединений. */
pthread_mutex_lock(&connections_lock);
int is_limit = connections > HANDLE_CONNS_COUNT - 1;
pthread_mutex_unlock(&connections_lock);
if (is_limit) {
TRACE;
/* Отправка клиенту сообщение о лимите */
send(client_sockfd, ALL_CONN_LIMIT_MSG,
sizeof(ALL_CONN_LIMIT_MSG), 0);
shutdown(client_sockfd, SHUT_RDWR);
close(client_sockfd);
continue;
}
pthread_mutex_lock(&init_connection_lock);
++connections_count;
DBG_printf("Connect: %lld\n", connections_count);
pthread_t client_thread;
struct connection_vars_t* connection =
calloc(sizeof(struct connection_vars_t), 1);
if (NULL == connection) {
TRACE;
fprintf(stderr, "Allocation failed\n");
exit(EXIT_FAILURE);
}
TRACE;
connection->sockfd = client_sockfd;
connection->addr = client_addr;
connection->n = connections_count;
TRACE;
status = pthread_create(
&client_thread,
NULL,
(void * (*)(void*)) _handler,
(void*) connection
);
CHECK_ERRNO(status, "Create handle connection thread");
pthread_detach(client_thread);
CHECK_ERRNO(status, "Detach connection thread");
pthread_mutex_lock(&connections_lock);
if (save_conn(connection)) {
/* Опасная ситуация */
fprintf(stderr, "No free place for connection\n");
TRACE;
dump_connection_vars(connection);
dump_connections();
pthread_mutex_unlock(&connections_lock);
pthread_mutex_unlock(&init_connection_lock);
exit(EXIT_FAILURE);
}
pthread_mutex_unlock(&connections_lock);
pthread_mutex_unlock(&init_connection_lock);
}
}
unsigned char EP932Controller_Task(void)
{
//DBG_printf(("EP932 EP932Controller_Task \r\n"));
// Read Interrupt Flag and updat the internal information
ReadInterruptFlags();
// Polling Hot-Plug every 80ms
if(HTP_TimeCount > 80/EP932C_TIMER_PERIOD) {
HTP_TimeCount = 0;
ConnectionState = HDMI_Tx_HTPLG();
HTPLG_NOW = ConnectionState;
if(HTPLG_LAST != HTPLG_NOW)
{
HTPLG_LAST = HTPLG_NOW;
if(HTPLG_NOW == 0)
{
DBG_printf(("Without HotPlug\r\n"));
EP_HDMI_DumpMessage();
}
else
{
DBG_printf(("Detect HotPlug \r\n"));
}
}
is_Hot_Plug = (ConnectionState == 1)? 1:0;
if(is_Connected != ((ConnectionState)?1:0) ) {
if(HP_ChangeCount++ >= 1) { // Accept continuous 1 error = 1*80 ms = 80 ms (Skip when low period < 80 ms)
HP_ChangeCount = 0;
is_Connected = ((ConnectionState)?1:0);
}
}
else {
HP_ChangeCount = 0;
}
if(is_Hot_Plug) {
pEP932C_Registers->System_Status |= EP932E_System_Status__HTPLG;
}
else {
pEP932C_Registers->System_Status &= ~EP932E_System_Status__HTPLG;
}
is_ReceiverSense = HDMI_Tx_RSEN(); // Only valid when TX is powered on
if(TX_State > TXS_Wait_Upstream) { // Powered Up and have Input
// Update RSEN
if(is_ReceiverSense) {
pEP932C_Registers->System_Status |= EP932E_System_Status__RSEN;
}
else {
pEP932C_Registers->System_Status &= ~EP932E_System_Status__RSEN;
}
RSEN_ChangeCount = 0;
// Read HSO VSO POL information
EP932_Reg_Read(EP932_General_Control_4, DDC_Data, 1);
Video_Params.HVPol = 0;//DDC_Data[0] & (EP932_DE_Control__VSO_POL | EP932_DE_Control__HSO_POL);
}
else {
if(RSEN_ChangeCount++ >= 8) { // Accept continuous 8 error = 8*80 ms = 640 ms (Skip when low period < 640 ms)
RSEN_ChangeCount = 0;
pEP932C_Registers->System_Status &= ~EP932E_System_Status__RSEN;
}
}
}
//
// Update EP932 Registers according to the System Process
//
//DBG_printf(("TX_State=%d \n",TX_State));
switch(TX_State) {
case TXS_Search_EDID:
if(is_Connected) {
if(ReadEDID_TimeCount > 200/EP932C_TIMER_PERIOD) {
unsigned char EDID_DDC_Status = 0;
// Confirm Hot-Plug (time-out after 1s)
if(!is_Hot_Plug) {
if(ReadEDID_TimeCount <= 1000/EP932C_TIMER_PERIOD) break;
DBG_printf(("WARNING: EDID detected without Hot-Plug for 1s\r\n"));
}
// Read EDID
DBG_printf(("\r\nState Transist: Read EDID -> [TXS_Wait_Upstream] 0x%x\r\n",pEP932C_Registers->System_Configuration));
memset(pEP932C_Registers->Readed_EDID, 0xFF, 256);
if(!(pEP932C_Registers->System_Configuration & EP932E_System_Configuration__FORCE_HDMI_CAP)){
EDID_DDC_Status = Downstream_Rx_read_EDID(pEP932C_Registers->Readed_EDID);
if(EDID_DDC_Status) {
//if(EDID_DDC_Status == EDID_STATUS_NoAct) {
if(EDID_DDC_Status != EDID_STATUS_ChecksumError) {
DBG_printf(("WARNING: EDID read failed 0x%02X\r\n", (int)EDID_DDC_Status));
if(ReadEDID_TimeCount <= 500/EP932C_TIMER_PERIOD) break;
}
}
}
ReadEDID_TimeCount = 0;
// Set Output
if(pEP932C_Registers->System_Configuration & EP932E_System_Configuration__FORCE_HDMI_CAP) {
is_Cap_HDMI = 1;
}
else {
is_Cap_HDMI = EDID_GetHDMICap(pEP932C_Registers->Readed_EDID);
}
if(is_Cap_HDMI) {
DBG_printf(("Support HDMI"));
// Default Capability
is_Cap_YCC444 = is_Cap_YCC422 = 0;
pEP932C_Registers->EDID_ASFreq = 0x07;
pEP932C_Registers->EDID_AChannel = 1;
pEP932C_Registers->EDID_VideoDataAddr = 0x00;
pEP932C_Registers->EDID_AudioDataAddr = 0x00;
pEP932C_Registers->EDID_SpeakerDataAddr = 0x00;
pEP932C_Registers->EDID_VendorDataAddr = 0x00;
if(!EDID_DDC_Status) {
if(pEP932C_Registers->Readed_EDID[131] & 0x20) { // Support YCC444
is_Cap_YCC444 = 1;
DBG_printf((" YCC444"));
}
if(pEP932C_Registers->Readed_EDID[131] & 0x10) { // Support YCC422
is_Cap_YCC422 = 1;
DBG_printf((" YCC422"));
}
DBG_printf(("\r\n"));
pEP932C_Registers->EDID_ASFreq = EDID_GetPCMFreqCap(pEP932C_Registers->Readed_EDID);
DBG_printf(("EDID ASFreq = 0x%02X\r\n",(int)pEP932C_Registers->EDID_ASFreq));
pEP932C_Registers->EDID_AChannel = EDID_GetPCMChannelCap(pEP932C_Registers->Readed_EDID);
DBG_printf(("EDID AChannel = 0x%02X\r\n",(int)pEP932C_Registers->EDID_AChannel));
pEP932C_Registers->EDID_VideoDataAddr = EDID_GetDataBlockAddr(pEP932C_Registers->Readed_EDID, 0x40);
pEP932C_Registers->EDID_AudioDataAddr = EDID_GetDataBlockAddr(pEP932C_Registers->Readed_EDID, 0x20);
pEP932C_Registers->EDID_SpeakerDataAddr = EDID_GetDataBlockAddr(pEP932C_Registers->Readed_EDID, 0x80);
pEP932C_Registers->EDID_VendorDataAddr = EDID_GetDataBlockAddr(pEP932C_Registers->Readed_EDID, 0x60);
}
}
else {
DBG_printf(("Support DVI RGB only\r\n"));
is_Cap_YCC444 = is_Cap_YCC422 = 0;
pEP932C_Registers->EDID_ASFreq = pEP932C_Registers->EDID_AChannel = 0;
}
if(is_Cap_HDMI)
pEP932C_Registers->EDID_Status = EDID_DDC_Status | EP932E_EDID_Status__HDMI;
else
pEP932C_Registers->EDID_Status = EDID_DDC_Status;
DBG_printf(("Support Max Audio Channel %d\r\n", (int)pEP932C_Registers->EDID_AChannel+1));
DBG_printf(("Support Audio Freq 0x%02X\r\n", (int)pEP932C_Registers->EDID_ASFreq));
// Report EDID Change
pEP932C_Registers->Interrupt_Flags |= EP932E_Interrupt_Flags__EDID_CHG;
if(EP932C_GenerateInt && (pEP932C_Registers->Interrupt_Enable & EP932E_Interrupt_Enable__EDID_CHG) ) EP932C_GenerateInt();
TX_State = TXS_Wait_Upstream;
}
}
else {
pEP932C_Registers->EDID_Status = EDID_STATUS_NoAct;
ReadEDID_TimeCount = 0;
}
break;
case TXS_Wait_Upstream:
if(!is_Connected) {
TXS_RollBack_Wait_Upstream();
TX_State = TXS_Search_EDID;
}
else if(!(pEP932C_Registers->Power_Control & (EP932E_Power_Control__PD_HDMI | EP932E_Power_Control__PD_TOT)) ) {
DBG_printf(("\r\nState Transist: Power Up -> [TXS_Stream]\r\n"));
// Power Up
HDMI_Tx_Power_Up();
TX_State = TXS_Stream;
}
else {
// Check Force HDMI bit
if(!is_Cap_HDMI) {
if(pEP932C_Registers->System_Configuration & EP932E_System_Configuration__FORCE_HDMI_CAP) {
TXS_RollBack_Wait_Upstream();
TX_State = TXS_Search_EDID;
}
}
}
break;
case TXS_Stream:
#if defined(Enable_HDCP)
if(!is_HDCP_Info_BKSV_Rdy && is_ReceiverSense && is_Hot_Plug) {
// Get HDCP Info
if(!Downstream_Rx_read_BKSV(pEP932C_Registers->HDCP_BKSV)) {
pEP932C_Registers->HDCP_Status = EP932E_HDCP_Status__BKSV;
}
pEP932C_Registers->HDCP_BCAPS3[0] = Downstream_Rx_BCAPS();
is_HDCP_Info_BKSV_Rdy = 1;
}
#endif
if(!is_Connected) {
TXS_RollBack_Stream();
TXS_RollBack_Wait_Upstream();
TX_State = TXS_Search_EDID;
}
else if(pEP932C_Registers->Power_Control & (EP932E_Power_Control__PD_HDMI | EP932E_Power_Control__PD_TOT) ) {
pEP932C_Registers->Power_Control |= EP932E_Power_Control__PD_HDMI;
TXS_RollBack_Stream();
TX_State = TXS_Wait_Upstream;
}
#if defined(Enable_HDCP)
else if(!((pEP932C_Registers->System_Configuration & EP932E_System_Configuration__HDCP_DIS) || is_VideoChanging) && is_ReceiverSense) {
// Enable mute for transmiter video and audio
HDMI_Tx_Mute_Enable();
DBG_printf(("\r\nState Transist: Start HDCP -> [TXS_HDCP]\r\n"));
TX_State = TXS_HDCP;
}
#endif
break;
#if defined(Enable_HDCP)
case TXS_HDCP:
if(!is_Connected || !is_Hot_Plug) {
TXS_RollBack_HDCP();
TXS_RollBack_Stream();
TXS_RollBack_Wait_Upstream();
TX_State = TXS_Search_EDID;
}
else if(pEP932C_Registers->Power_Control & (EP932E_Power_Control__PD_HDMI | EP932E_Power_Control__PD_TOT) ) {
pEP932C_Registers->Power_Control |= EP932E_Power_Control__PD_HDMI;
TXS_RollBack_HDCP();
TXS_RollBack_Stream();
TX_State = TXS_Wait_Upstream;
}
else if((pEP932C_Registers->System_Configuration & EP932E_System_Configuration__HDCP_DIS) || is_VideoChanging) {
TXS_RollBack_HDCP();
TX_State = TXS_Stream;
}
else {
pEP932C_Registers->HDCP_State = HDCP_Authentication_Task(is_ReceiverSense && is_Hot_Plug);
pEP932C_Registers->HDCP_Status = HDCP_Get_Status();
}
break;
#endif
}
//
// Update EP932 Registers for any time
//
// Mute Control
if( (pEP932C_Registers->System_Configuration & EP932E_System_Configuration__AUDIO_DIS) || (TX_State < TXS_Stream) || is_VideoChanging || is_AudioChanging ) {
HDMI_Tx_AMute_Enable();
}
else {
HDMI_Tx_AMute_Disable();
}
if( (pEP932C_Registers->System_Configuration & EP932E_System_Configuration__VIDEO_DIS) || (TX_State < TXS_Stream) || is_VideoChanging ) {
HDMI_Tx_VMute_Enable();
}
else {
HDMI_Tx_VMute_Disable();
}
// HDMI Mode
if(!is_Cap_HDMI || (pEP932C_Registers->System_Configuration & EP932E_System_Configuration__HDMI_DIS) ) {
HDMI_Tx_DVI(); // Set to DVI mode (The Info Frame and Audio Packets would not be send)
}
else {
HDMI_Tx_HDMI(); // Set to HDMI mode
}
++Process_Dispatch_ID;
if(Process_Dispatch_ID > 2) Process_Dispatch_ID = 0;
switch(Process_Dispatch_ID) {
case 0:
//
// Update Video Params
//
// Video Interface
Video_Params.Interface = pEP932C_Registers->Video_Interface[0];
// Video Timing
if(pEP932C_Registers->Video_Input_Format[0]) {
// Manul set the Video Timing
if(pEP932C_Registers->Video_Input_Format[0] < 128) {
Video_Params.VideoSettingIndex = pEP932C_Registers->Video_Input_Format[0];
}
else {
Video_Params.VideoSettingIndex = pEP932C_Registers->Video_Input_Format[0] - (128 - EP932_VDO_Settings_IT_Start);
}
}
// Select Sync Mode
Video_Params.SyncMode = (pEP932C_Registers->Video_Interface[1] & EP932E_Video_Interface_Setting_1__SYNC) >> 2;
// Select Color Space
switch(pEP932C_Registers->Video_Interface[1] & EP932E_Video_Interface_Setting_1__COLOR) {
default:
case EP932E_Video_Interface_Setting_1__COLOR__Auto:
switch(Video_Params.VideoSettingIndex) {
case 4: case 5: case 16: case 19: case 20: case 31: case 32:
case 33: case 34: case 39: case 40: case 41: case 46: case 47: // HD Timing
Video_Params.ColorSpace = COLORSPACE_709;
break;
default:
if(Video_Params.VideoSettingIndex && Video_Params.VideoSettingIndex < EP932_VDO_Settings_IT_Start) { // SD Timing
Video_Params.ColorSpace = COLORSPACE_601;
}
else { // IT Timing
Video_Params.ColorSpace = COLORSPACE_709;
}
}
break;
case EP932E_Video_Interface_Setting_1__COLOR__601:
Video_Params.ColorSpace = COLORSPACE_601;
break;
case EP932E_Video_Interface_Setting_1__COLOR__709:
Video_Params.ColorSpace = COLORSPACE_709;
break;
}
// Set Input Format
switch(pEP932C_Registers->Video_Interface[1] & EP932E_Video_Interface_Setting_1__VIN_FMT) {
default:
case EP932E_Video_Interface_Setting_1__VIN_FMT__RGB:
Video_Params.FormatIn = COLORFORMAT_RGB;
Video_Params.FormatOut = COLORFORMAT_RGB;
break;
case EP932E_Video_Interface_Setting_1__VIN_FMT__YCC444:
Video_Params.FormatIn = COLORFORMAT_YCC444;
if(is_Cap_YCC444) {
Video_Params.FormatOut = COLORFORMAT_YCC444;
}
else if(is_Cap_YCC422) {
Video_Params.FormatOut = COLORFORMAT_YCC422;
}
else {
Video_Params.FormatOut = COLORFORMAT_RGB;
}
break;
case EP932E_Video_Interface_Setting_1__VIN_FMT__YCC422:
Video_Params.FormatIn = COLORFORMAT_YCC422;
if(is_Cap_YCC444) {
Video_Params.FormatOut = COLORFORMAT_YCC444;
}
else if(is_Cap_YCC422) {
Video_Params.FormatOut = COLORFORMAT_YCC422;
}
else {
Video_Params.FormatOut = COLORFORMAT_RGB;
}
break;
}
//add by eric.lu
// Set Output Format
switch(pEP932C_Registers->Video_Output_Format) {
default:
case 0: // Auto, don't need change setting.
break;
case 1: // Force to YUV444 output format
Video_Params.FormatOut = COLORFORMAT_YCC444;
break;
case 2: // Force to YUV422 output format
Video_Params.FormatOut = COLORFORMAT_YCC422;
break;
case 3: // Force to RGB444 output format
Video_Params.FormatOut = COLORFORMAT_RGB;
break;
}
// end of add
// DVI mode settings overwrite
if(!is_Cap_HDMI || (pEP932C_Registers->System_Configuration & EP932E_System_Configuration__HDMI_DIS) ) {
Video_Params.FormatOut = COLORFORMAT_RGB;
}
// AFAR
Video_Params.AFARate = ((pEP932C_Registers->Video_Input_Format[1] & EP932E_Video_Input_Format_1__AFAR) >> 4) | 0x08;
// add by eric.lu
// SCAN
Video_Params.SCAN = (pEP932C_Registers->Video_Input_Format[1] & EP932E_Video_Input_Format_1__SCAN);
// end of add
// Video Change
if(memcmp(&Video_Params, &pEP932C_Registers->Video_Params_Backup, sizeof(VDO_PARAMS)) != 0) {
if(memcmp(&Video_Params, &pEP932C_Registers->Video_Params_Backup, 6) != 0) {
is_TimingChanging = 1;
}
// DBG_printf(("Video_Params new: interface 0x%02X, Vindex 0x%02X, HV 0x%02X, mode 0x%02X, Fin 0x%02X, Fout 0x%02X, color 0x%02X, AFAR 0x%02X\r\n",(int)Video_Params.Interface, (int)Video_Params.VideoSettingIndex, (int)Video_Params.HVPol ,(int)Video_Params.SyncMode, (int)Video_Params.FormatIn, (int)Video_Params.FormatOut, (int)Video_Params.ColorSpace, (int)Video_Params.AFARate));
// DBG_printf(("Video_Params old: interface 0x%02X, Vindex 0x%02X, HV 0x%02X, mode 0x%02X, Fin 0x%02X, Fout 0x%02X, color 0x%02X, AFAR 0x%02X\r\n",(int)pEP932C_Registers->Video_Params_Backup.Interface, (int)pEP932C_Registers->Video_Params_Backup.VideoSettingIndex, (int)pEP932C_Registers->Video_Params_Backup.HVPol ,(int)pEP932C_Registers->Video_Params_Backup.SyncMode, (int)pEP932C_Registers->Video_Params_Backup.FormatIn, (int)pEP932C_Registers->Video_Params_Backup.FormatOut, (int)pEP932C_Registers->Video_Params_Backup.ColorSpace, (int)pEP932C_Registers->Video_Params_Backup.AFARate));
pEP932C_Registers->Video_Params_Backup = Video_Params;
VideoChg_TimeCount = 0;
is_VideoChanging = 1;
}
// Video Change Debouncing
if(is_VideoChanging) {
if(VideoChg_TimeCount > AV_STABLE_TIME/EP932C_TIMER_PERIOD) {
DBG_printf(("### VideoChanging \r\n"));
if(is_TimingChanging)
EP932Controller_Reset();
HDMI_Tx_Video_Config(&Video_Params);
if(is_TimingChanging) {
if(!is_AudioChanging)
HDMI_Tx_Audio_Config(&Audio_Params);
}
is_TimingChanging = 0;
is_VideoChanging = 0;
VideoChg_TimeCount = 0;
// Report Video Change
pEP932C_Registers->Interrupt_Flags |= EP932E_Interrupt_Flags__VIDEO_CHG;
if(EP932C_GenerateInt && (pEP932C_Registers->Interrupt_Enable & EP932E_Interrupt_Enable__VIDEO_CHG) ) EP932C_GenerateInt();
}
}
break;
case 1:
//
// Update Audio Params
//
Audio_Params.Interface = pEP932C_Registers->Audio_Interface & 0x0F; // IIS, WS_M, WS_POL, SCK_POL
Audio_Params.VideoSettingIndex = Video_Params.VideoSettingIndex;
// Update Audio Channel Number
if(EP932_VDO_Settings[Video_Params.VideoSettingIndex].Pix_Freq_Type <= PIX_FREQ_27027KHz) {
Audio_Params.ChannelNumber = 1;
}
else {
Audio_Params.ChannelNumber = min(((pEP932C_Registers->Audio_Interface & 0x70) >> 4), pEP932C_Registers->EDID_AChannel);
}
// Update VFS
if(Audio_Params.VideoSettingIndex < EP932_VDO_Settings_IT_Start) {
// Pixel Clock Type shift (59.94/60)
Audio_Params.VFS = (pEP932C_Registers->Video_Input_Format[1] & EP932E_Video_Input_Format_1__VIF)? 1:0;
}
else {
Audio_Params.VFS = 0;
}
Audio_Params.NoCopyRight = (pEP932C_Registers->Audio_Input_Format & EP932E_Audio_Input_Format__NoCopyRight)?1:0;
// Write Frequency info (Use ADO_FREQ or Auto)
switch( pEP932C_Registers->Audio_Input_Format & EP932E_Audio_Input_Format__ADO_FREQ ) {
case EP932E_Audio_Input_Format__ADO_FREQ__32000Hz:
Audio_Params.InputFrequency = ADSFREQ_32000Hz;
// Disable Down Sample
Audio_Params.ADSRate = 0;
break;
default:
case EP932E_Audio_Input_Format__ADO_FREQ__44100Hz:
Audio_Params.InputFrequency = ADSFREQ_44100Hz;
// Disable Down Sample
Audio_Params.ADSRate = 0;
break;
case EP932E_Audio_Input_Format__ADO_FREQ__48000Hz:
Audio_Params.InputFrequency = ADSFREQ_48000Hz;
// Disable Down Sample
Audio_Params.ADSRate = 0;
break;
case EP932E_Audio_Input_Format__ADO_FREQ__88200Hz:
Audio_Params.InputFrequency = ADSFREQ_88200Hz;
if(pEP932C_Registers->EDID_ASFreq & 0x08) { // 88.2kHz
// Disable Down Sample
Audio_Params.ADSRate = 0;
}
else {
// Enable Down Sample 1/2
Audio_Params.ADSRate = 1;
}
break;
case EP932E_Audio_Input_Format__ADO_FREQ__96000Hz:
Audio_Params.InputFrequency = ADSFREQ_96000Hz;
if(pEP932C_Registers->EDID_ASFreq & 0x10) { // 96kHz
// Disable Down Sample
Audio_Params.ADSRate = 0;
}
else {
if(pEP932C_Registers->EDID_ASFreq & 0x04) { // 48kHz
// Enable Down Sample 1/2
Audio_Params.ADSRate = 1;
}
else {
// Enable Down Sample 1/3
Audio_Params.ADSRate = 2;
}
}
break;
case EP932E_Audio_Input_Format__ADO_FREQ__176400Hz:
Audio_Params.InputFrequency = ADSFREQ_176400Hz;
if(pEP932C_Registers->EDID_ASFreq & 0x20) { // 176kHz
// Disable Down Sample
Audio_Params.ADSRate = 0;
}
else {
if(pEP932C_Registers->EDID_ASFreq & 0x08) { // 88.2kHz
// Enable Down Sample 1/2
Audio_Params.ADSRate = 1;
}
else {
// Enable Down Sample 1/4
Audio_Params.ADSRate = 3;
}
}
break;
case EP932E_Audio_Input_Format__ADO_FREQ__192000Hz:
Audio_Params.InputFrequency = ADSFREQ_192000Hz;
if(pEP932C_Registers->EDID_ASFreq & 0x40) { // 192kHz
// Disable Down Sample
Audio_Params.ADSRate = 0;
}
else {
if(pEP932C_Registers->EDID_ASFreq & 0x10) { // 96kHz
// Enable Down Sample 1/2
Audio_Params.ADSRate = 1;
}
else {
// Enable Down Sample 1/4
Audio_Params.ADSRate = 3;
}
}
break;
}
// Audio Change
if(memcmp(&Audio_Params, &pEP932C_Registers->Audio_Params_Backup, sizeof(ADO_PARAMS)) != 0) {
pEP932C_Registers->Audio_Params_Backup = Audio_Params;
AudioChg_TimeCount = 0;
is_AudioChanging = 1;
}
// Audio Change Debouncing
if(is_AudioChanging) {
if(AudioChg_TimeCount > AV_STABLE_TIME/EP932C_TIMER_PERIOD) {
HDMI_Tx_Audio_Config(&Audio_Params);
is_AudioChanging = 0;
AudioChg_TimeCount = 0;
// Report Audio Change
pEP932C_Registers->Interrupt_Flags |= EP932E_Interrupt_Flags__AUDIO_CHG;
if(EP932C_GenerateInt && (pEP932C_Registers->Interrupt_Enable & EP932E_Interrupt_Enable__AUDIO_CHG) ) EP932C_GenerateInt();
}
}
break;
case 2:
// Update TREG
if(pEP932C_Registers->Analog_Test_Control != Backup_Analog_Test_Control) {
Backup_Analog_Test_Control = pEP932C_Registers->Analog_Test_Control;
if(pEP932C_Registers->Analog_Test_Control & 0x01) {
EP932_Reg_Set_Bit(EP932_Color_Space_Control, 0x01);
}
else {
EP932_Reg_Clear_Bit(EP932_Color_Space_Control, 0x01);
}
if(pEP932C_Registers->Analog_Test_Control & 0x02) {
EP932_Reg_Set_Bit(EP932_Color_Space_Control, 0x02);
}
else {
EP932_Reg_Clear_Bit(EP932_Color_Space_Control, 0x02);
}
}
break;
}
// Return the status
if(pEP932C_Registers->Power_Control & (EP932E_Power_Control__PD_HDMI | EP932E_Power_Control__PD_TOT)) {
return EP932C_TASK_Idle;
}
else {
return EP932C_TASK_Pending;
}
}
int system_copy_qson(IO_Structure *from,IO_Structure *to ) {
machine_reset(get_ready_stmt()); // big deal, start fresh
// if the source is memory format
if(from->sa_family == AF_MEMORY) {
if(to->sa_family== AF_FILE) {
FILE *fd;
fd= fopen((char *)to->addr, "w+");
printf("File out %s\n",(char *) to->addr);
mem_to_file(fd,(int *) from->buff,AF_FILE);
fflush(fd);
fclose(fd);
} else if(to->sa_family== AF_CONSOLE) {
mem_to_file(stdout,(int *) from->buff,AF_CONSOLE);
} else if(to->sa_family== AF_TABLE){
TABLE * table;
init_table((char *) to->addr,1,&table);
to->buff = (void*) table;
mem_to_table(table,(int *) from->buff,AF_TABLE);
} else if(to->sa_family== AF_INET)
mem_to_net(to->fd,(int *) from->buff,Qson_IO);
// If the source is a table
}else if(from->sa_family== AF_TABLE ) {
TABLE * table;
if( (to->sa_family== AF_CONSOLE) || ( to->sa_family== AF_INET)) {
printf("Table from %s\n",(char *) from->addr);
init_table((char *) from->addr,0,&table);
to->buff = (void*) table;
table_to_Json(table,to);
}else if(to->sa_family== AF_TABLE)
dup_table((char *) from->addr,(char *) to->addr);
else if(to->sa_family== AF_MEMORY){
init_table((char *) from->addr,0,&table);
to->buff = (void *) table_to_mem(table);
}
// else this might be from the network
} else if ((from->sa_family== AF_INET) ||
(from->sa_family== AF_CONSOLE)|| (from->sa_family== AF_FILE) ) {
if( to->sa_family== AF_TABLE) {
TABLE * table;
DBG_printf("New Table %s\n",(char *) to->addr);
init_table((char *) to->addr,1,&table);
to->buff = (void*) table;
if(from->format == Json_IO)
parser((char *) from->buff,table); // Json from the net
else if (from->format == Qson_IO)
qson_to_table(table,(char *) to->buff,to->count);
}
// source is file
} else if(from->sa_family== AF_FILE) {
if(to->sa_family== AF_MEMORY){
FILE *fd;
printf("File in %s\n",(char *) from->addr);
fd= fopen((char *) from->addr, "r");
to->buff = file_to_mem(fd);
fclose(fd);
}
}
return 0;
}
/*${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash} ....................*/
static QState FlashMgr_WritingFlash(FlashMgr * const me, QEvt const * const e) {
QState status_;
switch (e->sig) {
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash} */
case Q_ENTRY_SIG: {
me->errorCode = ERR_FLASH_WRITE_TIMEOUT; /* Set the timeout error code*/
if ( (me->fwPacketCurr + 1) % 100 == 0 ) {
DBG_printf("Writing FW data packet %d of %d total.\n", me->fwPacketCurr + 1, me->fwFlashMetadata._imageNumPackets);
}
QTimeEvt_rearm( /* Re-arm timer on entry */
&me->flashOpTimerEvt,
SEC_TO_TICKS( LL_MAX_TOUT_SEC_FLASH_DATA_WRITE )
);
uint16_t bytesWritten = 0;
DC3Error_t err = FLASH_writeBuffer(
me->flashAddrCurr,
me->fwDataToFlash,
me->fwDataToFlashLen,
&bytesWritten
);
me->errorCode = err;
if( ERR_NONE != err || bytesWritten != me->fwDataToFlashLen) { /* Error occurred */
WRN_printf("Error flashing data: 0x%08x\n", me->errorCode);
QEvt *evt = Q_NEW(QEvt, FLASH_ERROR_SIG);
QACTIVE_POST(AO_FlashMgr, (QEvt *)(evt), AO_FlashMgr);
} else { /* No errors */
/* Increment addr and counters */
me->flashAddrCurr += bytesWritten;
me->fwPacketCurr += 1;
QEvt *evt = Q_NEW(QEvt, FLASH_DONE_SIG);
QACTIVE_POST(AO_FlashMgr, (QEvt *)(evt), AO_FlashMgr);
}
status_ = Q_HANDLED();
break;
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE} */
case FLASH_DONE_SIG: {
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[MorePackets?]} */
if (me->fwPacketCurr != me->fwPacketExp) {
status_ = Q_TRAN(&FlashMgr_WaitingForFWData);
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[else]} */
else {
DBG_printf("No more fw packets expected\n");
/* Do a check of the FW image and compare all the CRCs and sizes */
CRC_ResetDR();
uint32_t crcCheck = CRC32_Calc(
(uint8_t *)FLASH_APPL_START_ADDR,
me->fwFlashMetadata._imageSize
);
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[else]::[CRCMatch?]} */
if (me->fwFlashMetadata._imageCrc == crcCheck) {
DBG_printf("CRCs of the FW image match, writing metadata...\n");
me->errorCode = FLASH_writeApplSize( me->fwFlashMetadata._imageSize );
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[else]::[CRCMatch?]::[NoError?]} */
if (ERR_NONE == me->errorCode) {
me->errorCode = FLASH_writeApplCRC( me->fwFlashMetadata._imageCrc );
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[else]::[CRCMatch?]::[NoError?]::[NoError?]} */
if (ERR_NONE == me->errorCode) {
me->errorCode = FLASH_writeApplMajVer( me->fwFlashMetadata._imageMaj );
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[else]::[CRCMatch?]::[NoError?]::[NoError?]::[NoError?]} */
if (ERR_NONE == me->errorCode) {
me->errorCode = FLASH_writeApplMinVer( me->fwFlashMetadata._imageMin );
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[else]::[CRCMatch?]::[NoError?]::[NoError?]::[NoError?]::[NoError?]} */
if (ERR_NONE == me->errorCode) {
me->errorCode = FLASH_writeApplBuildDatetime(
(uint8_t *)me->fwFlashMetadata._imageDatetime,
me->fwFlashMetadata._imageDatetime_len
);
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[else]::[CRCMatch?]::[NoError?]::[NoError?]::[NoError?]::[NoError?]::[NoError?]} */
if (ERR_NONE == me->errorCode) {
LOG_printf("Successfully finished upgrading FW!\n");
status_ = Q_TRAN(&FlashMgr_Idle);
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[else]::[CRCMatch?]::[NoError?]::[NoError?]::[NoError?]::[NoError?]::[else]} */
else {
ERR_printf("Unable to write image build datetime after flashing. Error: 0x%08x.\n", me->errorCode);
status_ = Q_TRAN(&FlashMgr_Idle);
}
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[else]::[CRCMatch?]::[NoError?]::[NoError?]::[NoError?]::[else]} */
else {
ERR_printf("Unable to write image Minor Version after flashing. Error: 0x%08x.\n", me->errorCode);
status_ = Q_TRAN(&FlashMgr_Idle);
}
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[else]::[CRCMatch?]::[NoError?]::[NoError?]::[else]} */
else {
ERR_printf("Unable to write image Major Version after flashing. Error: 0x%08x.\n", me->errorCode);
status_ = Q_TRAN(&FlashMgr_Idle);
}
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[else]::[CRCMatch?]::[NoError?]::[else]} */
else {
ERR_printf("Unable to write image CRC after flashing. Error: 0x%08x.\n", me->errorCode);
status_ = Q_TRAN(&FlashMgr_Idle);
}
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[else]::[CRCMatch?]::[else]} */
else {
ERR_printf("Unable to write image size after flashing. Error: 0x%08x.\n", me->errorCode);
status_ = Q_TRAN(&FlashMgr_Idle);
}
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_DONE::[else]::[else]} */
else {
me->errorCode = ERR_FLASH_INVALID_IMAGE_CRC_AFTER_FLASH;
ERR_printf("CRC check failed after flash. Error: 0x%08x.\n", me->errorCode);
ERR_printf("Expected : 0x%08x\n", me->fwFlashMetadata._imageCrc);
ERR_printf("Calculated: 0x%08x\n", crcCheck);
status_ = Q_TRAN(&FlashMgr_Idle);
}
}
break;
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_ERROR} */
case FLASH_ERROR_SIG: {
WRN_printf("FLASH_ERROR\n");
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_ERROR::[RetriesLeft?]} */
if (me->retryCurr < MAX_FLASH_RETRIES) {
LOG_printf("Retrying to flash packet, retry %d out of %d max\n", me->retryCurr, MAX_FLASH_RETRIES);
status_ = Q_TRAN(&FlashMgr_WritingFlash);
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::WritingFlash::FLASH_ERROR::[else]} */
else {
ERR_printf("No more retries\n");
status_ = Q_TRAN(&FlashMgr_Idle);
}
break;
}
default: {
status_ = Q_SUPER(&FlashMgr_BusyFlash);
break;
}
}
return status_;
}
int main(void) {
uint16_t i = 0;
OscInit();
AnalogInit();
OutputInit();
PPSInit();
Timing_Init();
UART_DMA_Init();
UI_LED_Initialize();
for (i=0; i<UI_LED_Count; i++) {
UI_LED_SetState(UI_LED_List[i], LED_On);
}
UI_LED_Update();
DBG_printf("\r\n");
DBG_printf("\2330;36mCalsol Datalogger v%u.%u (alpha)\23337m", VERSION_MAJ, VERSION_MIN);
DBG_printf("\23336m Built %s %s with C30 ver %i\23337m", __DATE__, __TIME__, __C30_VERSION__);
DBG_DATA_printf("\23336mDevice reset:%s%s%s%s%s%s%s%s\23337m",
(RCONbits.TRAPR? " Trap" : ""),
(RCONbits.IOPUWR? " IllegalOpcode/UninitializedW" : ""),
(RCONbits.CM? " ConfigMismatch" : ""),
(RCONbits.EXTR? " ExternalReset" : ""),
(RCONbits.SWR? " SoftwareReset" : ""),
(RCONbits.WDTO? " WatchdogTimeout" : ""),
(RCONbits.BOR? " BrownOutReset" : ""),
(RCONbits.POR? " PowerOnReset" : "")
);
ECAN_Init();
ECAN_Config();
C1FCTRLbits.FSA = 4; // FIFO starts
C1FEN1 = 0;
ECAN_SetStandardFilter(0, 0x00, 0, 15);
ECAN_SetStandardMask(0, 0x00);
ECAN_SetMode(ECAN_MODE_OPERATE);
ECAN_SetupDMA();
UI_Switch_Update();
if (UI_Switch_GetTest()) {
DBG_printf("Entering test mode");
UI_LED_SetState(&UI_LED_Fault, LED_Blink);
while (UI_Switch_GetTest()) {
UI_LED_Update();
UI_Switch_Update();
}
UI_LED_SetState(&UI_LED_Fault, LED_Off);
UI_LED_Update();
}
for (i=0; i<UI_LED_Count; i++) {
UI_LED_SetState(UI_LED_List[i], LED_Off);
}
DBG_printf("Initialization complete");
Datalogger_Init();
while(1) {
Datalogger_Loop();
}
}
/*${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash} .......................*/
static QState FlashMgr_PrepFlash(FlashMgr * const me, QEvt const * const e) {
QState status_;
switch (e->sig) {
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash} */
case Q_ENTRY_SIG: {
/* Self post an event to keep going. The reason this is done is so that we can use
* common error handling of the parent state to report errors back to CommMgr instead
* of having to manually port events whenever an error occurs.*/
QEvt *evt = Q_NEW(QEvt, FLASH_NEXT_STEP_SIG);
QACTIVE_POST(AO_FlashMgr, (QEvt *)(evt), AO_FlashMgr);
status_ = Q_HANDLED();
break;
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::FLASH_NEXT_STEP} */
case FLASH_NEXT_STEP_SIG: {
DBG_printf("FLASH_NEXT_STEP\n");
LOG_printf("Extracted FW image metadata:\n");
LOG_printf("CRC: 0x%08x\n", me->fwFlashMetadata._imageCrc);
LOG_printf("Maj: %02d\n", me->fwFlashMetadata._imageMaj);
LOG_printf("Min: %02d\n", me->fwFlashMetadata._imageMin);
LOG_printf("Size: %d\n", me->fwFlashMetadata._imageSize);
LOG_printf("Type: %d\n", me->fwFlashMetadata._imageType);
LOG_printf("Datetime: %s\n", me->fwFlashMetadata._imageDatetime);
LOG_printf("Number of packets: %d\n", me->fwFlashMetadata._imageNumPackets);
/* Do some sanity checking on the FW image metadata */
me->errorCode = FLASH_validateMetadata(&(me->fwFlashMetadata));
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::FLASH_NEXT_STEP::[MetadataValid?]} */
if (ERR_NONE == me->errorCode) {
DBG_printf("Finding flash sectors to erase.\n");
me->errorCode = FLASH_getSectorsToErase(
me->flashSectorsToErase,
&(me->flashSectorsToEraseNum),
ADDR_FLASH_SECTORS,
me->fwFlashMetadata._imageType,
me->fwFlashMetadata._imageSize
);
/* Set the start address which will get used later when the fw packets start coming in*/
if (me->fwFlashMetadata._imageType == _DC3_Application ) {
me->flashAddrCurr = FLASH_APPL_START_ADDR;
me->fwPacketExp = me->fwFlashMetadata._imageNumPackets;
DBG_printf("Expecting %d FW data packets\n", me->fwPacketExp);
} else {
me->errorCode = ERR_FLASH_IMAGE_TYPE_INVALID;
ERR_printf("FW image type %d currently not supported for FW upgrades, error: 0x%08x\n",
me->fwFlashMetadata._imageType, me->errorCode);
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::FLASH_NEXT_STEP::[MetadataValid?]::[SectorsValid?]} */
if (ERR_NONE == me->errorCode && me->flashSectorsToEraseNum > 1) {
LOG_printf("List of %d sectors (by address) to erase:\n", me->flashSectorsToEraseNum);
for( uint8_t i=0; i < me->flashSectorsToEraseNum; i++ ) {
LOG_printf("Sector at address at 0x%08x\n", me->flashSectorsToErase[i]);
}
status_ = Q_TRAN(&FlashMgr_ErasingSector);
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::FLASH_NEXT_STEP::[MetadataValid?]::[else]} */
else {
ERR_printf("Unable to get a list of sectors to erase. Error: 0x%08x\n", me->errorCode);
status_ = Q_TRAN(&FlashMgr_Idle);
}
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::FLASH_NEXT_STEP::[else]} */
else {
ERR_printf("FW image metadata failed validation with error: 0x%08x\n", me->errorCode);
status_ = Q_TRAN(&FlashMgr_Idle);
}
break;
}
/* ${AOs::FlashMgr::SM::Active::BusyFlash::PrepFlash::FLASH_OP_TIMEOUT} */
case FLASH_OP_TIMEOUT_SIG: {
/* Override whatever error since the timeout interrupted whatever was happening. */
me->errorCode = ERR_FLASH_ERASE_TIMEOUT;
ERR_printf("Timed out while preparing flash for FW update. Error: 0x%08x\n", me->errorCode);
status_ = Q_TRAN(&FlashMgr_Idle);
break;
}
default: {
status_ = Q_SUPER(&FlashMgr_BusyFlash);
break;
}
}
return status_;
}
void EP_HDMI_SetAudFmt(HDMI_AudFmt_t Audfmt, HDMI_AudFreq Audfreq)
{
if(Audfmt == AUD_I2S)
{
EP932C_Registers.Audio_Interface = 0x18; // 2 channel IIS
DBG_printf(("Audio interface is IIS - 2.0 CH, "));
}
else
{
EP932C_Registers.Audio_Interface = 0x10; // SPDIF
DBG_printf(("Audio interface is SPDIF, "));
}
//EP932C_Registers.System_Configuration = EP932E_System_Configuration__HDCP_DIS;
if(Audfreq == AUD_Mute)
{
EP932C_Registers.System_Configuration |=
/*0x22*/EP932E_System_Configuration__AUDIO_DIS; // Audio mute enable
}
else
{
/*
EP932C_Registers.System_Configuration =
;*/ // Audio mute disable
}
EP932C_Registers.Audio_Input_Format = Audfreq; // set Audio frequency
DBG_printf(("freq = "));
switch(Audfreq)
{
case AUD_Mute:
DBG_printf(("Audio Mute\r\n"));
break;
case AUD_SF_32000Hz:
DBG_printf(("32K Hz\r\n"));
break;
case AUD_SF_44100Hz:
DBG_printf(("44.1K Hz\r\n"));
break;
case AUD_SF_48000Hz:
DBG_printf(("48K Hz\r\n"));
break;
case AUD_SF_88200Hz:
DBG_printf(("88.2K Hz\r\n"));
break;
case AUD_SF_96000Hz:
DBG_printf(("96K Hz\r\n"));
break;
case AUD_SF_176400Hz:
DBG_printf(("176.4K Hz\r\n"));
break;
case AUD_SF_192000Hz:
DBG_printf(("192K Hz\r\n"));
break;
default:
DBG_printf(("Unknown %d\r\n",Audfreq));
break;
}
}
void EP_HDMI_DumpMessage(void)
{
unsigned short Temp_USHORT;
unsigned char temp_R[2];
unsigned char reg_addr;
// System Status
DBG_printf(("\r\n\r\n======= Dump EP932E information =======\r\n"));
DBG_printf(("\r\n[EDID Data]"));
for(Temp_USHORT = 0; Temp_USHORT < 256; ++Temp_USHORT) {
if(Temp_USHORT%16 == 0) DBG_printf(("\r\n"));
if(Temp_USHORT%8 == 0) DBG_printf((" "));
DBG_printf(("0x%02X,", (int)EP932C_Registers.Readed_EDID[Temp_USHORT] ));
}
DBG_printf(("\r\n"));
DBG_printf(("\r\n[Revision & Configuration]\r\n"));
DBG_printf(("VendorID=0x%04X, ", EP932C_Registers.VendorID ));
DBG_printf(("DeviceID=0x%04X, ", EP932C_Registers.DeviceID ));
DBG_printf(("Version=%d.%d, CFG=0x%02X\r\n", (int)EP932C_Registers.Version_Major, (int)EP932C_Registers.Version_Minor, (int)EP932C_Registers.Configuration ));
DBG_printf(("\r\n[Interrupt Flags]\r\n"));
DBG_printf(("EDID_CHG=%d, ", (int)((EP932C_Registers.Interrupt_Flags & EP932E_Interrupt_Flags__EDID_CHG)?1:0) ));
DBG_printf(("VIDEO_CHG=%d, ", (int)((EP932C_Registers.Interrupt_Flags & EP932E_Interrupt_Flags__VIDEO_CHG)?1:0) ));
DBG_printf(("AUDIO_CHG=%d\r\n", (int)((EP932C_Registers.Interrupt_Flags & EP932E_Interrupt_Flags__AUDIO_CHG)?1:0) ));
DBG_printf(("\r\n[System Status]\r\n"));
DBG_printf(("RSEN=%d, ", (int)((EP932C_Registers.System_Status & EP932E_System_Status__RSEN)?1:0) ));
DBG_printf(("HTPLG=%d, ", (int)((EP932C_Registers.System_Status & EP932E_System_Status__HTPLG)?1:0) ));
DBG_printf(("KEY_FAIL=%d, ", (int)((EP932C_Registers.System_Status & EP932E_System_Status__KEY_FAIL)?1:0) ));
DBG_printf(("DEF_KEY=%d\r\n", (int)((EP932C_Registers.System_Status & EP932E_System_Status__DEF_KEY)?1:0) ));
DBG_printf(("\r\n[EDID Status]\r\n"));
DBG_printf(("EDID_HDMI=%d, ", (int)((EP932C_Registers.EDID_Status & EP932E_EDID_Status__HDMI)?1:0) ));
DBG_printf(("DDC_STATUS=%d\r\n", (int)(EP932C_Registers.EDID_Status & 0x0F) ));
DBG_printf(("VIDEO_DATA_ADDR=0x%02X, ", (int)EP932C_Registers.EDID_VideoDataAddr ));
DBG_printf(("AUDIO_DATA_ADDR=0x%02X, ", (int)EP932C_Registers.EDID_AudioDataAddr ));
DBG_printf(("SPEAKER_DATA_ADDR=0x%02X, ", (int)EP932C_Registers.EDID_SpeakerDataAddr ));
DBG_printf(("VENDOR_DATA_ADDR=0x%02X\r\n", (int)EP932C_Registers.EDID_VendorDataAddr ));
DBG_printf(("ASFREQ=0x%02X, ", (int)EP932C_Registers.EDID_ASFreq ));
DBG_printf(("ACHANNEL=%d\r\n", (int)EP932C_Registers.EDID_AChannel ));
DBG_printf(("\r\n[Video Status]\r\n"));
DBG_printf(("Interface=0x%02X, ", (int)EP932C_Registers.Video_Params_Backup.Interface ));
DBG_printf(("VideoSettingIndex=%d, ", (int)EP932C_Registers.Video_Params_Backup.VideoSettingIndex ));
DBG_printf(("HVPol=%d, ", (int)EP932C_Registers.Video_Params_Backup.HVPol ));
DBG_printf(("SyncMode=%d, ", (int)EP932C_Registers.Video_Params_Backup.SyncMode ));
DBG_printf(("FormatIn=%d, ", (int)EP932C_Registers.Video_Params_Backup.FormatIn ));
DBG_printf(("FormatOut=%d, ", (int)EP932C_Registers.Video_Params_Backup.FormatOut ));
DBG_printf(("ColorSpace=%d, ", (int)EP932C_Registers.Video_Params_Backup.ColorSpace ));
DBG_printf(("AFARate=%d\r\n", (int)EP932C_Registers.Video_Params_Backup.AFARate ));
DBG_printf(("\r\n[Audio Status]\r\n"));
DBG_printf(("Interface=0x%02X, ", (int)EP932C_Registers.Audio_Params_Backup.Interface ));
DBG_printf(("VideoSettingIndex=%d, ", (int)EP932C_Registers.Audio_Params_Backup.VideoSettingIndex ));
DBG_printf(("ChannelNumber=%d, ", (int)EP932C_Registers.Audio_Params_Backup.ChannelNumber ));
DBG_printf(("ADSRate=%d, ", (int)EP932C_Registers.Audio_Params_Backup.ADSRate ));
DBG_printf(("InputFrequency=%d, ", (int)EP932C_Registers.Audio_Params_Backup.InputFrequency ));
DBG_printf(("VFS=%d, ", (int)EP932C_Registers.Audio_Params_Backup.VFS ));
DBG_printf(("NoCopyRight=%d\r\n", (int)EP932C_Registers.Audio_Params_Backup.NoCopyRight ));
DBG_printf(("\r\n[Power Control]\r\n"));
DBG_printf(("PD_HDMI=%d, ", (int)((EP932C_Registers.Power_Control & EP932E_Power_Control__PD_HDMI)?1:0) ));
DBG_printf(("PD_TOT=%d\r\n", (int)((EP932C_Registers.Power_Control & EP932E_Power_Control__PD_TOT)?1:0) ));
DBG_printf(("\r\n[System Configuration]\r\n"));
DBG_printf(("HDCP_DIS=%d, ", (int)((EP932C_Registers.System_Configuration & EP932E_System_Configuration__HDCP_DIS)?1:0) ));
DBG_printf(("HDMI_DIS=%d, ", (int)((EP932C_Registers.System_Configuration & EP932E_System_Configuration__HDMI_DIS)?1:0) ));
DBG_printf(("AUDIO_DIS=%d, ", (int)((EP932C_Registers.System_Configuration & EP932E_System_Configuration__AUDIO_DIS)?1:0) ));
DBG_printf(("VIDEO_DIS=%d\r\n", (int)((EP932C_Registers.System_Configuration & EP932E_System_Configuration__VIDEO_DIS)?1:0) ));
DBG_printf(("\r\n[Interrupt Enable]\r\n"));
DBG_printf(("EDID_CHG=%d, ", (int)((EP932C_Registers.Interrupt_Enable & EP932E_Interrupt_Enable__EDID_CHG)?1:0) ));
DBG_printf(("VS_PERIOD_CHG=%d, ", (int)((EP932C_Registers.Interrupt_Enable & EP932E_Interrupt_Enable__VIDEO_CHG)?1:0) ));
DBG_printf(("AS_FREQ_CHG=%d\r\n", (int)((EP932C_Registers.Interrupt_Enable & EP932E_Interrupt_Enable__AUDIO_CHG)?1:0) ));
DBG_printf(("\r\n[Video Interface 0]\r\n"));
DBG_printf(("DK=%d, ", (int)((EP932C_Registers.Video_Interface[0] & EP932E_Video_Interface_Setting_0__DK)?1:0) ));
DBG_printf(("DKEN=%d, ", (int)((EP932C_Registers.Video_Interface[0] & EP932E_Video_Interface_Setting_0__DKEN)?1:0) ));
DBG_printf(("DSEL=%d, ", (int)((EP932C_Registers.Video_Interface[0] & EP932E_Video_Interface_Setting_0__DSEL)?1:0) ));
DBG_printf(("BSEL=%d, ", (int)((EP932C_Registers.Video_Interface[0] & EP932E_Video_Interface_Setting_0__BSEL)?1:0) ));
DBG_printf(("EDGE=%d, ", (int)((EP932C_Registers.Video_Interface[0] & EP932E_Video_Interface_Setting_0__EDGE)?1:0) ));
DBG_printf(("FMT12=%d\r\n", (int)((EP932C_Registers.Video_Interface[0] & EP932E_Video_Interface_Setting_0__FMT12)?1:0) ));
DBG_printf(("\r\n[Video Interface 1]\r\n"));
DBG_printf(("COLOR=%d, ", (int)((EP932C_Registers.Video_Interface[1] & EP932E_Video_Interface_Setting_1__COLOR)>>4) ));
DBG_printf(("SYNC=%d, ", (int)((EP932C_Registers.Video_Interface[1] & EP932E_Video_Interface_Setting_1__SYNC)>>2) ));
DBG_printf(("VIN_FMT=%d\r\n", (int)((EP932C_Registers.Video_Interface[1] & EP932E_Video_Interface_Setting_1__VIN_FMT)>>0) ));
DBG_printf(("\r\n[Audio Interface]\r\n"));
DBG_printf(("CHANNEL=%d, ", (int) (EP932C_Registers.Audio_Interface & EP932E_Audio_Interface_Setting__CHANNEL)>>4 ));
DBG_printf(("IIS=%d, ", (int)((EP932C_Registers.Audio_Interface & EP932E_Audio_Interface_Setting__IIS)?1:0) ));
DBG_printf(("WS_M=%d, ", (int)((EP932C_Registers.Audio_Interface & EP932E_Audio_Interface_Setting__WS_M)?1:0) ));
DBG_printf(("WS_POL=%d, ", (int)((EP932C_Registers.Audio_Interface & EP932E_Audio_Interface_Setting__WS_POL)?1:0) ));
DBG_printf(("SCK_POL=%d\r\n", (int)((EP932C_Registers.Audio_Interface & EP932E_Audio_Interface_Setting__SCK_POL)?1:0) ));
DBG_printf(("\r\n[Video Input Format 0]\r\n"));
DBG_printf(("VIC=%d\r\n", (int)EP932C_Registers.Video_Input_Format[0] ));
DBG_printf(("\r\n[Video Input Format 1]\r\n"));
DBG_printf(("AFAR_VIF=0x%02X\r\n", (int)EP932C_Registers.Video_Input_Format[1] ));
DBG_printf(("\r\n[EP932 Register value]"));
for(reg_addr = 0; reg_addr<=0x88; reg_addr++)
{
EP932_Reg_Read(reg_addr, temp_R, 1);
if(reg_addr%8 == 0)DBG_printf(("\r\n"));
DBG_printf(("[%02X]%02X, ",(int)reg_addr,(int)temp_R[0]));
}
DBG_printf(("\r\n"));
}
void EP_HDMI_Set_Video_Timing(LCD_TIMING Timing)
{
DBG_printf(("\r\n\r\n"));
DBG_printf(("##############################################\r\n"));
// no skew, Dual edge - falling edge first, 12 bit, FMT12 = 0,
EP932C_Registers.Video_Interface[0] = 0x04 /*| BSEL_24bit*/ /*| EDGE_rising */ /*| FMT_12*/;
DBG_printf(("Video_Interface_0 = 0x%02X \r\n",(int)EP932C_Registers.Video_Interface[0] ));
// mode: DE + Hsync + Vsync , input: YUV422
EP932C_Registers.Video_Interface[1] = 0x0; // DE,HS,VS, YUV422
DBG_printf(("Video_Interface_1 = 0x%02X \r\n",(int)EP932C_Registers.Video_Interface[1] ));
switch (Timing)
{
case HDMI_1080P:/*1920x1080p 60Hz[16:9]*/
DBG_printf(("TVOUT_MODE_1080P60\r\n"));
EP932C_Registers.Video_Input_Format[0] = 0x10;
break;
// case HDMI_1080I: /*1920x1080I 60Hz[16:9]*/
// DBG_printf(("TVOUT_MODE_1080I60\r\n"));
// EP932C_Registers.Video_Input_Format[0] = 0x05;
// break;
case HDMI_720P: /*1280x720p 60Hz[16:9]*/
DBG_printf(("TVOUT_MODE_720p\r\n"));
EP932C_Registers.Video_Input_Format[0] = 0x04;
break;
case HDMI_480P_16_9: /*720x480p 60Hz[16:9]*/
DBG_printf(("TVOUT_MODE_480p[16:9]\r\n"));
EP932C_Registers.Video_Input_Format[0] = 0x03;
break;
case HDMI_480P_4_3: /*720x480p 60Hz[4:3]*/
DBG_printf(("TVOUT_MODE_480p[4:3]\r\n"));
EP932C_Registers.Video_Input_Format[0] = 0x02;
break;
// case HDMI_480I_16_9: /*720x480I 60Hz[16:9]*/
// DBG_printf(("TVOUT_MODE_480I[16:9]\r\n"));
// EP932C_Registers.Video_Input_Format[0] = 0x07;
// break;
// case HDMI_480I_4_3: /*720x480I 60Hz[4:3]*/
// DBG_printf(("TVOUT_MODE_480I[4:3]\r\n"));
// EP932C_Registers.Video_Input_Format[0] = 0x06;
// break;
case HDMI_576P_16_9: /*720x576p 50Hz[16:9]*/
DBG_printf(("TVOUT_MODE_576p[16:9]\r\n"));
EP932C_Registers.Video_Input_Format[0] = 0x12;
break;
case HDMI_576P_4_3: /*720x576p 50Hz[4:3]*/
DBG_printf(("TVOUT_MODE_576p[4:3]\r\n"));
EP932C_Registers.Video_Input_Format[0] = 0x11;
break;
// case HDMI_576I_16_9: /*720x576I 50Hz[16:9]*/
// DBG_printf(("TVOUT_MODE_576I[16:9]\r\n"));
// EP932C_Registers.Video_Input_Format[0] = 0x16;
// break;
// case HDMI_576I_4_3: /*720x576I 50Hz[4:3]*/
// DBG_printf(("TVOUT_MODE_576I[4:3]\r\n"));
// EP932C_Registers.Video_Input_Format[0] = 0x15;
// break;
case HDMI_640_480: //640x480p 60Hz[4:3]:
DBG_printf(("TVOUT_MODE_640x480p[4:3]\r\n"));
EP932C_Registers.Video_Input_Format[0] = 0x01;
break;
default:
DBG_printf(("TVOUT_MODE_Unknown : %d\r\n",Timing));
EP932C_Registers.Video_Input_Format[0] = 0x00;
break;
}
// power on
EP932C_Registers.Power_Control = 0x00;
//===================================================================
DBG_printf(("##############################################\r\n"));
}
void EP932Controller_Reset(void)
{
#if defined(Enable_HDCP)
SMBUS_STATUS status = SMBUS_STATUS_Success;
#endif
// Reset Hardware
DBG_printf(("Reset EP932\r\n"));
EP_EP932M_Reset();
pEP932C_Registers->System_Configuration = 0;
pEP932C_Registers->System_Status = 0;
EP932_EnableHPInit();
// Initial Variables
EP932_Reg_Set_Bit(EP932_Pixel_Repetition_Control, EP932_Pixel_Repetition_Control__OSCSEL);
#if defined(Enable_HDCP)
// Read HDCP Key for EEPROM
status = HDMI_Tx_Get_Key((unsigned char *)HDCP_Key);
//DBG_printf(("Read HDCP Key = 0x%02X\r\n",(int)status));
HDCP_Fake(0);
pEP932C_Registers->System_Status &= ~EP932E_System_Status__KEY_FAIL;
// Check HDCP key and up load the key
if(status) {
// Do not upload the default Key!
pEP932C_Registers->System_Configuration |= EP932E_System_Configuration__HDCP_DIS;
pEP932C_Registers->System_Status |= EP932E_System_Status__KEY_FAIL;
DBG_printf(("No HDCP Key\r\n"));
}
else {
// Check HDCP key and up load the key
ChkSum = 0;
for(i=0; i<328; ++i) {
ChkSum += *((unsigned char *)HDCP_Key+i);
}
DBG_printf(("HDCP Key Check Sum 0x%02X\r\n", (int)ChkSum ));
if(HDCP_Key[3][7] != 0x50 || HDCP_Key[12][7] != 0x01 || ChkSum != 0x00) {// || HDCP_Key[40][0] != 0xA5) {
HDCP_Fake(1);
pEP932C_Registers->System_Status |= EP932E_System_Status__KEY_FAIL;
DBG_printf(("Check Key failed!\r\n"));
pEP932C_Registers->System_Configuration |= EP932E_System_Configuration__HDCP_DIS;
//DBG_printf(("Disable HDCP \r\n"));
}
else {
// Upload the key 0-39
for(i=0; i<40; ++i) {
DDC_Data[0] = (unsigned char)i;
status |= EP932_Reg_Write(EP932_Key_Add, DDC_Data, 1);
memcpy(DDC_Data,&HDCP_Key[i][0],7);
status |= EP932_Reg_Write(EP932_Key_Data, DDC_Data, 7);
}
// Read and check
for(i=0; i<40; ++i) {
DDC_Data[0] = (unsigned char)i;
status |= EP932_Reg_Write(EP932_Key_Add, DDC_Data, 1);
status |= EP932_Reg_Read(EP932_Key_Data, DDC_Data, 7);
if((memcmp(DDC_Data,&HDCP_Key[i][0],7) != 0) || status) {
// Test failed
HDCP_Fake(1);
pEP932C_Registers->System_Status |= EP932E_System_Status__KEY_FAIL;
DBG_printf(("Check Key failed!\r\n"));
pEP932C_Registers->System_Configuration |= EP932E_System_Configuration__HDCP_DIS;
//DBG_printf(("Disable HDCP \r\n"));
break;
}
}
// Upload final KSV 40
DDC_Data[0] = 40;
status |= EP932_Reg_Write(EP932_Key_Add, DDC_Data, 1);
memcpy(DDC_Data,&HDCP_Key[40][0],7);
status |= EP932_Reg_Write(EP932_Key_Data, DDC_Data, 7);
// Read back and check
if(!HDMI_Tx_read_AKSV(pEP932C_Registers->HDCP_AKSV)) {
// Test failed
HDCP_Fake(1);
pEP932C_Registers->System_Status |= EP932E_System_Status__KEY_FAIL;
DBG_printf(("Check KSV failed!\r\n"));
pEP932C_Registers->System_Configuration |= EP932E_System_Configuration__HDCP_DIS;
//DBG_printf(("Disable HDCP \r\n"));
}
}
}
#else
pEP932C_Registers->System_Status |= EP932E_System_Status__KEY_FAIL;
pEP932C_Registers->System_Configuration |= EP932E_System_Configuration__HDCP_DIS|EP932E_System_Configuration__FORCE_HDMI_CAP;
#endif
// EP932 Interface Reset
EP932_If_Reset();
// Internal Variable Reset
// bit
//Event_HDMI_Int = 0;
is_ReceiverSense = 0;
// data
Backup_Analog_Test_Control = 0;
if(TX_State > TXS_Search_EDID) {
DBG_printf(("\r\nState Transist: Reset -> [TXS_Wait_Upstream]\r\n"));
TX_State = TXS_Wait_Upstream;
}
DBG_printf(("EP932Controller_Reset finish\r\n"));
}
/**
* Взаимодействие с пользователем.
*
* @param[in] connection описание соединения.
* @return статус завершения.
*/
int user_interaction(IN struct connection_vars_t* conn)
{
TRACE;
int infp, outfp;
int pid = popen2(user_command, &infp, &outfp);
CHECK_ERRNO(pid, "Execute application");
char* buf = calloc(1, sizeof(char));
struct pollfd* fds = calloc(sizeof(struct pollfd), 2);
fds[0].fd = outfp;
fds[1].fd = conn->sockfd;
fds[0].events = fds[1].events = POLLIN;
while (true) {
int status = poll(fds, 2, TIMEOUT_MS);
CHECK_ERRNO(status, "Polling");
DBG_printf("Revents: %d %d\n", fds[0].revents, fds[1].revents);
if ((fds[0].revents | fds[1].revents) & POLLNVAL) {
/* Один из дескрипторов закрылся */
DBG_printf("One of fd has been closed\n");
break;
}
if (0 == status) {
/* Время ожидания истекло */
send(conn->sockfd, CONN_TIMEOUT_MSG,
sizeof(CONN_TIMEOUT_MSG), 0);
break;
}
int count = 0; /* Количество данных в fd */
status = ioctl(conn->sockfd, FIONREAD, &count);
CHECK_ERRNO(status, "Get available data in sockfd");
DBG_printf("%d bytes to read from socket\n", count);
if ((0 == count) && (fds[1].revents & POLLIN)) {
/*
* Если poll возвращает, что данные есть,
* но эти данные нельзя прочитать, то
* скорее всего сокет закрылся, а эти данные
* это что-то для сетевого стека, а не для нас.
*/
DBG_printf("Socket most likely closed\n");
break;
}
if (count > MAX_DATA_COUNT) {
/* TODO: Возможно, стоит генерировать сообщение. */
break;
}
if (count > 0) {
TRACE;
buf = realloc(buf, count);
int ret = recv(conn->sockfd, buf, count, 0);
DBG_printf("%d bytes ret from socket\n", ret);
if (ret < 0) {
break;
}
ret = write(infp, buf, ret);
if (ret < 0) {
break;
}
}
status = ioctl(outfp, FIONREAD, &count);
CHECK_ERRNO(status, "Get available data in outfp");
DBG_printf("%d bytes to read from outfp\n", count);
if (count > MAX_DATA_COUNT) {
/* TODO: Возможно, стоит генерировать сообщение. */
break;
}
if (count > 0) {
TRACE;
buf = realloc(buf, count);
int ret = read(outfp, buf, sizeof(buf));
DBG_printf("%d bytes ret from outfp\n", ret);
if (ret < 0) {
break;
}
ret = send(conn->sockfd, buf, ret, 0);
if (ret < 0) {
break;
}
}
}
close(infp);
close(outfp);
free(buf);
free(fds);
kill(pid, SIGTERM);
TRACE;
return 0;
}
/**
* Creates a file (creates the directory entry for a file) for optimized write.
* After this function returns successfully, it should be possible to do optimized
* writes on the file starting at the beginning.
* No checks are done against duplicate file name, and no clusters are allocated.
* File space is allocated during write operations.
*
* @param[in] fs Filesystem structure.
* @param[in] dir Directory structure.
* @param[out] fileOpt Output optimized file structure.
* @param[in] name File name, up to 8 characters.
* @param[in] ext File extension, up to 3 characters.
* @retval 1 Success
* @retval -1 Error creating file
* @retval -2 SD Card Error
* @retval -128 General error
*/
int8_t FAT32_CreateFileOpt(FAT32FS *fs, FAT32Directory *dir, FAT32FileOpt *file, char *name, char *ext) {
uint32_t currentCluster = dir->directoryTableAvailableCluster;
fs_addr_t currentLBA = dir->directoryTableAvailableLBA;
uint8_t clusterOffset = dir->directoryTableAvailableClusterOffset; // block number within the cluster
fs_length_t iii = 0;
DBG_DATA_printf("Starting cluster = 0x%08lx", currentCluster);
// Search for an empty file
while (1) {
if (BLOCK_SIZE != SD_SPI_ReadSingleBlock(fs->card, currentLBA, file->directoryTableBlockData)) {
DBG_printf("Error creating file (SD Read error on LBA = 0x%08lx).", currentLBA);
return -2; // Sanity check: Not reading the correct number of bytes
}
DBG_DATA_printf("Read Directory Table LBA = 0x%08lx", currentLBA)
// Search Directory Table for desired entry
for (iii = 0; iii < fs->bytesPerSector; iii += 32) {
DBG_SPAM_printf("Searching record '%8.8s.%3.3s'.", file->directoryTableBlockData + iii, file->directoryTableBlockData + iii + 8);
if (file->directoryTableBlockData[iii] == 0x00 || file->directoryTableBlockData[iii] == 0xe5) { // Available entry
DBG_printf("Available entry found.");
// Update directory structure with new end
dir->directoryTableAvailableCluster = currentCluster;
dir->directoryTableAvailableClusterOffset = clusterOffset;
dir->directoryTableAvailableLBA = currentLBA;
FATCreateDirectoryTableEntry(file->directoryTableBlockData+iii, name, ext);
// Fill out file structure
strncpy((char *) file->name, (char*)file->directoryTableBlockData+iii, 8);
strncpy((char *) file->ext, (char*)file->directoryTableBlockData+iii+8, 3);
file->fs = fs;
file->directoryTableLBA = currentLBA;
file->directoryTableBlockOffset = iii;
file->directoryTableDirty = 0;
file->startCluster = 0;
file->size = 0;
file->previousFATBlockData = file->previousFATData;
file->currentFATBlockData = file->currentFATData;
file->previousFATBlockOffset = 0;
file->previousFATDirty = 0;
file->previousFileSize = 0;
file->currentCluster = 0;
file->currentLBA = 0;
file->position = 0;
file->currentOperation = FILE_OP_None;
file->nextOperation = FILE_OP_WritingDataIdle;
file->dataBuffer[0] = SD_DMA_GetBuffer(0);
if (file->dataBuffer[0] == NULL) {
DBG_ERR_printf("Error allocating DMA buffer 0");
return -128;
}
file->dataBuffer[1] = SD_DMA_GetBuffer(1);
if (file->dataBuffer[1] == NULL) {
DBG_ERR_printf("Error allocating DMA buffer 1");
return -128;
}
file->fsBuffer = SD_DMA_GetBuffer(2);
if (file->fs == NULL) {
DBG_ERR_printf("Error allocating DMA FS buffer");
return -128;
}
file->dataBufferWrite = 0;
file->dataBufferFill = 0;
file->dataBufferNumFilled = 0;
file->dataBufferPos = 0;
file->overflowBufferBegin = 0;
file->overflowBufferEnd = 0;
file->overflowBufferSize = 0;
FAT32_InitializeFileFAT(file);
SD_SPI_WriteSingleBlock(fs->card, file->directoryTableLBA, file->directoryTableBlockData);
file->directoryTableDirty = 0;
SD_SPI_WriteSingleBlock(fs->card, file->currentFATLBA, file->currentFATBlockData);
file->currentFATAllocated = 0;
FAT32_FillFSInformationSector(file);
SD_SPI_WriteSingleBlock(fs->card, fs->FS_info_LBA, file->fsBuffer);
file->fs->fsInfoDirty = 0;
return 1;
}
}
// Advance to next block
clusterOffset++;
if (clusterOffset >= fs->sectorsPerCluster) { // End of cluster
currentCluster = getNextCluster(fs, currentCluster);
DBG_DATA_printf("Next cluster = 0x%08lx", currentCluster);
// Sanity check: ensure Directory Table cluster is valid
if (currentCluster >= 0xF0000000) {
DBG_printf("Error creating file (searched past end of Directory Table Cluster).");
return -1;
}
currentLBA = GetClusterLBA(fs, currentCluster);
clusterOffset = 0;
} else { // Advance to next block within cluster
currentLBA++;
}
}
}
void CPLR_Task( void* pvParameters )
{
(void) pvParameters;
QEvt const *evt; /* This pointer to an event always lives but should be
garbage collected after finishing to process it so the
memory in the pool to which it points can be reused. If
this thread needs to wait on another event while still
processing this (main) one, a different local pointer
should be used and garbage collected after. */
DC3Error_t status = ERR_NONE; /* Keep track of failures of various func
calls and commands. If this is ever set
to something other than ERR_NONE, it will
be printed out at the end of the for loop*/
for (;;) { /* Beginning of the thread forever loop */
/* Check if there's data in the queue and process it if there. */
evt = QEQueue_get(&CPLR_evtQueue);
if ( evt != (QEvt *)0 ) { /* Check whether an event is present in queue */
switch( evt->sig ) { /* Identify the event by its signal enum */
case CPLR_ETH_SYS_TEST_SIG:
DBG_printf(
"Received CPLR_ETH_SYS_TEST_SIG (%d) signal with event EthEvt of len: %d\n",
evt->sig,
((EthEvt const *)evt)->msg_len
);
#if 0
/* Going to use this signal to test some stuff in this thread */
/* Do a read from the EEPROM on the I2C Bus */
status = I2C_readDevMemEVT(
_DC3_EEPROM, // DC3I2CDevice_t iDev,
0x00, // uint16_t offset,
17, // uint16_t bytesToRead,
_DC3_ACCESS_FRT, // AccessType_t accType,
NULL // QActive* callingAO
);
if ( ERR_NONE != status ) {
ERR_printf("Error calling I2C_readDevMemEVT()\n");
goto CPLR_Task_ERR_HANDLE; /* Stop and jump to error handling */
}
/* If we got here, there were no errors during the call to
* I2C_readDevMemEVT() so we can expect an event from that driver
*/
uint32_t timeout = 1000;
QEvt const *evtI2CDone = 0;
/* We only expect an I2C read done signal and no others */
do {
evtI2CDone = QEQueue_get(&CPLR_evtQueue);
if (evtI2CDone != (QEvt *)0 ) {
break;
} else {
vTaskDelay(1);
}
} while ( --timeout != 0 );
if ( 0 == timeout ) {
ERR_printf("Timed out waiting for an event\n");
} else {
switch( evtI2CDone->sig ) {
case I2C1_DEV_READ_DONE_SIG:
DBG_printf("Got I2C1_DEV_READ_DONE_SIG\n");
break;
default:
WRN_printf("Unknown signal %d\n", evtI2CDone->sig);
break;
}
QF_gc(evt);
}
#endif
uint8_t buffer[20];
uint16_t bytesRead = 0;
DBG_printf("Issuing I2C_readDevMemFRT()\n");
status = I2C_readDevMemFRT(
_DC3_EEPROM, // const DC3I2CDevice_t iDev,
0x00, // const uint16_t offset,
17, // const uint16_t nBytesToRead
sizeof(buffer), // const uint16_t nBufferSize,
buffer, // uint8_t const *pBuffer,
&bytesRead // uint16_t *pBytesRead,
);
char tmp[120];
uint16_t tmpLen = 0;
status = CON_hexToStr(
(const uint8_t *)buffer, // data to convert
bytesRead, // length of data to convert
tmp, // where to write output
sizeof(tmp), // max size of output buffer
&tmpLen, // size of the resulting output
0, // no columns
' ', // separator
true // bPrintX
);
DBG_printf("I2C_readDevMemFRT() returned having read %d bytes: %s\n", bytesRead, tmp);
break;
default:
WRN_printf("Received an unknown signal: %d. Ignoring...\n", evt->sig);
break;
}
/* If any data from the event needs to be used after garbage
* collection, it should be locally stored if. */
CPLR_Task_ERR_HANDLE: /* Handle any error that may have occurred. */
/* Print error if exists */
ERR_COND_OUTPUT(
status,
_DC3_ACCESS_FRT,
"Error 0x%08x occurred in FreeRTOS thread!!!\n",
status
);
QF_gc(evt); /* !!! Don't forget to garbage collect the event after
processing the event. After this, any data to which
this pointer points to may not be valid and should not
be referenced. */
}
// vTaskSuspend(NULL);
vTaskDelay(1); /* Always task-delay so this thread can go to sleep while
other threads/AOs can process their data */
} /* End of the thread forever loop */
}
