int zynq_pll_init(void) {
zynq_slcr_unlock();
/* ARM PLL & Clock config
* 375 cycles needed for pll
* 26 divisor on pll
* enable all ARM clocks
* 2 divisor on ARM clocks
* ARM clock source is ARM PLL
*/
SLCR_REG(ARM_PLL_CFG) = PLL_CFG_LOCK_CNT(375) | PLL_CFG_PLL_CP(2) | PLL_CFG_PLL_RES(12);
SLCR_REG(ARM_PLL_CTRL) = PLL_FDIV(26) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_RESET;
if (pll_poll(PLL_STATUS_ARM_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(ARM_CLK_CTRL) = ARM_CLK_CTRL_DIVISOR(2) | ARM_CLK_CTRL_CPU_6OR4XCLKACT |
ARM_CLK_CTRL_CPU_3OR2XCLKACT | ARM_CLK_CTRL_CPU_2XCLKACT |
ARM_CLK_CTRL_CPU_1XCLKACT |ARM_CLK_CTRL_PERI_CLKACT;
/* DDR PLL & Clock config
* 475 cycles needed
* 21 divisor on PLL
* enable all DDR clocks
* 2 divisor for 3XCLK, 3 divisor for 2XCLK
*/
SLCR_REG(DDR_PLL_CFG) = PLL_CFG_LOCK_CNT(475) | PLL_CFG_PLL_CP(2) | PLL_CFG_PLL_RES(12);
SLCR_REG(DDR_PLL_CTRL) = PLL_FDIV(26) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_RESET;
if (pll_poll(PLL_STATUS_DDR_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(DDR_CLK_CTRL) = DDR_CLK_CTRL_DDR_3XCLKACT | DDR_CLK_CTRL_DDR_2XCLKACT |
DDR_CLK_CTRL_DDR_3XCLK_DIV(2) | DDR_CLK_CTRL_DDR_2XCLK_DIV(3);
/* IO PLL config
* 500 cycles needed for pll
* 20 divisor
*/
SLCR_REG(IO_PLL_CFG) = PLL_CFG_LOCK_CNT(500) | PLL_CFG_PLL_CP(2) | PLL_CFG_PLL_RES(12);
SLCR_REG(IO_PLL_CTRL) = PLL_FDIV(20) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(IO_PLL_CTRL) &= ~PLL_RESET;
if (pll_poll(PLL_STATUS_IO_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(IO_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
zynq_slcr_lock();
return 0;
}
[48] = MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
[49] = MIO_TRI_ENABLE | MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18,
// 50-51 are BTN4 and BTN5
[50] = MIO_IO_TYPE_LVCMOS18 | MIO_DISABLE_RCVR,
[51] = MIO_IO_TYPE_LVCMOS18 | MIO_DISABLE_RCVR,
// 52-53 gem0
[52] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18 | MIO_PULLUP,
[53] = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18 | MIO_PULLUP,
};
const zynq_clk_cfg_t zynq_clk_cfg = {
.arm_clk = ARM_CLK_CTRL_DIVISOR(2) | ARM_CLK_CTRL_CPU_6OR4XCLKACT |
ARM_CLK_CTRL_CPU_3OR2XCLKACT | ARM_CLK_CTRL_CPU_2XCLKACT |
ARM_CLK_CTRL_CPU_1XCLKACT |ARM_CLK_CTRL_PERI_CLKACT,
.ddr_clk = DDR_CLK_CTRL_DDR_3XCLKACT | DDR_CLK_CTRL_DDR_2XCLKACT |
DDR_CLK_CTRL_DDR_3XCLK_DIV(2) | DDR_CLK_CTRL_DDR_2XCLK_DIV(3),
.dci_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(52) | CLK_CTRL_DIVISOR1(2),
.gem0_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(8) | CLK_CTRL_DIVISOR1(1),
.gem0_rclk = CLK_CTRL_CLKACT,
.lqspi_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(5),
.sdio_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(20),
.uart_clk = CLK_CTRL_CLKACT1 | CLK_CTRL_DIVISOR0(20),
.pcap_clk = CLK_CTRL_CLKACT | CLK_CTRL_DIVISOR0(5),
.fpga0_clk = CLK_CTRL_DIVISOR0(10) | CLK_CTRL_DIVISOR1(1),
.fpga1_clk = CLK_CTRL_SRCSEL(3) | CLK_CTRL_DIVISOR0(6) | CLK_CTRL_DIVISOR1(1),
.fpga2_clk = CLK_CTRL_SRCSEL(2) | CLK_CTRL_DIVISOR0(53) | CLK_CTRL_DIVISOR1(2),
.fpga3_clk = CLK_CTRL_DIVISOR1(1),
.aper_clk = DMA_CPU_CLK_EN | USB0_CPU_CLK_EN | USB1_CPU_CLK_EN |
GEM0_CPU_CLK_EN | SDI0_CPU_CLK_EN | I2C0_CPU_CLK_EN |
I2C1_CPU_CLK_EN | UART1_CPU_CLK_EN | GPIO_CPU_CLK_EN |
LQSPI_CPU_CLK_EN | SMC_CPU_CLK_EN,
