case FLASH_STATUS: return max8997->i2c; default: return ERR_PTR(-EINVAL); } } struct max8997_irq_data { int mask; enum max8997_irq_source group; }; #define DECLARE_IRQ(idx, _group, _mask) \ [(idx)] = { .group = (_group), .mask = (_mask) } static const struct max8997_irq_data max8997_irqs[] = { DECLARE_IRQ(MAX8997_PMICIRQ_PWRONR, PMIC_INT1, 1 << 0), DECLARE_IRQ(MAX8997_PMICIRQ_PWRONF, PMIC_INT1, 1 << 1), DECLARE_IRQ(MAX8997_PMICIRQ_PWRON1SEC, PMIC_INT1, 1 << 3), DECLARE_IRQ(MAX8997_PMICIRQ_JIGONR, PMIC_INT1, 1 << 4), DECLARE_IRQ(MAX8997_PMICIRQ_JIGONF, PMIC_INT1, 1 << 5), DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT2, PMIC_INT1, 1 << 6), DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT1, PMIC_INT1, 1 << 7), DECLARE_IRQ(MAX8997_PMICIRQ_JIGR, PMIC_INT2, 1 << 0), DECLARE_IRQ(MAX8997_PMICIRQ_JIGF, PMIC_INT2, 1 << 1), DECLARE_IRQ(MAX8997_PMICIRQ_MR, PMIC_INT2, 1 << 2), DECLARE_IRQ(MAX8997_PMICIRQ_DVS1OK, PMIC_INT2, 1 << 3), DECLARE_IRQ(MAX8997_PMICIRQ_DVS2OK, PMIC_INT2, 1 << 4), DECLARE_IRQ(MAX8997_PMICIRQ_DVS3OK, PMIC_INT2, 1 << 5), DECLARE_IRQ(MAX8997_PMICIRQ_DVS4OK, PMIC_INT2, 1 << 6),
case MUIC_INT1 ... MUIC_INT3: return max77693->muic; default: return ERR_PTR(-EINVAL); } } struct max77693_irq_data { int mask; enum max77693_irq_source group; }; #define DECLARE_IRQ(idx, _group, _mask) \ [(idx)] = { .group = (_group), .mask = (_mask) } static const struct max77693_irq_data max77693_irqs[] = { DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_OPEN, LED_INT, 1 << 0), DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_SHORT, LED_INT, 1 << 1), DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_OPEN, LED_INT, 1 << 2), DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_SHORT, LED_INT, 1 << 3), DECLARE_IRQ(MAX77693_LED_IRQ_MAX_FLASH, LED_INT, 1 << 4), DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T120C_INT, TOPSYS_INT, 1 << 0), DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T140C_INT, TOPSYS_INT, 1 << 1), DECLARE_IRQ(MAX77693_TOPSYS_IRQLOWSYS_INT, TOPSYS_INT, 1 << 3), DECLARE_IRQ(MAX77693_CHG_IRQ_BYP_I, CHG_INT, 1 << 0), #if defined(CONFIG_CHARGER_MAX77803) DECLARE_IRQ(MAX77693_CHG_IRQ_BATP_I, CHG_INT, 1 << 2), #else DECLARE_IRQ(MAX77693_CHG_IRQ_THM_I, CHG_INT, 1 << 2), #endif
case MAX77843_MUIC_INT1 ... MAX77843_MUIC_INT3: return max77843->muic; default: return ERR_PTR(-EINVAL); } } struct max77843_irq_data { int mask; enum max77843_irq_source group; }; #define DECLARE_IRQ(idx, _group, _mask) \ [(idx)] = { .group = (_group), .mask = (_mask) } static const struct max77843_irq_data max77843_irqs[] = { DECLARE_IRQ(MAX77843_CHG_IRQ_BYP_I, MAX77843_CHG_INT, 1 << 0), DECLARE_IRQ(MAX77843_CHG_IRQ_BATP_I, MAX77843_CHG_INT, 1 << 2), DECLARE_IRQ(MAX77843_CHG_IRQ_BAT_I, MAX77843_CHG_INT, 1 << 3), DECLARE_IRQ(MAX77843_CHG_IRQ_CHG_I, MAX77843_CHG_INT, 1 << 4), DECLARE_IRQ(MAX77843_CHG_IRQ_WCIN_I, MAX77843_CHG_INT, 1 << 5), DECLARE_IRQ(MAX77843_CHG_IRQ_CHGIN_I, MAX77843_CHG_INT, 1 << 6), DECLARE_IRQ(MAX77843_CHG_IRQ_AICL_I, MAX77843_CHG_INT, 1 << 7), DECLARE_IRQ(MAX77843_FG_IRQ_ALERT, MAX77843_FUEL_INT, 1 << 1), DECLARE_IRQ(MAX77843_MUIC_IRQ_INT1_ADC, MAX77843_MUIC_INT1, 1 << 0), DECLARE_IRQ(MAX77843_MUIC_IRQ_INT1_ADCERR, MAX77843_MUIC_INT1, 1 << 2), DECLARE_IRQ(MAX77843_MUIC_IRQ_INT1_ADC1K, MAX77843_MUIC_INT1, 1 << 3), DECLARE_IRQ(MAX77843_MUIC_IRQ_INT2_CHGTYP, MAX77843_MUIC_INT2, 1 << 0), DECLARE_IRQ(MAX77843_MUIC_IRQ_INT2_CHGDETREUN, MAX77843_MUIC_INT2, 1 << 1),
static const u8 max14577_mask_reg[] = { [MAX14577_IRQ_INT1] = MAX14577_REG_INTMASK1, [MAX14577_IRQ_INT2] = MAX14577_REG_INTMASK2, [MAX14577_IRQ_INT3] = MAX14577_REG_INTMASK3, }; struct max14577_irq_data { int mask; enum max14577_irq_source group; }; #define DECLARE_IRQ(idx, _group, _mask) \ [(idx)] = { .group = (_group), .mask = (_mask) } static const struct max14577_irq_data max14577_irqs[] = { DECLARE_IRQ(MAX14577_IRQ_INT1_ADC, MAX14577_IRQ_INT1, 1 << 0), DECLARE_IRQ(MAX14577_IRQ_INT1_ADCLOW, MAX14577_IRQ_INT1, 1 << 1), DECLARE_IRQ(MAX14577_IRQ_INT1_ADCERR, MAX14577_IRQ_INT1, 1 << 2), DECLARE_IRQ(MAX14577_IRQ_INT2_CHGTYP, MAX14577_IRQ_INT2, 1 << 0), DECLARE_IRQ(MAX14577_IRQ_INT2_CHGDETREUN, MAX14577_IRQ_INT2, 1 << 1), DECLARE_IRQ(MAX14577_IRQ_INT2_DCDTMR, MAX14577_IRQ_INT2, 1 << 2), DECLARE_IRQ(MAX14577_IRQ_INT2_DBCHG, MAX14577_IRQ_INT2, 1 << 3), DECLARE_IRQ(MAX14577_IRQ_INT2_VBVOLT, MAX14577_IRQ_INT2, 1 << 4), DECLARE_IRQ(MAX14577_IRQ_INT3_EOC, MAX14577_IRQ_INT3, 1 << 0), DECLARE_IRQ(MAX14577_IRQ_INT3_CGMBC, MAX14577_IRQ_INT3, 1 << 1), DECLARE_IRQ(MAX14577_IRQ_INT3_OVP, MAX14577_IRQ_INT3, 1 << 2), DECLARE_IRQ(MAX14577_IRQ_INT3_MBCCHGERR, MAX14577_IRQ_INT3, 1 << 3), };
case RTC_INT: return max77xxx->rtc_regmap; default: return ERR_PTR(-EINVAL); } } struct max77xxx_irq_data { int mask; enum max77xxx_irq_source group; }; #define DECLARE_IRQ(idx, _group, _mask) \ [(idx)] = { .group = (_group), .mask = (_mask) } static const struct max77xxx_irq_data max77xxx_irqs[] = { DECLARE_IRQ(MAX77XXX_PMICIRQ_PWRONF, PMIC_INT1, 1 << 0), DECLARE_IRQ(MAX77XXX_PMICIRQ_PWRONR, PMIC_INT1, 1 << 1), DECLARE_IRQ(MAX77XXX_PMICIRQ_JIGONBF, PMIC_INT1, 1 << 2), DECLARE_IRQ(MAX77XXX_PMICIRQ_JIGONBR, PMIC_INT1, 1 << 3), DECLARE_IRQ(MAX77XXX_PMICIRQ_ACOKBF, PMIC_INT1, 1 << 4), DECLARE_IRQ(MAX77XXX_PMICIRQ_ACOKBR, PMIC_INT1, 1 << 5), DECLARE_IRQ(MAX77XXX_PMICIRQ_ONKEY1S, PMIC_INT1, 1 << 6), DECLARE_IRQ(MAX77XXX_PMICIRQ_MRSTB, PMIC_INT1, 1 << 7), DECLARE_IRQ(MAX77XXX_PMICIRQ_140C, PMIC_INT2, 1 << 0), DECLARE_IRQ(MAX77XXX_PMICIRQ_120C, PMIC_INT2, 1 << 1), DECLARE_IRQ(MAX77XXX_RTCIRQ_RTC60S, RTC_INT, 1 << 0), DECLARE_IRQ(MAX77XXX_RTCIRQ_RTCA1, RTC_INT, 1 << 1), DECLARE_IRQ(MAX77XXX_RTCIRQ_RTCA2, RTC_INT, 1 << 2), DECLARE_IRQ(MAX77XXX_RTCIRQ_SMPL, RTC_INT, 1 << 3), DECLARE_IRQ(MAX77XXX_RTCIRQ_RTC1S, RTC_INT, 1 << 4), DECLARE_IRQ(MAX77XXX_RTCIRQ_WTSR, RTC_INT, 1 << 5),
case MUIC_INT1 ... MUIC_INT3: return max77849->muic; default: return ERR_PTR(-EINVAL); } } struct max77849_irq_data { int mask; enum max77849_irq_source group; }; #define DECLARE_IRQ(idx, _group, _mask) \ [(idx)] = { .group = (_group), .mask = (_mask) } static const struct max77849_irq_data max77849_irqs[] = { DECLARE_IRQ(MAX77849_TOPSYS_IRQ_T120C_INT, TOPSYS_INT, 1 << 0), DECLARE_IRQ(MAX77849_TOPSYS_IRQ_T140C_INT, TOPSYS_INT, 1 << 1), DECLARE_IRQ(MAX77849_TOPSYS_IRQLOWSYS_INT, TOPSYS_INT, 1 << 3), DECLARE_IRQ(MAX77849_CHG_IRQ_BYP_I, CHG_INT, 1 << 0), DECLARE_IRQ(MAX77849_CHG_IRQ_BATP_I, CHG_INT, 1 << 2), DECLARE_IRQ(MAX77849_CHG_IRQ_BAT_I, CHG_INT, 1 << 3), DECLARE_IRQ(MAX77849_CHG_IRQ_CHG_I, CHG_INT, 1 << 4), DECLARE_IRQ(MAX77849_CHG_IRQ_WCIN_I, CHG_INT, 1 << 5), DECLARE_IRQ(MAX77849_CHG_IRQ_CHGIN_I, CHG_INT, 1 << 6), DECLARE_IRQ(MAX77849_MUIC_IRQ_INT1_ADC, MUIC_INT1, 1 << 0), DECLARE_IRQ(MAX77849_MUIC_IRQ_INT1_ADCLOW, MUIC_INT1, 1 << 1), DECLARE_IRQ(MAX77849_MUIC_IRQ_INT1_ADCERR, MUIC_INT1, 1 << 2), DECLARE_IRQ(MAX77849_MUIC_IRQ_INT1_ADC1K, MUIC_INT1, 1 << 3),
case MUIC_INT1 ... MUIC_INT3: return max77828->muic; default: return ERR_PTR(-EINVAL); } } struct max77828_irq_data { int mask; enum max77828_irq_source group; }; #define DECLARE_IRQ(idx, _group, _mask) \ [(idx)] = { .group = (_group), .mask = (_mask) } static const struct max77828_irq_data max77828_irqs[] = { DECLARE_IRQ(MAX77828_MUIC_IRQ_INT1_ADC, MUIC_INT1, 1 << 0), DECLARE_IRQ(MAX77828_MUIC_IRQ_INT1_ADCERR, MUIC_INT1, 1 << 2), DECLARE_IRQ(MAX77828_MUIC_IRQ_INT1_ADC1K, MUIC_INT1, 1 << 3), DECLARE_IRQ(MAX77828_MUIC_IRQ_INT2_CHGTYP, MUIC_INT2, 1 << 0), DECLARE_IRQ(MAX77828_MUIC_IRQ_INT2_CHGDETREUN, MUIC_INT2, 1 << 1), DECLARE_IRQ(MAX77828_MUIC_IRQ_INT2_DCDTMR, MUIC_INT2, 1 << 2), DECLARE_IRQ(MAX77828_MUIC_IRQ_INT2_DXOVP, MUIC_INT2, 1 << 3), DECLARE_IRQ(MAX77828_MUIC_IRQ_INT2_VBVOLT, MUIC_INT2, 1 << 4), DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_VBADC, MUIC_INT3, 1 << 0), DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_VDNMON, MUIC_INT3, 1 << 1), DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_DNRES, MUIC_INT3, 1 << 2), DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_MPNACK, MUIC_INT3, 1 << 3), DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_MRXBUFOW, MUIC_INT3, 1 << 4), DECLARE_IRQ(MAX77828_MUIC_IRQ_INT3_MRXTRF, MUIC_INT3, 1 << 5),
case MUIC_INT1 ... MUIC_MAX_INT: return max77833->muic; default: return ERR_PTR(-EINVAL); } } struct max77833_irq_data { int mask; enum max77833_irq_source group; }; #define DECLARE_IRQ(idx, _group, _mask) \ [(idx)] = { .group = (_group), .mask = (_mask) } static const struct max77833_irq_data max77833_irqs[] = { DECLARE_IRQ(MAX77833_SYSTEM_IRQ_T100C_INT, TOP_INT, 1 << 0), DECLARE_IRQ(MAX77833_SYSTEM_IRQ_T120C_INT, TOP_INT, 1 << 1), DECLARE_IRQ(MAX77833_SYSTEM_IRQ_T140C_INT, TOP_INT, 1 << 2), DECLARE_IRQ(MAX77833_SYSTEM_IRQ_I2C_WD_INT, TOP_INT, 1 << 3), DECLARE_IRQ(MAX77833_SYSTEM_IRQ_SYSUVLO_INT, TOP_INT, 1 << 4), DECLARE_IRQ(MAX77833_SYSTEM_IRQ_MRSTB_INT, TOP_INT, 1 << 5), DECLARE_IRQ(MAX77833_SYSTEM_IRQ_TS_INT, TOP_INT, 1 << 7), DECLARE_IRQ(MAX77833_CHG_IRQ_BYP_I, CHG_INT, 1 << 0), DECLARE_IRQ(MAX77833_CHG_IRQ_BATP_I, CHG_INT, 1 << 2), DECLARE_IRQ(MAX77833_CHG_IRQ_BAT_I, CHG_INT, 1 << 3), DECLARE_IRQ(MAX77833_CHG_IRQ_CHG_I, CHG_INT, 1 << 4), DECLARE_IRQ(MAX77833_CHG_IRQ_WCIN_I, CHG_INT, 1 << 5), DECLARE_IRQ(MAX77833_CHG_IRQ_CHGIN_I, CHG_INT, 1 << 6), DECLARE_IRQ(MAX77833_CHG_IRQ_AICL_I, CHG_INT, 1 << 7),
case MUIC_INT1: return max77665->muic; default: return ERR_PTR(-EINVAL); } } struct max77665_irq_data { int mask; enum max77665_irq_source group; }; #define DECLARE_IRQ(idx, _group, _mask) \ [(idx)] = { .group = (_group), .mask = (_mask) } static const struct max77665_irq_data max77665_irqs[] = { DECLARE_IRQ(MAX77665_CHG_IRQ_BYP_I, CHG_INT, 1 << 0), DECLARE_IRQ(MAX77665_CHG_IRQ_THM_I, CHG_INT, 1 << 2), DECLARE_IRQ(MAX77665_CHG_IRQ_BAT_I, CHG_INT, 1 << 3), DECLARE_IRQ(MAX77665_CHG_IRQ_CHG_I, CHG_INT, 1 << 4), DECLARE_IRQ(MAX77665_CHG_IRQ_CHGIN_I, CHG_INT, 1 << 6), DECLARE_IRQ(MAX77665_TOPSYS_IRQ_T120C_INT, TOPSYS_INT, 1 << 0), DECLARE_IRQ(MAX77665_TOPSYS_IRQ_T140C_INT, TOPSYS_INT, 1 << 1), DECLARE_IRQ(MAX77665_TOPSYS_IRQ_LOWSYS_INT, TOPSYS_INT, 1 << 3), DECLARE_IRQ(MAX77665_LED_IRQ_FLED2_OPEN, LED_INT, 1 << 0), DECLARE_IRQ(MAX77665_LED_IRQ_FLED2_SHORT, LED_INT, 1 << 1), DECLARE_IRQ(MAX77665_LED_IRQ_FLED1_OPEN, LED_INT, 1 << 2), DECLARE_IRQ(MAX77665_LED_IRQ_FLED1_SHORT, LED_INT, 1 << 3), DECLARE_IRQ(MAX77665_LED_IRQ_MAX_FLASH, LED_INT, 1 << 4),