cdrv = qemu_chr_new("braille", "braille", NULL);
if (!cdrv)
return NULL;
dev = usb_create(bus, "usb-braille");
qdev_prop_set_chr(&dev->qdev, "chardev", cdrv);
return dev;
}
static const VMStateDescription vmstate_usb_serial = {
.name = "usb-serial",
.unmigratable = 1,
};
static Property serial_properties[] = {
DEFINE_PROP_CHR("chardev", USBSerialState, cs),
DEFINE_PROP_END_OF_LIST(),
};
static void usb_serial_dev_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
USBDeviceClass *uc = USB_DEVICE_CLASS(klass);
uc->realize = usb_serial_realize;
uc->handle_reset = usb_serial_handle_reset;
uc->handle_control = usb_serial_handle_control;
uc->handle_data = usb_serial_handle_data;
dc->vmsd = &vmstate_usb_serial;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
s->irq = irq;
s->chr = chr;
s->it_shift = it_shift;
qemu_register_reset(parallel_reset, s);
memory_region_init_io(&s->iomem, ¶llel_mm_ops, s,
"parallel", 8 << it_shift);
memory_region_add_subregion(address_space, base, &s->iomem);
return true;
}
static Property parallel_isa_properties[] = {
DEFINE_PROP_UINT32("index", ISAParallelState, index, -1),
DEFINE_PROP_HEX32("iobase", ISAParallelState, iobase, -1),
DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7),
DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
DEFINE_PROP_END_OF_LIST(),
};
static void parallel_isa_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
ic->init = parallel_isa_initfn;
dc->props = parallel_isa_properties;
}
static TypeInfo parallel_isa_info = {
.name = "isa-parallel",
.parent = TYPE_ISA_DEVICE,
.instance_size = sizeof(ISAParallelState),
.name = TYPE_IVSHMEM_DOORBELL,
.version_id = 0,
.minimum_version_id = 0,
.pre_load = ivshmem_pre_load,
.post_load = ivshmem_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
VMSTATE_MSIX(parent_obj, IVShmemState),
VMSTATE_UINT32(intrstatus, IVShmemState),
VMSTATE_UINT32(intrmask, IVShmemState),
VMSTATE_END_OF_LIST()
},
};
static Property ivshmem_doorbell_properties[] = {
DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1),
DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD,
true),
DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
DEFINE_PROP_END_OF_LIST(),
};
static void ivshmem_doorbell_init(Object *obj)
{
IVShmemState *s = IVSHMEM_DOORBELL(obj);
s->features |= (1 << IVSHMEM_MSI);
s->legacy_size = SIZE_MAX; /* whatever the server sends */
s->not_legacy_32bit = 1;
}
}
static int debugcon_isa_initfn(ISADevice *dev)
{
ISADebugconState *isa = DO_UPCAST(ISADebugconState, dev, dev);
DebugconState *s = &isa->state;
debugcon_init_core(s);
register_ioport_write(isa->iobase, 1, 1, debugcon_ioport_write, s);
register_ioport_read(isa->iobase, 1, 1, debugcon_ioport_read, s);
return 0;
}
static Property debugcon_isa_properties[] = {
DEFINE_PROP_HEX32("iobase", ISADebugconState, iobase, 0xe9),
DEFINE_PROP_CHR("chardev", ISADebugconState, state.chr),
DEFINE_PROP_HEX32("readback", ISADebugconState, state.readback, 0xe9),
DEFINE_PROP_END_OF_LIST(),
};
static void debugcon_isa_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
ic->init = debugcon_isa_initfn;
dc->props = debugcon_isa_properties;
}
static TypeInfo debugcon_isa_info = {
.name = "isa-debugcon",
.parent = TYPE_ISA_DEVICE,
sysbus_init_irq(dev, &uart->irq);
uart_regs = cpu_register_io_memory(grlib_apbuart_read,
grlib_apbuart_write,
uart, DEVICE_NATIVE_ENDIAN);
if (uart_regs < 0) {
return -1;
}
sysbus_init_mmio(dev, UART_REG_SIZE, uart_regs);
return 0;
}
static SysBusDeviceInfo grlib_gptimer_info = {
.init = grlib_apbuart_init,
.qdev.name = "grlib,apbuart",
.qdev.size = sizeof(UART),
.qdev.props = (Property[]) {
DEFINE_PROP_CHR("chrdev", UART, chr),
DEFINE_PROP_END_OF_LIST()
}
};
static void grlib_gptimer_register(void)
{
sysbus_register_withprop(&grlib_gptimer_info);
}
device_init(grlib_gptimer_register)
IPMIBmcExtern *ibe = IPMI_BMC_EXTERN(obj);
ibe->extern_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, extern_timeout, ibe);
vmstate_register(NULL, 0, &vmstate_ipmi_bmc_extern, ibe);
}
static void ipmi_bmc_extern_finalize(Object *obj)
{
IPMIBmcExtern *ibe = IPMI_BMC_EXTERN(obj);
timer_del(ibe->extern_timer);
timer_free(ibe->extern_timer);
}
static Property ipmi_bmc_extern_properties[] = {
DEFINE_PROP_CHR("chardev", IPMIBmcExtern, chr),
DEFINE_PROP_END_OF_LIST(),
};
static void ipmi_bmc_extern_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
IPMIBmcClass *bk = IPMI_BMC_CLASS(oc);
bk->handle_command = ipmi_bmc_extern_handle_command;
bk->handle_reset = ipmi_bmc_extern_handle_reset;
dc->hotpluggable = false;
dc->realize = ipmi_bmc_extern_realize;
dc->props = ipmi_bmc_extern_properties;
}
memory_region_init_io(&s->mmio, OBJECT(s), &uart_ops, s,
TYPE_ALTERA_UART, R_MAX * sizeof(uint32_t));
sysbus_init_mmio(dev, &s->mmio);
if (!s->chr) {
s->chr = serial_hds[0];
}
if (s->chr) {
qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
}
return 0;
}
static Property altera_uart_properties[] = {
DEFINE_PROP_CHR("chardev", AlteraUART, chr),
DEFINE_PROP_END_OF_LIST(),
};
static void altera_uart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = altera_uart_init;
dc->props = altera_uart_properties;
}
static const TypeInfo altera_uart_info = {
.name = TYPE_ALTERA_UART,
.parent = TYPE_SYS_BUS_DEVICE,
{
return 0;
}
static void console_reset(DeviceState *dev)
{
SCLPEvent *event = SCLP_EVENT(dev);
SCLPConsoleLM *scon = DO_UPCAST(SCLPConsoleLM, event, event);
event->event_pending = false;
scon->length = 0;
scon->write_errors = 0;
}
static Property console_properties[] = {
DEFINE_PROP_CHR("chardev", SCLPConsoleLM, chr),
DEFINE_PROP_UINT32("write_errors", SCLPConsoleLM, write_errors, 0),
DEFINE_PROP_BOOL("echo", SCLPConsoleLM, echo, true),
DEFINE_PROP_END_OF_LIST(),
};
static void console_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SCLPEventClass *ec = SCLP_EVENT_CLASS(klass);
dc->props = console_properties;
dc->reset = console_reset;
dc->vmsd = &vmstate_sclplmconsole;
ec->init = console_init;
ec->exit = console_exit;
*/
qemu_chr_add_handlers(vcon->chr, NULL, NULL, NULL, NULL);
}
return 0;
}
static VirtIOSerialPortInfo virtconsole_info = {
.qdev.name = "virtconsole",
.qdev.size = sizeof(VirtConsole),
.init = virtconsole_initfn,
.exit = virtconsole_exitfn,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT8("is_console", VirtConsole, port.is_console, 1),
DEFINE_PROP_UINT32("nr", VirtConsole, port.id, VIRTIO_CONSOLE_BAD_ID),
DEFINE_PROP_CHR("chardev", VirtConsole, chr),
DEFINE_PROP_STRING("name", VirtConsole, port.name),
DEFINE_PROP_END_OF_LIST(),
},
};
static void virtconsole_register(void)
{
virtio_serial_port_qdev_register(&virtconsole_info);
}
device_init(virtconsole_register)
/* Generic Virtio Serial Ports */
static int virtserialport_initfn(VirtIOSerialPort *port)
{
VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port);
"milkymist-uart", R_MAX * 4);
sysbus_init_mmio(sbd, &s->regs_region);
}
static const VMStateDescription vmstate_milkymist_uart = {
.name = "milkymist-uart",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX),
VMSTATE_END_OF_LIST()
}
};
static Property milkymist_uart_properties[] = {
DEFINE_PROP_CHR("chardev", MilkymistUartState, chr),
DEFINE_PROP_END_OF_LIST(),
};
static void milkymist_uart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = milkymist_uart_realize;
dc->reset = milkymist_uart_reset;
dc->vmsd = &vmstate_milkymist_uart;
dc->props = milkymist_uart_properties;
}
static const TypeInfo milkymist_uart_info = {
.name = TYPE_MILKYMIST_UART,
}
ser_update_irq(s);
}
static const MemoryRegionOps ser_ops = {
.read = ser_read,
.write = ser_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
}
};
static Property etraxfs_ser_properties[] = {
DEFINE_PROP_CHR("chardev", ETRAXSerial, chr),
DEFINE_PROP_END_OF_LIST(),
};
static void serial_receive(void *opaque, const uint8_t *buf, int size)
{
ETRAXSerial *s = opaque;
int i;
/* Got a byte. */
if (s->rx_fifo_len >= 16) {
D(qemu_log("WARNING: UART dropped char.\n"));
return;
}
for (i = 0; i < size; i++) {
memory_region_init_io(&s->iomem, obj, &mcf_uart_ops, s, "uart", 0x40);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
}
static void mcf_uart_realize(DeviceState *dev, Error **errp)
{
mcf_uart_state *s = MCF_UART(dev);
qemu_chr_fe_set_handlers(&s->chr, mcf_uart_can_receive, mcf_uart_receive,
mcf_uart_event, s, NULL, true);
}
static Property mcf_uart_properties[] = {
DEFINE_PROP_CHR("chardev", mcf_uart_state, chr),
DEFINE_PROP_END_OF_LIST(),
};
static void mcf_uart_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = mcf_uart_realize;
dc->reset = mcf_uart_reset;
dc->props = mcf_uart_properties;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
static const TypeInfo mcf_uart_info = {
.name = TYPE_MCF_UART,
static const VMStateDescription vmstate_isa_serial = {
.name = "serial",
.version_id = 3,
.minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(state, ISASerialState, 0, vmstate_serial, SerialState),
VMSTATE_END_OF_LIST()
}
};
static Property serial_isa_properties[] = {
DEFINE_PROP_UINT32("index", ISASerialState, index, -1),
DEFINE_PROP_UINT32("iobase", ISASerialState, iobase, -1),
DEFINE_PROP_UINT32("irq", ISASerialState, isairq, -1),
DEFINE_PROP_CHR("chardev", ISASerialState, state.chr),
DEFINE_PROP_UINT32("wakeup", ISASerialState, state.wakeup, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void serial_isa_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = serial_isa_realizefn;
dc->vmsd = &vmstate_isa_serial;
dc->props = serial_isa_properties;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
static const TypeInfo serial_isa_info = {
CharBackend chr;
uint32_t regs[R_MAX_0];
uint32_t baud;
DepRegisterInfo regs_info0[R_MAX_0];
DepRegisterInfo regs_info1[R_MAX_1];
DepRegisterInfo *regs_infos[2];
const char *prefix;
} XilinxUART;
static Property xlx_iom_properties[] = {
DEFINE_PROP_BOOL("use-uart-rx", XilinxUART, cfg.use_rx, 0),
DEFINE_PROP_BOOL("use-uart-tx", XilinxUART, cfg.use_tx, 0),
DEFINE_PROP_BOOL("uart-rx-interrupt", XilinxUART, cfg.rx_interrupt, 0),
DEFINE_PROP_BOOL("uart-tx-interrupt", XilinxUART, cfg.tx_interrupt, 0),
DEFINE_PROP_BOOL("uart-error-interrupt", XilinxUART, cfg.err_interrupt, 0),
DEFINE_PROP_CHR("chardev", XilinxUART, chr),
DEFINE_PROP_END_OF_LIST(),
};
static void uart_rx(void *opaque, const uint8_t *buf, int size)
{
XilinxUART *s = opaque;
if (!s->cfg.use_rx) {
return;
}
if (s->regs[R_IOM_UART_STATUS] & IOM_UART_STATUS_RX_VALID) {
s->regs[R_IOM_UART_STATUS] |= IOM_UART_STATUS_OVERRUN;
if (s->cfg.err_interrupt) {
qemu_irq_pulse(s->irq_err);
static const VMStateDescription vmstate_pci_multi_serial = {
.name = "pci-serial-multi",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
0, vmstate_serial, SerialState),
VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
VMSTATE_END_OF_LIST()
}
};
static Property serial_pci_properties[] = {
DEFINE_PROP_CHR("chardev", PCISerialState, state.chr),
DEFINE_PROP_END_OF_LIST(),
};
static Property multi_2x_serial_pci_properties[] = {
DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
DEFINE_PROP_END_OF_LIST(),
};
static Property multi_4x_serial_pci_properties[] = {
DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr),
DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr),
DEFINE_PROP_END_OF_LIST(),
