static int allocate_pipes(struct echoaudio *chip, struct audiopipe *pipe,
int pipe_index, int interleave)
{
int i;
u32 channel_mask;
char is_cyclic;
DE_ACT(("allocate_pipes: ch=%d int=%d\n", pipe_index, interleave));
if (chip->bad_board)
return -EIO;
is_cyclic = 1;
for (channel_mask = i = 0; i < interleave; i++)
channel_mask |= 1 << (pipe_index + i);
if (chip->pipe_alloc_mask & channel_mask) {
DE_ACT(("allocate_pipes: channel already open\n"));
return -EAGAIN;
}
chip->comm_page->position[pipe_index] = 0;
chip->pipe_alloc_mask |= channel_mask;
if (is_cyclic)
chip->pipe_cyclic_mask |= channel_mask;
pipe->index = pipe_index;
pipe->interleave = interleave;
pipe->state = PIPE_STATE_STOPPED;
pipe->dma_counter = &chip->comm_page->position[pipe_index];
*pipe->dma_counter = 0;
DE_ACT(("allocate_pipes: ok\n"));
return pipe_index;
}
static int set_input_clock(struct echoaudio *chip, u16 clock)
{
DE_ACT(("set_input_clock:\n"));
switch (clock) {
case ECHO_CLOCK_INTERNAL:
/* Reset the audio state to unknown (just in case) */
chip->clock_state = GD_CLOCK_UNDEF;
chip->spdif_status = GD_SPDIF_STATUS_UNDEF;
set_sample_rate(chip, chip->sample_rate);
chip->input_clock = clock;
DE_ACT(("Set Gina clock to INTERNAL\n"));
break;
case ECHO_CLOCK_SPDIF:
chip->comm_page->gd_clock_state = GD_CLOCK_SPDIFIN;
chip->comm_page->gd_spdif_status = GD_SPDIF_STATUS_NOCHANGE;
clear_handshake(chip);
send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
chip->clock_state = GD_CLOCK_SPDIFIN;
DE_ACT(("Set Gina20 clock to SPDIF\n"));
chip->input_clock = clock;
break;
default:
return -EINVAL;
}
return 0;
}
static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
{
u32 control_reg;
int err, incompatible_clock;
/* Set clock to "internal" if it's not compatible with the new mode */
incompatible_clock = FALSE;
switch (mode) {
case DIGITAL_MODE_SPDIF_OPTICAL:
case DIGITAL_MODE_SPDIF_RCA:
if (chip->input_clock == ECHO_CLOCK_ADAT)
incompatible_clock = TRUE;
break;
case DIGITAL_MODE_ADAT:
if (chip->input_clock == ECHO_CLOCK_SPDIF)
incompatible_clock = TRUE;
break;
default:
DE_ACT(("Digital mode not supported: %d\n", mode));
return -EINVAL;
}
spin_lock_irq(&chip->lock);
if (incompatible_clock) {
chip->sample_rate = 48000;
set_input_clock(chip, ECHO_CLOCK_INTERNAL);
}
/* Clear the current digital mode */
control_reg = le32_to_cpu(chip->comm_page->control_register);
control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK;
/* Tweak the control reg */
switch (mode) {
case DIGITAL_MODE_SPDIF_OPTICAL:
control_reg |= E3G_SPDIF_OPTICAL_MODE;
break;
case DIGITAL_MODE_SPDIF_RCA:
/* E3G_SPDIF_OPTICAL_MODE bit cleared */
break;
case DIGITAL_MODE_ADAT:
control_reg |= E3G_ADAT_MODE;
control_reg &= ~E3G_DOUBLE_SPEED_MODE; /* @@ useless */
break;
}
err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
spin_unlock_irq(&chip->lock);
if (err < 0)
return err;
chip->digital_mode = mode;
DE_ACT(("set_digital_mode(%d)\n", chip->digital_mode));
return incompatible_clock;
}
static int set_sample_rate(struct echoaudio *chip, u32 rate)
{
u8 clock;
switch (rate) {
case 96000:
clock = GD24_96000;
break;
case 88200:
clock = GD24_88200;
break;
case 48000:
clock = GD24_48000;
break;
case 44100:
clock = GD24_44100;
break;
case 32000:
clock = GD24_32000;
break;
case 22050:
clock = GD24_22050;
break;
case 16000:
clock = GD24_16000;
break;
case 11025:
clock = GD24_11025;
break;
case 8000:
clock = GD24_8000;
break;
default:
DE_ACT(("set_sample_rate: Error, invalid sample rate %d\n",
rate));
return -EINVAL;
}
if (wait_handshake(chip))
return -EIO;
DE_ACT(("set_sample_rate: %d clock %d\n", rate, clock));
chip->sample_rate = rate;
/* Override the sample rate if this card is set to Echo sync. */
if (chip->input_clock == ECHO_CLOCK_ESYNC)
clock = GD24_EXT_SYNC;
chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP ? */
chip->comm_page->gd_clock_state = clock;
clear_handshake(chip);
return send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
}
/* ASIC status check - some cards have one or two ASICs that need to be
loaded. Once that load is complete, this function is called to see if
the load was successful.
If this load fails, it does not necessarily mean that the hardware is
defective - the external box may be disconnected or turned off.
This routine sometimes fails for Layla20; for Layla20, the loop runs
5 times and succeeds if it wins on three of the loops. */
static int check_asic_status(struct echoaudio *chip)
{
u32 asic_status;
int goodcnt, i;
chip->asic_loaded = FALSE;
for (i = goodcnt = 0; i < 5; i++) {
send_vector(chip, DSP_VC_TEST_ASIC);
/* The DSP will return a value to indicate whether or not
the ASIC is currently loaded */
if (read_dsp(chip, &asic_status) < 0) {
DE_ACT(("check_asic_status: failed on read_dsp\n"));
return -EIO;
}
if (asic_status == ASIC_ALREADY_LOADED) {
if (++goodcnt == 3) {
chip->asic_loaded = TRUE;
return 0;
}
}
}
return -EIO;
}
static int set_input_auto_mute(struct echoaudio *chip, int automute)
{
DE_ACT(("set_input_auto_mute %d\n", automute));
chip->digital_in_automute = automute;
return set_input_clock(chip, chip->input_clock);
}
static int set_input_clock(struct echoaudio *chip, u16 clock)
{
DE_ACT(("set_input_clock(%d)\n", clock));
if (snd_BUG_ON(clock != ECHO_CLOCK_INTERNAL &&
clock != ECHO_CLOCK_SPDIF))
return -EINVAL;
chip->input_clock = clock;
return set_sample_rate(chip, chip->sample_rate);
}
static int set_input_auto_mute(struct echoaudio *chip, int automute)
{
DE_ACT(("set_input_auto_mute %d\n", automute));
chip->digital_in_automute = automute;
/* Re-set the input clock to the current value - indirectly causes
the auto-mute flag to be sent to the DSP */
return set_input_clock(chip, chip->input_clock);
}
static int set_professional_spdif(struct echoaudio *chip, char prof)
{
DE_ACT(("set_professional_spdif %d\n", prof));
if (prof)
chip->comm_page->flags |=
cpu_to_le32(DSP_FLAG_PROFESSIONAL_SPDIF);
else
chip->comm_page->flags &=
~cpu_to_le32(DSP_FLAG_PROFESSIONAL_SPDIF);
chip->professional_spdif = prof;
return update_flags(chip);
}
/* Most configuration of 3G cards is accomplished by writing the control
register. write_control_reg sends the new control register value to the DSP. */
static int write_control_reg(struct echoaudio *chip, u32 ctl, u32 frq,
char force)
{
if (wait_handshake(chip))
return -EIO;
DE_ACT(("WriteControlReg: Setting 0x%x, 0x%x\n", ctl, frq));
ctl = cpu_to_le32(ctl);
frq = cpu_to_le32(frq);
if (ctl != chip->comm_page->control_register ||
frq != chip->comm_page->e3g_frq_register || force) {
chip->comm_page->e3g_frq_register = frq;
chip->comm_page->control_register = ctl;
clear_handshake(chip);
return send_vector(chip, DSP_VC_WRITE_CONTROL_REG);
}
DE_ACT(("WriteControlReg: not written, no change\n"));
return 0;
}
static int set_output_clock(struct echoaudio *chip, u16 clock)
{
DE_ACT(("set_output_clock: %d\n", clock));
switch (clock) {
case ECHO_CLOCK_SUPER:
clock = LAYLA20_OUTPUT_CLOCK_SUPER;
break;
case ECHO_CLOCK_WORD:
clock = LAYLA20_OUTPUT_CLOCK_WORD;
break;
default:
DE_ACT(("set_output_clock wrong clock\n"));
return -EINVAL;
}
if (wait_handshake(chip))
return -EIO;
chip->comm_page->output_clock = cpu_to_le16(clock);
chip->output_clock = clock;
clear_handshake(chip);
return send_vector(chip, DSP_VC_UPDATE_CLOCKS);
}
static int allocate_pipes(struct echoaudio *chip, struct audiopipe *pipe,
int pipe_index, int interleave)
{
int i;
u32 channel_mask;
char is_cyclic;
DE_ACT(("allocate_pipes: ch=%d int=%d\n", pipe_index, interleave));
if (chip->bad_board)
return -EIO;
is_cyclic = 1; /* This driver uses cyclic buffers only */
for (channel_mask = i = 0; i < interleave; i++)
channel_mask |= 1 << (pipe_index + i);
if (chip->pipe_alloc_mask & channel_mask) {
DE_ACT(("allocate_pipes: channel already open\n"));
return -EAGAIN;
}
chip->comm_page->position[pipe_index] = 0;
chip->pipe_alloc_mask |= channel_mask;
if (is_cyclic)
chip->pipe_cyclic_mask |= channel_mask;
pipe->index = pipe_index;
pipe->interleave = interleave;
pipe->state = PIPE_STATE_STOPPED;
/* The counter register is where the DSP writes the 32 bit DMA
position for a pipe. The DSP is constantly updating this value as
it moves data. The DMA counter is in units of bytes, not samples. */
pipe->dma_counter = &chip->comm_page->position[pipe_index];
*pipe->dma_counter = 0;
DE_ACT(("allocate_pipes: ok\n"));
return pipe_index;
}
static int start_transport(struct echoaudio *chip, u32 channel_mask,
u32 cyclic_mask)
{
DE_ACT(("start_transport %x\n", channel_mask));
if (wait_handshake(chip))
return -EIO;
chip->comm_page->cmd_start |= cpu_to_le32(channel_mask);
if (chip->comm_page->cmd_start) {
clear_handshake(chip);
send_vector(chip, DSP_VC_START_TRANSFER);
if (wait_handshake(chip))
return -EIO;
/* */
chip->active_mask |= channel_mask;
chip->comm_page->cmd_start = 0;
return 0;
}
DE_ACT(("start_transport: No pipes to start!\n"));
return -EINVAL;
}
static int set_sample_rate(struct echoaudio *chip, u32 rate)
{
if (snd_BUG_ON(rate < 8000 || rate > 50000))
return -EINVAL;
/* Only set the clock for internal mode. Do not return failure,
simply treat it as a non-event. */
if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
DE_ACT(("set_sample_rate: Cannot set sample rate - "
"clock not set to CLK_CLOCKININTERNAL\n"));
chip->comm_page->sample_rate = cpu_to_le32(rate);
chip->sample_rate = rate;
return 0;
}
if (wait_handshake(chip))
return -EIO;
DE_ACT(("set_sample_rate(%d)\n", rate));
chip->sample_rate = rate;
chip->comm_page->sample_rate = cpu_to_le32(rate);
clear_handshake(chip);
return send_vector(chip, DSP_VC_SET_LAYLA_SAMPLE_RATE);
}
static int stop_transport(struct echoaudio *chip, u32 channel_mask)
{
DE_ACT(("stop_transport %x\n", channel_mask));
if (wait_handshake(chip))
return -EIO;
chip->comm_page->cmd_stop |= cpu_to_le32(channel_mask);
chip->comm_page->cmd_reset |= cpu_to_le32(channel_mask);
if (chip->comm_page->cmd_reset) {
clear_handshake(chip);
send_vector(chip, DSP_VC_STOP_TRANSFER);
if (wait_handshake(chip))
return -EIO;
/* */
chip->active_mask &= ~channel_mask;
chip->comm_page->cmd_stop = 0;
chip->comm_page->cmd_reset = 0;
return 0;
}
DE_ACT(("stop_transport: No pipes to stop!\n"));
return 0;
}
/* Set the S/PDIF output format */
static int set_professional_spdif(struct echoaudio *chip, char prof)
{
u32 control_reg;
int err;
/* Clear the current S/PDIF flags */
control_reg = le32_to_cpu(chip->comm_page->control_register);
control_reg &= GML_SPDIF_FORMAT_CLEAR_MASK;
/* Set the new S/PDIF flags depending on the mode */
control_reg |= GML_SPDIF_TWO_CHANNEL | GML_SPDIF_24_BIT |
GML_SPDIF_COPY_PERMIT;
if (prof) {
/* Professional mode */
control_reg |= GML_SPDIF_PRO_MODE;
switch (chip->sample_rate) {
case 32000:
control_reg |= GML_SPDIF_SAMPLE_RATE0 |
GML_SPDIF_SAMPLE_RATE1;
break;
case 44100:
control_reg |= GML_SPDIF_SAMPLE_RATE0;
break;
case 48000:
control_reg |= GML_SPDIF_SAMPLE_RATE1;
break;
}
} else {
/* Consumer mode */
switch (chip->sample_rate) {
case 32000:
control_reg |= GML_SPDIF_SAMPLE_RATE0 |
GML_SPDIF_SAMPLE_RATE1;
break;
case 48000:
control_reg |= GML_SPDIF_SAMPLE_RATE1;
break;
}
}
if ((err = write_control_reg(chip, control_reg, FALSE)))
return err;
chip->professional_spdif = prof;
DE_ACT(("set_professional_spdif to %s\n",
prof ? "Professional" : "Consumer"));
return 0;
}
static int set_input_clock(struct echoaudio *chip, u16 clock)
{
u32 control_reg, clocks_from_dsp;
DE_ACT(("set_input_clock:\n"));
/* Mask off the clock select bits */
control_reg = le32_to_cpu(chip->comm_page->control_register) &
GML_CLOCK_CLEAR_MASK;
clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
switch (clock) {
case ECHO_CLOCK_INTERNAL:
DE_ACT(("Set Gina24 clock to INTERNAL\n"));
chip->input_clock = ECHO_CLOCK_INTERNAL;
return set_sample_rate(chip, chip->sample_rate);
case ECHO_CLOCK_SPDIF:
if (chip->digital_mode == DIGITAL_MODE_ADAT)
return -EAGAIN;
DE_ACT(("Set Gina24 clock to SPDIF\n"));
control_reg |= GML_SPDIF_CLOCK;
if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF96)
control_reg |= GML_DOUBLE_SPEED_MODE;
else
control_reg &= ~GML_DOUBLE_SPEED_MODE;
break;
case ECHO_CLOCK_ADAT:
if (chip->digital_mode != DIGITAL_MODE_ADAT)
return -EAGAIN;
DE_ACT(("Set Gina24 clock to ADAT\n"));
control_reg |= GML_ADAT_CLOCK;
control_reg &= ~GML_DOUBLE_SPEED_MODE;
break;
case ECHO_CLOCK_ESYNC:
DE_ACT(("Set Gina24 clock to ESYNC\n"));
control_reg |= GML_ESYNC_CLOCK;
control_reg &= ~GML_DOUBLE_SPEED_MODE;
break;
case ECHO_CLOCK_ESYNC96:
DE_ACT(("Set Gina24 clock to ESYNC96\n"));
control_reg |= GML_ESYNC_CLOCK | GML_DOUBLE_SPEED_MODE;
break;
default:
DE_ACT(("Input clock 0x%x not supported for Gina24\n", clock));
return -EINVAL;
}
chip->input_clock = clock;
return write_control_reg(chip, control_reg, TRUE);
}
static int sglist_add_mapping(struct echoaudio *chip, struct audiopipe *pipe,
dma_addr_t address, size_t length)
{
int head = pipe->sglist_head;
struct sg_entry *list = (struct sg_entry *)pipe->sgpage.area;
if (head < MAX_SGLIST_ENTRIES - 1) {
list[head].addr = cpu_to_le32(address);
list[head].size = cpu_to_le32(length);
pipe->sglist_head++;
} else {
DE_ACT(("SGlist: too many fragments\n"));
return -ENOMEM;
}
return 0;
}
static int free_pipes(struct echoaudio *chip, struct audiopipe *pipe)
{
u32 channel_mask;
int i;
DE_ACT(("free_pipes: Pipe %d\n", pipe->index));
if (snd_BUG_ON(!is_pipe_allocated(chip, pipe->index)))
return -EINVAL;
if (snd_BUG_ON(pipe->state != PIPE_STATE_STOPPED))
return -EINVAL;
for (channel_mask = i = 0; i < pipe->interleave; i++)
channel_mask |= 1 << (pipe->index + i);
chip->pipe_alloc_mask &= ~channel_mask;
chip->pipe_cyclic_mask &= ~channel_mask;
return 0;
}
static int set_sample_rate(struct echoaudio *chip, u32 rate)
{
u32 clock, control_reg, old_control_reg;
if (wait_handshake(chip))
return -EIO;
old_control_reg = le32_to_cpu(chip->comm_page->control_register);
control_reg = old_control_reg & ~INDIGO_EXPRESS_CLOCK_MASK;
switch (rate) {
case 32000:
clock = INDIGO_EXPRESS_32000;
break;
case 44100:
clock = INDIGO_EXPRESS_44100;
break;
case 48000:
clock = INDIGO_EXPRESS_48000;
break;
case 64000:
clock = INDIGO_EXPRESS_32000|INDIGO_EXPRESS_DOUBLE_SPEED;
break;
case 88200:
clock = INDIGO_EXPRESS_44100|INDIGO_EXPRESS_DOUBLE_SPEED;
break;
case 96000:
clock = INDIGO_EXPRESS_48000|INDIGO_EXPRESS_DOUBLE_SPEED;
break;
default:
return -EINVAL;
}
control_reg |= clock;
if (control_reg != old_control_reg) {
DE_ACT(("set_sample_rate: %d clock %d\n", rate, clock));
chip->comm_page->control_register = cpu_to_le32(control_reg);
chip->sample_rate = rate;
clear_handshake(chip);
return send_vector(chip, DSP_VC_UPDATE_CLOCKS);
}
return 0;
}
static int set_sample_rate(struct echoaudio *chip, u32 rate)
{
u32 control_reg;
switch (rate) {
case 96000:
control_reg = MIA_96000;
break;
case 88200:
control_reg = MIA_88200;
break;
case 48000:
control_reg = MIA_48000;
break;
case 44100:
control_reg = MIA_44100;
break;
case 32000:
control_reg = MIA_32000;
break;
default:
DE_ACT(("set_sample_rate: %d invalid!\n", rate));
return -EINVAL;
}
/* Override the clock setting if this Mia is set to S/PDIF clock */
if (chip->input_clock == ECHO_CLOCK_SPDIF)
control_reg |= MIA_SPDIF;
/* Set the control register if it has changed */
if (control_reg != le32_to_cpu(chip->comm_page->control_register)) {
if (wait_handshake(chip))
return -EIO;
chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */
chip->comm_page->control_register = cpu_to_le32(control_reg);
chip->sample_rate = rate;
clear_handshake(chip);
return send_vector(chip, DSP_VC_UPDATE_CLOCKS);
}
return 0;
}
/* This function routes the sound from a virtual channel to a real output */
static int set_vmixer_gain(struct echoaudio *chip, u16 output, u16 pipe,
int gain)
{
int index;
if (snd_BUG_ON(pipe >= num_pipes_out(chip) ||
output >= num_busses_out(chip)))
return -EINVAL;
if (wait_handshake(chip))
return -EIO;
chip->vmixer_gain[output][pipe] = gain;
index = output * num_pipes_out(chip) + pipe;
chip->comm_page->vmixer[index] = gain;
DE_ACT(("set_vmixer_gain: pipe %d, out %d = %d\n", pipe, output, gain));
return 0;
}
static int write_dsp(struct echoaudio *chip, u32 data)
{
u32 status, i;
for (i = 0; i < 10000000; i++) { /* */
status = get_dsp_register(chip, CHI32_STATUS_REG);
if ((status & CHI32_STATUS_HOST_WRITE_EMPTY) != 0) {
set_dsp_register(chip, CHI32_DATA_REG, data);
wmb(); /* */
return 0;
}
udelay(1);
cond_resched();
}
chip->bad_board = TRUE; /* */
DE_ACT((KERN_ERR "write_dsp: Set bad_board to TRUE\n"));
return -EIO;
}
static int send_vector(struct echoaudio *chip, u32 command)
{
int i;
wmb(); /* Flush all pending writes before sending the command */
/* Wait up to 100ms for the "vector busy" bit to be off */
for (i = 0; i < VECTOR_BUSY_TIMEOUT; i++) {
if (!(get_dsp_register(chip, CHI32_VECTOR_REG) &
CHI32_VECTOR_BUSY)) {
set_dsp_register(chip, CHI32_VECTOR_REG, command);
/*if (i) DE_ACT(("send_vector time: %d\n", i));*/
return 0;
}
udelay(1);
}
DE_ACT((KERN_ERR "timeout on send_vector\n"));
return -EBUSY;
}
static int send_vector(struct echoaudio *chip, u32 command)
{
int i;
wmb(); /* */
/* */
for (i = 0; i < VECTOR_BUSY_TIMEOUT; i++) {
if (!(get_dsp_register(chip, CHI32_VECTOR_REG) &
CHI32_VECTOR_BUSY)) {
set_dsp_register(chip, CHI32_VECTOR_REG, command);
/* */
return 0;
}
udelay(1);
}
DE_ACT((KERN_ERR "timeout on send_vector\n"));
return -EBUSY;
}
static int write_control_reg(struct echoaudio *chip, u32 value, char force)
{
/* Handle the digital input auto-mute */
if (chip->digital_in_automute)
value |= GML_DIGITAL_IN_AUTO_MUTE;
else
value &= ~GML_DIGITAL_IN_AUTO_MUTE;
DE_ACT(("write_control_reg: 0x%x\n", value));
/* Write the control register */
value = cpu_to_le32(value);
if (value != chip->comm_page->control_register || force) {
if (wait_handshake(chip))
return -EIO;
chip->comm_page->control_register = value;
clear_handshake(chip);
return send_vector(chip, DSP_VC_WRITE_CONTROL_REG);
}
return 0;
}
static int set_sample_rate(struct echoaudio *chip, u32 rate)
{
u32 control_reg;
switch (rate) {
case 96000:
control_reg = MIA_96000;
break;
case 88200:
control_reg = MIA_88200;
break;
case 48000:
control_reg = MIA_48000;
break;
case 44100:
control_reg = MIA_44100;
break;
case 32000:
control_reg = MIA_32000;
break;
default:
DE_ACT(("set_sample_rate: %d invalid!\n", rate));
return -EINVAL;
}
/* */
if (control_reg != le32_to_cpu(chip->comm_page->control_register)) {
if (wait_handshake(chip))
return -EIO;
chip->comm_page->sample_rate = cpu_to_le32(rate); /* */
chip->comm_page->control_register = cpu_to_le32(control_reg);
chip->sample_rate = rate;
clear_handshake(chip);
return send_vector(chip, DSP_VC_UPDATE_CLOCKS);
}
return 0;
}
static int rest_in_peace(struct echoaudio *chip)
{
DE_ACT(("rest_in_peace() open=%x\n", chip->pipe_alloc_mask));
/* */
stop_transport(chip, chip->active_mask);
set_meters_on(chip, FALSE);
#ifdef ECHOCARD_HAS_MIDI
enable_midi_input(chip, FALSE);
#endif
/* */
if (chip->dsp_code) {
/* */
chip->dsp_code = NULL;
/* */
return send_vector(chip, DSP_VC_GO_COMATOSE);
}
return 0;
}
static int rest_in_peace(struct echoaudio *chip)
{
DE_ACT(("rest_in_peace() open=%x\n", chip->pipe_alloc_mask));
/* Stops all active pipes (just to be sure) */
stop_transport(chip, chip->active_mask);
set_meters_on(chip, FALSE);
#ifdef ECHOCARD_HAS_MIDI
enable_midi_input(chip, FALSE);
#endif
/* Go to sleep */
if (chip->dsp_code) {
/* Make load_firmware do a complete reload */
chip->dsp_code = NULL;
/* Put the DSP to sleep */
return send_vector(chip, DSP_VC_GO_COMATOSE);
}
return 0;
}
static int set_input_clock(struct echoaudio *chip, u16 clock_source)
{
u16 clock;
u32 rate;
DE_ACT(("set_input_clock:\n"));
rate = 0;
switch (clock_source) {
case ECHO_CLOCK_INTERNAL:
DE_ACT(("Set Layla20 clock to INTERNAL\n"));
rate = chip->sample_rate;
clock = LAYLA20_CLOCK_INTERNAL;
break;
case ECHO_CLOCK_SPDIF:
DE_ACT(("Set Layla20 clock to SPDIF\n"));
clock = LAYLA20_CLOCK_SPDIF;
break;
case ECHO_CLOCK_WORD:
DE_ACT(("Set Layla20 clock to WORD\n"));
clock = LAYLA20_CLOCK_WORD;
break;
case ECHO_CLOCK_SUPER:
DE_ACT(("Set Layla20 clock to SUPER\n"));
clock = LAYLA20_CLOCK_SUPER;
break;
default:
DE_ACT(("Input clock 0x%x not supported for Layla24\n",
clock_source));
return -EINVAL;
}
chip->input_clock = clock_source;
chip->comm_page->input_clock = cpu_to_le16(clock);
clear_handshake(chip);
send_vector(chip, DSP_VC_UPDATE_CLOCKS);
if (rate)
set_sample_rate(chip, rate);
return 0;
}
