int disp_bls_set_backlight(unsigned int level)
{
unsigned int mapped_level;
DISP_MSG("disp_bls_set_backlight: %d, gBLSPowerOn = %d\n", level, gBLSPowerOn);
mutex_lock(&backlight_mutex);
if(level && !clock_is_on(MT_CG_PWM_MM_SW_CG))
enable_clock(MT_CG_PWM_MM_SW_CG, "DDP");
if (level && !clock_is_on(MT_CG_MDP_BLS_26M_SW_CG))
{
// remove CG control to DDP path
ASSERT(0);
if (!gBLSPowerOn)
{
// config BLS parameter
disp_bls_config();
}
}
#ifdef USE_DISP_BLS_MUTEX
disp_bls_get_mutex();
#else
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x3);
#endif
mapped_level = brightness_mapping(level);
DISP_MSG("after mapping, mapped_level: %d\n", mapped_level);
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, mapped_level);
if (mapped_level) // enable PWM generator
DISP_REG_SET(DISP_REG_BLS_EN, DISP_REG_GET(DISP_REG_BLS_EN) | 0x10000);
else // disable PWM generator
DISP_REG_SET(DISP_REG_BLS_EN, DISP_REG_GET(DISP_REG_BLS_EN) & 0xFFFEFFFF);
DISP_MSG("after SET, PWM_DUTY: %d\n", DISP_REG_GET(DISP_REG_BLS_PWM_DUTY));
#ifdef USE_DISP_BLS_MUTEX
disp_bls_release_mutex();
#else
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x0);
#endif
if(!level && clock_is_on(MT_CG_PWM_MM_SW_CG))
disable_clock(MT_CG_PWM_MM_SW_CG, "DDP");
if (!level && gBLSPowerOn)
{
DISP_MSG("disp_bls_set_backlight: disable clock\n");
// disable_clock(MT_CG_DISP0_SMI_LARB0 , "DDP");
gBLSPowerOn = 0;
}
mutex_unlock(&backlight_mutex);
return 0;
}
void disp_bls_update_gamma_lut(void)
{
int index, i;
unsigned long regValue;
unsigned long CurVal, Count;
#ifndef NEW_GAMMA_ARRAY_ARRANGEMENT
// make it build fail for EPC rule after MP
DISP_MSG("disp_bls_update_gamma_lut!\n");
#endif
DISP_MSG("disp_bls_update_gamma_lut!\n");
// init gamma table
for(index = 0; index < 3; index++)
{
for(Count = 0; Count < 257 ; Count++)
{
g_gamma_lut.entry[index][Count] = g_gamma_index.entry[index][Count];
}
}
// disable BLS_EN first
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x00000003);
regValue = DISP_REG_GET(DISP_REG_BLS_EN);
DISP_REG_SET(DISP_REG_BLS_EN, regValue & 0x00010000);
DISP_MSG("ready to modify gamma lut, set BLS_EN=%x\n", DISP_REG_GET(DISP_REG_BLS_EN));
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x00000000);
DISP_REG_SET(DISP_REG_BLS_LUT_UPDATE, 0x1);
for (i = 0; i < 256 ; i++)
{
CurVal = (((g_gamma_lut.entry[0][i]&0x3FF)<<20) | ((g_gamma_lut.entry[1][i]&0x3FF)<<10) | (g_gamma_lut.entry[2][i]&0x3FF));
DISP_REG_SET(DISP_REG_BLS_GAMMA_LUT(i), CurVal);
DISP_DBG("[%d] GAMMA LUT = 0x%x, (%lu, %lu, %lu)\n", i, DISP_REG_GET(DISP_REG_BLS_GAMMA_LUT(i)),
g_gamma_lut.entry[0][i], g_gamma_lut.entry[1][i], g_gamma_lut.entry[2][i]);
}
/* Set Gamma Last point*/
DISP_REG_SET(DISP_REG_BLS_GAMMA_SETTING, 0x00000001);
// set gamma last index
CurVal = (((g_gamma_lut.entry[0][256]&0x3FF)<<20) | ((g_gamma_lut.entry[1][256]&0x3FF)<<10) | (g_gamma_lut.entry[2][256]&0x3FF));
DISP_REG_SET(DISP_REG_BLS_GAMMA_BOUNDARY, CurVal);
DISP_REG_SET(DISP_REG_BLS_LUT_UPDATE, 0);
//DISP_REG_SET(DISP_REG_BLS_EN, regValue);
//set BLS_EN to oringinal value
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x00000003);
DISP_REG_SET(DISP_REG_BLS_EN, regValue);
DISP_MSG("end modifying gamma lut, set BLS_EN=%x\n", DISP_REG_GET(DISP_REG_BLS_EN));
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x00000000);
}
static int WDMADumpHidenReg(unsigned idx)
{
unsigned int i = 0;
DISP_MSG("[DDP] dump WDMA 0xac:\n [DDP]:");
for (i = 0; i < 16; i++) {
DISP_REG_SET_FIELD(WDMA_CFG_FLD_REG_MASK,
idx * DISP_INDEX_OFFSET + DISP_REG_WDMA_CFG, i);
DISP_MSG("0x%x, ", DISP_REG_GET(DISP_REG_WDMA_CFG));
}
return 0;
}
int disp_bls_config(void)
{
#if !defined(MTK_AAL_SUPPORT)
if (!clock_is_on(MT_CG_MDP_BLS_26M_SW_CG))
{
// remove CG control to DDP path
ASSERT(0);
}
if (!gBLSPowerOn)
{
DISP_MSG("disp_bls_config: enable clock\n");
// enable_clock(MT_CG_DISP0_SMI_LARB0, "DDP");
gBLSPowerOn = 1;
}
#ifdef USE_DISP_BLS_MUTEX
DISP_MSG("disp_bls_config : gBLSMutexID = %d\n", gBLSMutexID);
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_RST(gBLSMutexID), 1);
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_RST(gBLSMutexID), 0);
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_MOD(gBLSMutexID), 0x200); // BLS
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_SOF(gBLSMutexID), 0); // single mode
if (disp_bls_get_mutex() == 0)
{
#else
DISP_MSG("disp_bls_config\n");
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x3);
#endif
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, DISP_REG_GET(DISP_REG_BLS_PWM_DUTY));
DISP_REG_SET(DISP_REG_BLS_PWM_CON, 0x0);
DISP_REG_SET(DISP_REG_BLS_EN, 0x00010001); // enable BLS_EN
#ifdef USE_DISP_BLS_MUTEX
if (disp_bls_release_mutex() == 0)
return 0;
}
return -1;
#else
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x0);
#endif
#endif
DISP_MSG("disp_bls_config:-\n");
return 0;
return 0;
}
void disp_bls_init(unsigned int srcWidth, unsigned int srcHeight)
{
DISP_MSG("disp_bls_init : srcWidth = %d, srcHeight = %d\n", srcWidth, srcHeight);
// TODO: fix register setting
DISP_REG_SET(DISP_REG_BLS_SRC_SIZE, (srcHeight << 16) | srcWidth);
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, DISP_REG_GET(DISP_REG_BLS_PWM_DUTY));
DISP_REG_SET(DISP_REG_BLS_PWM_CON, 0x0);
DISP_REG_SET(DISP_REG_BLS_INTEN, 0xF);
disp_bls_update_gamma_lut();
//disp_bls_update_pwm_lut(); // not used in 6572
#if 0 // TODO: fix Dither setting
// Dithering
DISP_REG_SET(DISP_REG_BLS_DITHER(0), 0x00000001);
DISP_REG_SET(DISP_REG_BLS_DITHER(6), 0x00000000);
DISP_REG_SET(DISP_REG_BLS_DITHER(13), 0x00000222);
DISP_REG_SET(DISP_REG_BLS_DITHER(14), 0x00000000);
DISP_REG_SET(DISP_REG_BLS_DITHER(15), 0x22220001);
DISP_REG_SET(DISP_REG_BLS_DITHER(16), 0x22222222);
DISP_REG_SET(DISP_REG_BLS_DITHER(17), 0x00000000);
#endif
DISP_REG_SET(DISP_REG_BLS_EN, 0x00010001); // enable BLS_EN
disp_bls_config_full(srcWidth, srcHeight);
#if 0
disp_dump_reg(DISP_MODULE_BLS);
#endif
}
int disp_bls_set_max_backlight(unsigned int level)
{
mutex_lock(&backlight_mutex);
DISP_MSG("disp_bls_set_max_backlight: level = %d, current level = %d\n", level * 1023 / 255, gMaxLevel);
//PWM duty input = PWM_DUTY_IN / 1024
gMaxLevel = level * 1023 / 255;
mutex_unlock(&backlight_mutex);
return 0;
}
int disp_bls_set_backlight(unsigned int level)
{
DISP_AAL_PARAM *param;
DISP_MSG("disp_bls_set_backlight: %d\n", level);
mutex_lock(&backlight_mutex);
disp_aal_lock();
param = get_aal_config();
param->pwmDuty = brightness_mapping(level);
disp_aal_unlock();
mutex_unlock(&backlight_mutex);
return 0;
}
char* get_fmt_name(DISP_MODULE_ENUM module, unsigned int fmt)
{
if(module==DISP_MODULE_OVL)
{
switch(fmt)
{
case 0: return "rgb888";
case 1: return "rgb565";
case 2: return "argb8888";
case 3: return "pargb8888";
case 4: return "xrgb8888";
case 8: return "yuyv";
case 9: return "uvvy";
case 10: return "yvyu";
case 11: return "vyuy";
case 15: return "yuv444";
default:
DISP_MSG("ddp_get_fmt_name, unknown fmt=%d, module=%d \n", fmt, module);
return "unknown";
}
}
else if(module==DISP_MODULE_RDMA) // todo: confirm with designers
{
switch(fmt)
{
case 0: return "yuyv";
case 1: return "uyvy";
case 2: return "yvyu";
case 3: return "vyuy";
case 4: return "rgb565";
case 8: return "rgb888";
case 16: return "argb8888";
default:
DISP_MSG("ddp_get_fmt_name, unknown fmt=%d, module=%d \n", fmt, module);
return "unknown";
}
}
return "unknown";
}
void ddp_enable_bls(int BLS_switch)
{
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x00000003);
if(BLS_switch == FALSE)
DISP_REG_SET(DISP_REG_BLS_EN, 0x00010000);
else
DISP_REG_SET(DISP_REG_BLS_EN, 0x00010001);
DISP_MSG("aal_debug_flag changed,aal_debug_flag=%d, set BLS_EN=%x", aal_debug_flag, DISP_REG_GET(DISP_REG_BLS_EN));
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x00000000);
}
void disp_bls_update_gamma_lut(void)
{
#if defined(DDP_GAMMA_SUPPORT)
int index, i;
unsigned long regValue;
unsigned long CurVal, Count;
DISP_MSG("disp_bls_update_gamma_lut!\n");
if (DISP_REG_GET(DISP_REG_BLS_EN) & 0x1)
{
DISP_ERR("try to update gamma lut while BLS is active\n");
return;
}
// init gamma table
for(index = 0; index < 3; index++)
{
for(Count = 0; Count < 257 ; Count++)
{
g_gamma_lut.entry[index][Count] = g_gamma_index.entry[index][Count];
}
}
DISP_REG_SET(DISP_REG_BLS_LUT_UPDATE, 0x1);
for (i = 0; i < 256 ; i++)
{
CurVal = (((g_gamma_lut.entry[0][i]&0x3FF)<<20) | ((g_gamma_lut.entry[1][i]&0x3FF)<<10) | (g_gamma_lut.entry[2][i]&0x3FF));
DISP_REG_SET(DISP_REG_BLS_GAMMA_LUT(i), CurVal);
DISP_DBG("[%d] GAMMA LUT = 0x%x, (%lu, %lu, %lu)\n", i, DISP_REG_GET(DISP_REG_BLS_GAMMA_LUT(i)),
g_gamma_lut.entry[0][i], g_gamma_lut.entry[1][i], g_gamma_lut.entry[2][i]);
}
/* Set Gamma Last point*/
DISP_REG_SET(DISP_REG_BLS_GAMMA_SETTING, 0x00000001);
// set gamma last index
CurVal = (((g_gamma_lut.entry[0][256]&0x3FF)<<20) | ((g_gamma_lut.entry[1][256]&0x3FF)<<10) | (g_gamma_lut.entry[2][256]&0x3FF));
DISP_REG_SET(DISP_REG_BLS_GAMMA_BOUNDARY, CurVal);
DISP_REG_SET(DISP_REG_BLS_LUT_UPDATE, 0);
#endif
}
void disp_bls_update_pwm_lut(void)
{
int i;
unsigned int regValue;
DISP_MSG("disp_bls_update_pwm_lut!\n");
regValue = DISP_REG_GET(DISP_REG_BLS_EN);
if (regValue & 0x1) {
DISP_ERR("update PWM LUT while BLS func enabled!\n");
disp_dump_reg(DISP_MODULE_BLS);
}
//DISP_REG_SET(DISP_REG_BLS_EN, (regValue & 0x00010000));
for (i = 0; i < PWM_LUT_ENTRY; i++)
{
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(i), g_pwm_lut.entry[i]);
DISP_DBG("[%d] PWM LUT = 0x%x (%lu)\n", i, DISP_REG_GET(DISP_REG_BLS_LUMINANCE(i)), g_pwm_lut.entry[i]);
}
DISP_REG_SET(DISP_REG_BLS_LUMINANCE_255, g_pwm_lut.entry[PWM_LUT_ENTRY-1]);
//DISP_REG_SET(DISP_REG_BLS_EN, regValue);
}
int disp_dump_reg(DISP_MODULE_ENUM module)
{
unsigned int index;
switch(module)
{
case DISP_MODULE_ROT:
DISP_MSG("===== DISP ROT Reg Dump: ============\n");
DISP_MSG("(+000)ROT_EN =0x%x\n", DISP_REG_GET(DISP_REG_ROT_EN ));
DISP_MSG("(+008)ROT_RESET =0x%x\n", DISP_REG_GET(DISP_REG_ROT_RESET ));
DISP_MSG("(+010)ROT_INTERRUPT_ENABLE =0x%x\n", DISP_REG_GET(DISP_REG_ROT_INTERRUPT_ENABLE ));
DISP_MSG("(+018)ROT_INTERRUPT_STATUS =0x%x\n", DISP_REG_GET(DISP_REG_ROT_INTERRUPT_STATUS ));
DISP_MSG("(+020)ROT_CON =0x%x\n", DISP_REG_GET(DISP_REG_ROT_CON ));
DISP_MSG("(+028)ROT_GMCIF_CON =0x%x\n", DISP_REG_GET(DISP_REG_ROT_GMCIF_CON ));
DISP_MSG("(+030)ROT_SRC_CON =0x%x\n", DISP_REG_GET(DISP_REG_ROT_SRC_CON ));
DISP_MSG("(+040)ROT_SRC_BASE_0 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_SRC_BASE_0 ));
DISP_MSG("(+048)ROT_SRC_BASE_1 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_SRC_BASE_1 ));
DISP_MSG("(+050)ROT_SRC_BASE_2 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_SRC_BASE_2 ));
DISP_MSG("(+060)ROT_MF_BKGD_SIZE_IN_BYTE =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MF_BKGD_SIZE_IN_BYTE ));
DISP_MSG("(+070)ROT_MF_SRC_SIZE =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MF_SRC_SIZE ));
DISP_MSG("(+078)ROT_MF_CLIP_SIZE =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MF_CLIP_SIZE ));
DISP_MSG("(+080)ROT_MF_OFFSET_1 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MF_OFFSET_1 ));
DISP_MSG("(+088)ROT_MF_PAR =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MF_PAR ));
DISP_MSG("(+090)ROT_SF_BKGD_SIZE_IN_BYTE =0x%x\n", DISP_REG_GET(DISP_REG_ROT_SF_BKGD_SIZE_IN_BYTE ));
DISP_MSG("(+0B8)ROT_SF_PAR =0x%x\n", DISP_REG_GET(DISP_REG_ROT_SF_PAR ));
DISP_MSG("(+0C0)ROT_MB_DEPTH =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MB_DEPTH ));
DISP_MSG("(+0C8)ROT_MB_BASE =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MB_BASE ));
DISP_MSG("(+0D0)ROT_MB_CON =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MB_CON ));
DISP_MSG("(+0D8)ROT_SB_DEPTH =0x%x\n", DISP_REG_GET(DISP_REG_ROT_SB_DEPTH ));
DISP_MSG("(+0E0)ROT_SB_BASE =0x%x\n", DISP_REG_GET(DISP_REG_ROT_SB_BASE ));
DISP_MSG("(+0E8)ROT_SB_CON =0x%x\n", DISP_REG_GET(DISP_REG_ROT_SB_CON ));
DISP_MSG("(+0F0)ROT_VC1_RANGE =0x%x\n", DISP_REG_GET(DISP_REG_ROT_VC1_RANGE ));
DISP_MSG("(+200)ROT_TRANSFORM_0 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_TRANSFORM_0 ));
DISP_MSG("(+208)ROT_TRANSFORM_1 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_TRANSFORM_1 ));
DISP_MSG("(+210)ROT_TRANSFORM_2 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_TRANSFORM_2 ));
DISP_MSG("(+218)ROT_TRANSFORM_3 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_TRANSFORM_3 ));
DISP_MSG("(+220)ROT_TRANSFORM_4 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_TRANSFORM_4 ));
DISP_MSG("(+228)ROT_TRANSFORM_5 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_TRANSFORM_5 ));
DISP_MSG("(+230)ROT_TRANSFORM_6 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_TRANSFORM_6 ));
DISP_MSG("(+238)ROT_TRANSFORM_7 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_TRANSFORM_7 ));
DISP_MSG("(+240)ROT_RESV_DUMMY_0 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_RESV_DUMMY_0 ));
DISP_MSG("(+300)ROT_CHKS_EXTR =0x%x\n", DISP_REG_GET(DISP_REG_ROT_CHKS_EXTR ));
DISP_MSG("(+308)ROT_CHKS_INTW =0x%x\n", DISP_REG_GET(DISP_REG_ROT_CHKS_INTW ));
DISP_MSG("(+310)ROT_CHKS_INTR =0x%x\n", DISP_REG_GET(DISP_REG_ROT_CHKS_INTR ));
DISP_MSG("(+318)ROT_CHKS_ROTO =0x%x\n", DISP_REG_GET(DISP_REG_ROT_CHKS_ROTO ));
DISP_MSG("(+320)ROT_CHKS_SRIY =0x%x\n", DISP_REG_GET(DISP_REG_ROT_CHKS_SRIY ));
DISP_MSG("(+328)ROT_CHKS_SRIU =0x%x\n", DISP_REG_GET(DISP_REG_ROT_CHKS_SRIU ));
DISP_MSG("(+330)ROT_CHKS_SRIV =0x%x\n", DISP_REG_GET(DISP_REG_ROT_CHKS_SRIV ));
DISP_MSG("(+338)ROT_CHKS_SROY =0x%x\n", DISP_REG_GET(DISP_REG_ROT_CHKS_SROY ));
DISP_MSG("(+340)ROT_CHKS_SROU =0x%x\n", DISP_REG_GET(DISP_REG_ROT_CHKS_SROU ));
DISP_MSG("(+348)ROT_CHKS_SROV =0x%x\n", DISP_REG_GET(DISP_REG_ROT_CHKS_SROV ));
DISP_MSG("(+350)ROT_CHKS_VUPI =0x%x\n", DISP_REG_GET(DISP_REG_ROT_CHKS_VUPI ));
DISP_MSG("(+358)ROT_CHKS_VUPO =0x%x\n", DISP_REG_GET(DISP_REG_ROT_CHKS_VUPO ));
DISP_MSG("(+380)ROT_DEBUG_CON =0x%x\n", DISP_REG_GET(DISP_REG_ROT_DEBUG_CON ));
DISP_MSG("(+400)ROT_MON_STA_0 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_0 ));
DISP_MSG("(+408)ROT_MON_STA_1 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_1 ));
DISP_MSG("(+410)ROT_MON_STA_2 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_2 ));
DISP_MSG("(+418)ROT_MON_STA_3 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_3 ));
DISP_MSG("(+420)ROT_MON_STA_4 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_4 ));
DISP_MSG("(+428)ROT_MON_STA_5 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_5 ));
DISP_MSG("(+430)ROT_MON_STA_6 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_6 ));
DISP_MSG("(+438)ROT_MON_STA_7 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_7 ));
DISP_MSG("(+440)ROT_MON_STA_8 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_8 ));
DISP_MSG("(+448)ROT_MON_STA_9 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_9 ));
DISP_MSG("(+450)ROT_MON_STA_10 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_10 ));
DISP_MSG("(+458)ROT_MON_STA_11 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_11 ));
DISP_MSG("(+460)ROT_MON_STA_12 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_12 ));
DISP_MSG("(+468)ROT_MON_STA_13 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_13 ));
DISP_MSG("(+470)ROT_MON_STA_14 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_14 ));
DISP_MSG("(+478)ROT_MON_STA_15 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_15 ));
DISP_MSG("(+480)ROT_MON_STA_16 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_16 ));
DISP_MSG("(+488)ROT_MON_STA_17 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_17 ));
DISP_MSG("(+490)ROT_MON_STA_18 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_18 ));
DISP_MSG("(+498)ROT_MON_STA_19 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_19 ));
DISP_MSG("(+4A0)ROT_MON_STA_20 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_20 ));
DISP_MSG("(+4A8)ROT_MON_STA_21 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_21 ));
DISP_MSG("(+4B0)ROT_MON_STA_22 =0x%x\n", DISP_REG_GET(DISP_REG_ROT_MON_STA_22 ));
break;
case DISP_MODULE_SCL:
DISP_MSG("===== DISP SCL Reg Dump: ============\n");
DISP_MSG("(+000)SCL_CTRL =0x%x \n", DISP_REG_GET(DISP_REG_SCL_CTRL ));
DISP_MSG("(+004)SCL_INTEN =0x%x \n", DISP_REG_GET(DISP_REG_SCL_INTEN ));
DISP_MSG("(+008)SCL_INTSTA =0x%x \n", DISP_REG_GET(DISP_REG_SCL_INTSTA ));
DISP_MSG("(+00C)SCL_STATUS =0x%x \n", DISP_REG_GET(DISP_REG_SCL_STATUS ));
DISP_MSG("(+010)SCL_CFG =0x%x \n", DISP_REG_GET(DISP_REG_SCL_CFG ));
DISP_MSG("(+018)SCL_INP_CHKSUM =0x%x \n", DISP_REG_GET(DISP_REG_SCL_INP_CHKSUM ));
DISP_MSG("(+01C)SCL_OUTP_CHKSUM=0x%x \n", DISP_REG_GET(DISP_REG_SCL_OUTP_CHKSUM));
DISP_MSG("(+020)SCL_HRZ_CFG =0x%x \n", DISP_REG_GET(DISP_REG_SCL_HRZ_CFG ));
DISP_MSG("(+024)SCL_HRZ_SIZE =0x%x \n", DISP_REG_GET(DISP_REG_SCL_HRZ_SIZE ));
DISP_MSG("(+028)SCL_HRZ_FACTOR =0x%x \n", DISP_REG_GET(DISP_REG_SCL_HRZ_FACTOR ));
DISP_MSG("(+02C)SCL_HRZ_OFFSET =0x%x \n", DISP_REG_GET(DISP_REG_SCL_HRZ_OFFSET ));
DISP_MSG("(+040)SCL_VRZ_CFG =0x%x \n", DISP_REG_GET(DISP_REG_SCL_VRZ_CFG ));
DISP_MSG("(+044)SCL_VRZ_SIZE =0x%x \n", DISP_REG_GET(DISP_REG_SCL_VRZ_SIZE ));
DISP_MSG("(+048)SCL_VRZ_FACTOR =0x%x \n", DISP_REG_GET(DISP_REG_SCL_VRZ_FACTOR ));
DISP_MSG("(+04C)SCL_VRZ_OFFSET =0x%x \n", DISP_REG_GET(DISP_REG_SCL_VRZ_OFFSET ));
DISP_MSG("(+060)SCL_EXT_COEF =0x%x \n", DISP_REG_GET(DISP_REG_SCL_EXT_COEF ));
DISP_MSG("(+064)SCL_PEAK_CFG =0x%x \n", DISP_REG_GET(DISP_REG_SCL_PEAK_CFG ));
break;
case DISP_MODULE_OVL:
DISP_MSG("===== DISP OVL Reg Dump: ============\n");
DISP_MSG("(000)OVL_STA =0x%x \n", DISP_REG_GET(DISP_REG_OVL_STA ));
DISP_MSG("(004)OVL_INTEN =0x%x \n", DISP_REG_GET(DISP_REG_OVL_INTEN ));
DISP_MSG("(008)OVL_INTSTA =0x%x \n", DISP_REG_GET(DISP_REG_OVL_INTSTA ));
DISP_MSG("(00C)OVL_EN =0x%x \n", DISP_REG_GET(DISP_REG_OVL_EN ));
DISP_MSG("(010)OVL_TRIG =0x%x \n", DISP_REG_GET(DISP_REG_OVL_TRIG ));
DISP_MSG("(014)OVL_RST =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RST ));
DISP_MSG("(020)OVL_ROI_SIZE =0x%x \n", DISP_REG_GET(DISP_REG_OVL_ROI_SIZE ));
DISP_MSG("(024)OVL_DATAPATH_CON =0x%x \n", DISP_REG_GET(DISP_REG_OVL_DATAPATH_CON ));
DISP_MSG("(028)OVL_ROI_BGCLR =0x%x \n", DISP_REG_GET(DISP_REG_OVL_ROI_BGCLR ));
DISP_MSG("(02C)OVL_SRC_CON =0x%x \n", DISP_REG_GET(DISP_REG_OVL_SRC_CON ));
DISP_MSG("(030)OVL_L0_CON =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L0_CON ));
DISP_MSG("(034)OVL_L0_SRCKEY =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L0_SRCKEY ));
DISP_MSG("(038)OVL_L0_SRC_SIZE =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L0_SRC_SIZE ));
DISP_MSG("(03C)OVL_L0_OFFSET =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L0_OFFSET ));
DISP_MSG("(040)OVL_L0_ADDR =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L0_ADDR ));
DISP_MSG("(044)OVL_L0_PITCH =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L0_PITCH ));
DISP_MSG("(0C0)OVL_RDMA0_CTRL =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA0_CTRL ));
DISP_MSG("(0C4)OVL_RDMA0_MEM_START_TRIG =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_START_TRIG ));
DISP_MSG("(0C8)OVL_RDMA0_MEM_GMC_SETTING =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING ));
DISP_MSG("(0CC)OVL_RDMA0_MEM_SLOW_CON =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_SLOW_CON ));
DISP_MSG("(0D0)OVL_RDMA0_FIFO_CTRL =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA0_FIFO_CTRL ));
DISP_MSG("(050)OVL_L1_CON =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L1_CON ));
DISP_MSG("(054)OVL_L1_SRCKEY =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L1_SRCKEY ));
DISP_MSG("(058)OVL_L1_SRC_SIZE =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L1_SRC_SIZE ));
DISP_MSG("(05C)OVL_L1_OFFSET =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L1_OFFSET ));
DISP_MSG("(060)OVL_L1_ADDR =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L1_ADDR ));
DISP_MSG("(064)OVL_L1_PITCH =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L1_PITCH ));
DISP_MSG("(0E0)OVL_RDMA1_CTRL =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA1_CTRL ));
DISP_MSG("(0E4)OVL_RDMA1_MEM_START_TRIG =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_START_TRIG ));
DISP_MSG("(0E8)OVL_RDMA1_MEM_GMC_SETTING =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING ));
DISP_MSG("(0EC)OVL_RDMA1_MEM_SLOW_CON =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_SLOW_CON ));
DISP_MSG("(0F0)OVL_RDMA1_FIFO_CTRL =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA1_FIFO_CTRL ));
DISP_MSG("(070)OVL_L2_CON =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L2_CON ));
DISP_MSG("(074)OVL_L2_SRCKEY =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L2_SRCKEY ));
DISP_MSG("(078)OVL_L2_SRC_SIZE =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L2_SRC_SIZE ));
DISP_MSG("(07C)OVL_L2_OFFSET =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L2_OFFSET ));
DISP_MSG("(080)OVL_L2_ADDR =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L2_ADDR ));
DISP_MSG("(084)OVL_L2_PITCH =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L2_PITCH ));
DISP_MSG("(100)OVL_RDMA2_CTRL =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA2_CTRL ));
DISP_MSG("(104)OVL_RDMA2_MEM_START_TRIG =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_START_TRIG ));
DISP_MSG("(108)OVL_RDMA2_MEM_GMC_SETTING =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING ));
DISP_MSG("(10C)OVL_RDMA2_MEM_SLOW_CON =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_SLOW_CON ));
DISP_MSG("(110)OVL_RDMA2_FIFO_CTRL =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA2_FIFO_CTRL ));
DISP_MSG("(090)OVL_L3_CON =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L3_CON ));
DISP_MSG("(094)OVL_L3_SRCKEY =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L3_SRCKEY ));
DISP_MSG("(098)OVL_L3_SRC_SIZE =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L3_SRC_SIZE ));
DISP_MSG("(09C)OVL_L3_OFFSET =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L3_OFFSET ));
DISP_MSG("(0A0)OVL_L3_ADDR =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L3_ADDR ));
DISP_MSG("(0A4)OVL_L3_PITCH =0x%x \n", DISP_REG_GET(DISP_REG_OVL_L3_PITCH ));
DISP_MSG("(120)OVL_RDMA3_CTRL =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA3_CTRL ));
DISP_MSG("(124)OVL_RDMA3_MEM_START_TRIG =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_START_TRIG ));
DISP_MSG("(128)OVL_RDMA3_MEM_GMC_SETTING =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING ));
DISP_MSG("(12C)OVL_RDMA3_MEM_SLOW_CON =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_SLOW_CON ));
DISP_MSG("(130)OVL_RDMA3_FIFO_CTRL =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA3_FIFO_CTRL ));
DISP_MSG("(1C4)OVL_DEBUG_MON_SEL =0x%x \n", DISP_REG_GET(DISP_REG_OVL_DEBUG_MON_SEL ));
DISP_MSG("(1C4)OVL_RDMA0_MEM_GMC_SETTING2 =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING2));
DISP_MSG("(1C8)OVL_RDMA1_MEM_GMC_SETTING2 =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING2));
DISP_MSG("(1CC)OVL_RDMA2_MEM_GMC_SETTING2 =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING2));
DISP_MSG("(1D0)OVL_RDMA3_MEM_GMC_SETTING2 =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING2));
DISP_MSG("(240)OVL_FLOW_CTRL_DBG =0x%x \n", DISP_REG_GET(DISP_REG_OVL_FLOW_CTRL_DBG ));
DISP_MSG("(244)OVL_ADDCON_DBG =0x%x \n", DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG ));
DISP_MSG("(248)OVL_OUTMUX_DBG =0x%x \n", DISP_REG_GET(DISP_REG_OVL_OUTMUX_DBG ));
DISP_MSG("(24C)OVL_RDMA0_DBG =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA0_DBG ));
DISP_MSG("(250)OVL_RDMA1_DBG =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA1_DBG ));
DISP_MSG("(254)OVL_RDMA2_DBG =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA2_DBG ));
DISP_MSG("(258)OVL_RDMA3_DBG =0x%x \n", DISP_REG_GET(DISP_REG_OVL_RDMA3_DBG ));
break;
case DISP_MODULE_COLOR:
break;
case DISP_MODULE_TDSHP:
break;
case DISP_MODULE_BLS:
break;
case DISP_MODULE_WDMA0:
case DISP_MODULE_WDMA1:
if(DISP_MODULE_WDMA0==module)
{
index = 0;
}
else if(DISP_MODULE_WDMA1==module)
{
index = 1;
}
DISP_MSG("===== DISP WDMA%d Reg Dump: ============\n", index);
DISP_MSG("(000)WDMA_INTEN =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_INTEN +0x1000*index) );
DISP_MSG("(004)WDMA_INTSTA =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_INTSTA +0x1000*index) );
DISP_MSG("(008)WDMA_EN =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_EN +0x1000*index) );
DISP_MSG("(00C)WDMA_RST =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_RST +0x1000*index) );
DISP_MSG("(010)WDMA_SMI_CON =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_SMI_CON +0x1000*index) );
DISP_MSG("(014)WDMA_CFG =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_CFG +0x1000*index) );
DISP_MSG("(018)WDMA_SRC_SIZE =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_SRC_SIZE +0x1000*index) );
DISP_MSG("(01C)WDMA_CLIP_SIZE =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_CLIP_SIZE +0x1000*index) );
DISP_MSG("(020)WDMA_CLIP_COORD =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_CLIP_COORD +0x1000*index) );
DISP_MSG("(024)WDMA_DST_ADDR =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_DST_ADDR +0x1000*index) );
DISP_MSG("(028)WDMA_DST_W_IN_BYTE =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_DST_W_IN_BYTE+0x1000*index) );
DISP_MSG("(02C)WDMA_ALPHA =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_ALPHA +0x1000*index) );
DISP_MSG("(030)WDMA_BUF_ADDR =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_BUF_ADDR +0x1000*index) );
DISP_MSG("(034)WDMA_STA =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_STA +0x1000*index) );
DISP_MSG("(038)WDMA_BUF_CON1 =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_BUF_CON1 +0x1000*index) );
DISP_MSG("(03C)WDMA_BUF_CON2 =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_BUF_CON2 +0x1000*index) );
DISP_MSG("(040)WDMA_C00 =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_C00 +0x1000*index) );
DISP_MSG("(044)WDMA_C02 =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_C02 +0x1000*index) );
DISP_MSG("(048)WDMA_C10 =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_C10 +0x1000*index) );
DISP_MSG("(04C)WDMA_C12 =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_C12 +0x1000*index) );
DISP_MSG("(050)WDMA_C20 =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_C20 +0x1000*index) );
DISP_MSG("(054)WDMA_C22 =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_C22 +0x1000*index) );
DISP_MSG("(058)WDMA_PRE_ADD0 =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_PRE_ADD0 +0x1000*index) );
DISP_MSG("(05C)WDMA_PRE_ADD2 =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_PRE_ADD2 +0x1000*index) );
DISP_MSG("(060)WDMA_POST_ADD0 =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_POST_ADD0 +0x1000*index) );
DISP_MSG("(064)WDMA_POST_ADD2 =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_POST_ADD2 +0x1000*index) );
DISP_MSG("(070)WDMA_DST_U_ADDR =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_DST_U_ADDR +0x1000*index) );
DISP_MSG("(074)WDMA_DST_V_ADDR =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_DST_V_ADDR +0x1000*index) );
DISP_MSG("(078)WDMA_DST_UV_PITCH =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_DST_UV_PITCH +0x1000*index) );
DISP_MSG("(090)WDMA_DITHER_CON =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_DITHER_CON +0x1000*index) );
DISP_MSG("(0A0)WDMA_FLOW_CTRL_DBG =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_FLOW_CTRL_DBG+0x1000*index) );
DISP_MSG("(0A4)WDMA_EXEC_DBG =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_EXEC_DBG +0x1000*index) );
DISP_MSG("(0A8)WDMA_CLIP_DBG =0x%x \n", DISP_REG_GET(DISP_REG_WDMA_CLIP_DBG +0x1000*index) );
break;
case DISP_MODULE_RDMA0:
case DISP_MODULE_RDMA1:
if(DISP_MODULE_RDMA0==module)
{
index = 0;
}
else if(DISP_MODULE_RDMA1==module)
{
index = 1;
}
DISP_MSG("===== DISP RDMA%d Reg Dump: ======== \n", index);
DISP_MSG("(000)RDMA_INT_ENABLE =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_INT_ENABLE +0x1000*index));
DISP_MSG("(004)RDMA_INT_STATUS =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_INT_STATUS +0x1000*index));
DISP_MSG("(010)RDMA_GLOBAL_CON =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON +0x1000*index));
DISP_MSG("(014)RDMA_SIZE_CON_0 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0 +0x1000*index));
DISP_MSG("(018)RDMA_SIZE_CON_1 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1 +0x1000*index));
DISP_MSG("(024)RDMA_MEM_CON =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_MEM_CON +0x1000*index));
DISP_MSG("(028)RDMA_MEM_START_ADDR =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR +0x1000*index));
DISP_MSG("(02C)RDMA_MEM_SRC_PITCH =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_MEM_SRC_PITCH +0x1000*index));
DISP_MSG("(030)RDMA_MEM_GMC_SETTING_0 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0+0x1000*index));
DISP_MSG("(034)RDMA_MEM_SLOW_CON =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_MEM_SLOW_CON +0x1000*index));
DISP_MSG("(030)RDMA_MEM_GMC_SETTING_1 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1+0x1000*index));
DISP_MSG("(040)RDMA_FIFO_CON =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_FIFO_CON +0x1000*index));
DISP_MSG("(054)RDMA_CF_00 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_00 +0x1000*index));
DISP_MSG("(058)RDMA_CF_01 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_01 +0x1000*index));
DISP_MSG("(05C)RDMA_CF_02 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_02 +0x1000*index));
DISP_MSG("(060)RDMA_CF_10 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_10 +0x1000*index));
DISP_MSG("(064)RDMA_CF_11 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_11 +0x1000*index));
DISP_MSG("(068)RDMA_CF_12 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_12 +0x1000*index));
DISP_MSG("(06C)RDMA_CF_20 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_20 +0x1000*index));
DISP_MSG("(070)RDMA_CF_21 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_21 +0x1000*index));
DISP_MSG("(074)RDMA_CF_22 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_22 +0x1000*index));
DISP_MSG("(078)RDMA_CF_PRE_ADD0 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_PRE_ADD0 +0x1000*index));
DISP_MSG("(07C)RDMA_CF_PRE_ADD1 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_PRE_ADD1 +0x1000*index));
DISP_MSG("(080)RDMA_CF_PRE_ADD2 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_PRE_ADD2 +0x1000*index));
DISP_MSG("(084)RDMA_CF_POST_ADD0 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_POST_ADD0 +0x1000*index));
DISP_MSG("(088)RDMA_CF_POST_ADD1 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_POST_ADD1 +0x1000*index));
DISP_MSG("(08C)RDMA_CF_POST_ADD2 =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_CF_POST_ADD2 +0x1000*index));
DISP_MSG("(090)RDMA_DUMMY =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_DUMMY +0x1000*index));
DISP_MSG("(094)RDMA_DEBUG_OUT_SEL =0x%x \n", DISP_REG_GET(DISP_REG_RDMA_DEBUG_OUT_SEL +0x1000*index));
break;
case DISP_MODULE_CMDQ:
DISP_MSG("===== DISP CMDQ Reg Dump: ============\n");
DISP_MSG("(0x10)CMDQ_IRQ_FLAG =0x%x \n", DISP_REG_GET(DISP_REG_CMDQ_IRQ_FLAG ));
DISP_MSG("(0x20)CMDQ_LOADED_THR =0x%x \n", DISP_REG_GET(DISP_REG_CMDQ_LOADED_THR ));
DISP_MSG("(0x30)CMDQ_THR_SLOT_CYCLES =0x%x \n", DISP_REG_GET(DISP_REG_CMDQ_THR_SLOT_CYCLES ));
DISP_MSG("(0x40)CMDQ_BUS_CTRL =0x%x \n", DISP_REG_GET(DISP_REG_CMDQ_BUS_CTRL ));
DISP_MSG("(0x50)CMDQ_ABORT =0x%x \n", DISP_REG_GET(DISP_REG_CMDQ_ABORT ));
for(index=0; index<CMDQ_THREAD_NUM; index++)
{
DISP_MSG("(0x%x)CMDQ_THRx_RESET%d =0x%x \n", (0x100 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_RESET(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_EN%d =0x%x \n", (0x104 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_EN(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_SUSPEND%d =0x%x \n", (0x108 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_SUSPEND(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_STATUS%d =0x%x \n", (0x10c + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_STATUS(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_IRQ_FLAG%d =0x%x \n", (0x110 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_IRQ_FLAG(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_IRQ_FLAG_EN%d =0x%x \n", (0x114 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_IRQ_FLAG_EN(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_SECURITY%d =0x%x \n", (0x118 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_SECURITY(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_PC%d =0x%x \n", (0x120 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_PC(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_END_ADDR%d =0x%x \n", (0x124 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_END_ADDR(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_EXEC_CMDS_CNT%d =0x%x \n", (0x128 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_EXEC_CMDS_CNT(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_WAIT_EVENTS0%d =0x%x \n", (0x130 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_WAIT_EVENTS0(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_WAIT_EVENTS1%d =0x%x \n", (0x134 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_WAIT_EVENTS1(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_OBSERVED_EVENTS0%d =0x%x \n", (0x140 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_OBSERVED_EVENTS0(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_OBSERVED_EVENTS1%d =0x%x \n", (0x144 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_OBSERVED_EVENTS1(index) ));
DISP_MSG("(0x%x)CMDQ_THRx_OBSERVED_EVENTS0_CLR%d =0x%x \n", (0x148 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_OBSERVED_EVENTS0_CLR(index)));
DISP_MSG("(0x%x)CMDQ_THRx_OBSERVED_EVENTS1_CLR%d =0x%x \n", (0x14c + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_OBSERVED_EVENTS1_CLR(index)));
DISP_MSG("(0x%x)CMDQ_THRx_INSTN_TIMEOUT_CYCLES%d =0x%x \n", (0x150 + 0x80*index), index, DISP_REG_GET(DISP_REG_CMDQ_THRx_INSTN_TIMEOUT_CYCLES(index)));
}
break;
case DISP_MODULE_GAMMA:
break;
case DISP_MODULE_DBI:
break;
case DISP_MODULE_DSI:
case DISP_MODULE_DSI_VDO:
case DISP_MODULE_DSI_CMD:
break;
case DISP_MODULE_DPI1:
break;
case DISP_MODULE_DPI0:
/*
DISP_MSG("===== DISP DPI0 Reg Dump: ============\n");
DISP_MSG("(0x00)DPI0_EN_REG = 0x%x \n", *DPI0_EN_REG );
DISP_MSG("(0x04)DPI0_RST_REG = 0x%x \n", *DPI0_RST_REG );
DISP_MSG("(0x08)DPI0_INTEN_REG = 0x%x \n", *DPI0_INTEN_REG );
DISP_MSG("(0x0C)DPI0_INTSTA_REG = 0x%x \n", *DPI0_INTSTA_REG );
DISP_MSG("(0x10)DPI0_CON_REG = 0x%x \n", *DPI0_CON_REG );
DISP_MSG("(0x14)DPI0_CLKCON_REG = 0x%x \n", *DPI0_CLKCON_REG );
DISP_MSG("(0x18)DPI0_SIZE_REG = 0x%x \n", *DPI0_SIZE_REG );
DISP_MSG("(0x1C)DPI0_TGEN_HWIDTH_REG = 0x%x \n", *DPI0_TGEN_HWIDTH_REG );
DISP_MSG("(0x20)DPI0_TGEN_HPORCH_REG = 0x%x \n", *DPI0_TGEN_HPORCH_REG );
DISP_MSG("(0x24)DPI0_TGEN_VWIDTH_LODD_REG = 0x%x \n", *DPI0_TGEN_VWIDTH_LODD_REG );
DISP_MSG("(0x28)DPI0_TGEN_VPORCH_LODD_REG = 0x%x \n", *DPI0_TGEN_VPORCH_LODD_REG );
DISP_MSG("(0x2C)DPI0_TGEN_WWIDTH_LEVEN_REG= 0x%x \n", *DPI0_TGEN_WWIDTH_LEVEN_REG);
DISP_MSG("(0x30)DPI0_TGEN_VPORCH_LEVEN_REG= 0x%x \n", *DPI0_TGEN_VPORCH_LEVEN_REG);
DISP_MSG("(0x34)DPI0_TGEN_VWIDTH_RODD_REG = 0x%x \n", *DPI0_TGEN_VWIDTH_RODD_REG );
DISP_MSG("(0x38)DPI0_TGEN_VPORCH_RODD_REG = 0x%x \n", *DPI0_TGEN_VPORCH_RODD_REG );
DISP_MSG("(0x50)DPI0_BG_HCNTL_REG = 0x%x \n", *DPI0_BG_HCNTL_REG );
DISP_MSG("(0x54)DPI0_BG_VCNTL_REG = 0x%x \n", *DPI0_BG_VCNTL_REG );
DISP_MSG("(0x60)DPI0_STATUS_REG = 0x%x \n", *DPI0_STATUS_REG );
DISP_MSG("(0x64)DPI0_MATRIX_COEFF_SET0_REG= 0x%x \n", *DPI0_MATRIX_COEFF_SET0_REG);
DISP_MSG("(0x68)DPI0_MATRIX_COEFF_SET1_REG= 0x%x \n", *DPI0_MATRIX_COEFF_SET1_REG);
DISP_MSG("(0x6C)DPI0_MATRIX_COEFF_SET2_REG= 0x%x \n", *DPI0_MATRIX_COEFF_SET2_REG);
DISP_MSG("(0X8C)DPI0_Y_LIMIT_REG = 0x%x \n", *DPI0_Y_LIMIT_REG );
DISP_MSG("(0x90)DPI0_C_LIMIT_REG = 0x%x \n", *DPI0_C_LIMIT_REG );
*/
break;
case DISP_MODULE_CONFIG:
DISP_MSG("(0x020)CFG_SCL_MOUT_EN =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_SCL_MOUT_EN ));
DISP_MSG("(0x024)CFG_OVL_MOUT_EN =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_OVL_MOUT_EN ));
DISP_MSG("(0x028)CFG_COLOR_MOUT_EN =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_COLOR_MOUT_EN ));
DISP_MSG("(0x02C)CFG_TDSHP_MOUT_EN =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_TDSHP_MOUT_EN ));
DISP_MSG("(0x030)CFG_MOUT_RST =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MOUT_RST ));
DISP_MSG("(0x034)CFG_RDMA0_OUT_SEL =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_RDMA0_OUT_SEL ));
DISP_MSG("(0x038)CFG_RDMA1_OUT_SEL =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_RDMA1_OUT_SEL ));
DISP_MSG("(0x03C)CFG_OVL_PQ_OUT_SEL =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_OVL_PQ_OUT_SEL ));
DISP_MSG("(0x040)CFG_WDMA0_SEL =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_WDMA0_SEL ));
DISP_MSG("(0x044)CFG_OVL_SEL =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_OVL_SEL ));
DISP_MSG("(0x048)CFG_OVL_PQ_IN_SEL =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_OVL_PQ_IN_SEL ));
DISP_MSG("(0x04C)CFG_COLOR_SEL =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_COLOR_SEL ));
DISP_MSG("(0x050)CFG_TDSHP_SEL =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_TDSHP_SEL ));
DISP_MSG("(0x054)CFG_BLS_SEL =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_BLS_SEL ));
DISP_MSG("(0x058)CFG_DBI_SEL =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_DBI_SEL ));
DISP_MSG("(0x05C)CFG_DPI0_SEL =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_DPI0_SEL ));
DISP_MSG("(0x60))CFG_MISC =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MISC ));
DISP_MSG("(0x70))CFG_PATH_DEBUG0 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_PATH_DEBUG0 ));
DISP_MSG("(0x74))CFG_PATH_DEBUG1 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_PATH_DEBUG1 ));
DISP_MSG("(0x78))CFG_PATH_DEBUG2 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_PATH_DEBUG2 ));
DISP_MSG("(0x7C))CFG_PATH_DEBUG3 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_PATH_DEBUG3 ));
DISP_MSG("(0x80))CFG_PATH_DEBUG4 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_PATH_DEBUG4 ));
DISP_MSG("(0x100)CFG_CG_CON0 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_CG_CON0 ));
DISP_MSG("(0x104)CFG_CG_SET0 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_CG_SET0 ));
DISP_MSG("(0x108)CFG_CG_CLR0 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_CG_CLR0 ));
DISP_MSG("(0x110)CFG_CG_CON1 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_CG_CON1 ));
DISP_MSG("(0x114)CFG_CG_SET1 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_CG_SET1 ));
DISP_MSG("(0x118)CFG_CG_CLR1 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_CG_CLR1 ));
DISP_MSG("(0x120)CFG_HW_DCM_EN0 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_HW_DCM_EN0 ));
DISP_MSG("(0x124)CFG_HW_DCM_EN_SET0 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_HW_DCM_EN_SET0 ));
DISP_MSG("(0x128)CFG_HW_DCM_EN_CLR0 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_HW_DCM_EN_CLR0 ));
DISP_MSG("(0x130)CFG_HW_DCM_EN1 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_HW_DCM_EN1 ));
DISP_MSG("(0x134)CFG_HW_DCM_EN_SET1 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_HW_DCM_EN_SET1 ));
DISP_MSG("(0x138)CFG_HW_DCM_EN_CLR1 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_HW_DCM_EN_CLR1 ));
DISP_MSG("(0x800)CFG_MBIST_DONE0 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_DONE0 ));
DISP_MSG("(0x804)CFG_MBIST_DONE1 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_DONE1 ));
DISP_MSG("(0x808)CFG_MBIST_FAIL0 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_FAIL0 ));
DISP_MSG("(0x80C)CFG_MBIST_FAIL1 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_FAIL1 ));
DISP_MSG("(0x810)CFG_MBIST_FAIL2 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_FAIL2 ));
DISP_MSG("(0x814)CFG_MBIST_HOLDB0 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_HOLDB0 ));
DISP_MSG("(0x818)CFG_MBIST_HOLDB1 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_HOLDB1 ));
DISP_MSG("(0x81C)CFG_MBIST_MODE0 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_MODE0 ));
DISP_MSG("(0x820)CFG_MBIST_MODE1 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_MODE1 ));
DISP_MSG("(0x824)CFG_MBIST_BSEL0 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_BSEL0 ));
DISP_MSG("(0x828)CFG_MBIST_BSEL1 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_BSEL1 ));
DISP_MSG("(0x82C)CFG_MBIST_BSEL2 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_BSEL2 ));
DISP_MSG("(0x830)CFG_MBIST_BSEL3 =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_BSEL3 ));
DISP_MSG("(0x834)CFG_MBIST_CON =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MBIST_CON ));
DISP_MSG("(0x870)CFG_DEBUG_OUT_SEL =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_DEBUG_OUT_SEL ));
DISP_MSG("(0x874)CFG_TEST_CLK_SEL =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_TEST_CLK_SEL ));
DISP_MSG("(0x880)CFG_DUMMY =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_DUMMY ));
DISP_MSG("((0x0) CFG_MUTEX_INTEN =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN ));
DISP_MSG("((0x4) CFG_MUTEX_INTSTA =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTSTA ));
DISP_MSG("((0x8) CFG_REG_UPD_TIMEOUT=0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_REG_UPD_TIMEOUT ));
DISP_MSG("((0xC) CFG_REG_COMMIT =0x%x \n", DISP_REG_GET(DISP_REG_CONFIG_REG_COMMIT ));
for(index=0; index<5; index++)
{
DISP_MSG("(0x%x)CFG_MUTEX_EN(%d) =0x%x \n", 0x20 + (0x20 * index), index, DISP_REG_GET(DISP_REG_CONFIG_MUTEX_EN(index) ));
DISP_MSG("(0x%x)CFG_MUTEX(%d) =0x%x \n", 0x24 + (0x20 * index), index, DISP_REG_GET(DISP_REG_CONFIG_MUTEX(index) ));
DISP_MSG("(0x%x)CFG_MUTEX_RST(%d) =0x%x \n", 0x28 + (0x20 * index), index, DISP_REG_GET(DISP_REG_CONFIG_MUTEX_RST(index) ));
DISP_MSG("(0x%x)CFG_MUTEX_MOD(%d) =0x%x \n", 0x2C + (0x20 * index), index, DISP_REG_GET(DISP_REG_CONFIG_MUTEX_MOD(index) ));
DISP_MSG("(0x%x)CFG_MUTEX_SOF(%d) =0x%x \n", 0x30 + (0x20 * index), index, DISP_REG_GET(DISP_REG_CONFIG_MUTEX_SOF(index) ));
}
break;
default:
DISP_MSG("disp_dump_reg() invalid module id=%d \n", module);
}
return 0;
}
static void process_dbg_opt(const char *opt)
{
char *buf = dbg_buf + strlen(dbg_buf);
if (0 == strncmp(opt, "regr:", 5))
{
char *p = (char *)opt + 5;
unsigned int addr = (unsigned int) simple_strtoul(p, &p, 16);
if (addr)
{
unsigned int regVal = DISP_REG_GET(addr);
DISP_MSG("regr: 0x%08X = 0x%08X\n", addr, regVal);
sprintf(buf, "regr: 0x%08X = 0x%08X\n", addr, regVal);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "regw:", 5))
{
char *p = (char *)opt + 5;
unsigned int addr = (unsigned int) simple_strtoul(p, &p, 16);
unsigned int val = (unsigned int) simple_strtoul(p + 1, &p, 16);
if (addr)
{
unsigned int regVal;
DISP_REG_SET(addr, val);
regVal = DISP_REG_GET(addr);
DISP_DBG("regw: 0x%08X, 0x%08X = 0x%08X\n", addr, val, regVal);
sprintf(buf, "regw: 0x%08X, 0x%08X = 0x%08X\n", addr, val, regVal);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "dbg_log:", 8))
{
char *p = (char *)opt + 8;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
dbg_log = 1;
else
dbg_log = 0;
sprintf(buf, "dbg_log: %d\n", dbg_log);
}
else if (0 == strncmp(opt, "irq_log:", 8))
{
char *p = (char *)opt + 8;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
irq_log = 1;
else
irq_log = 0;
sprintf(buf, "irq_log: %d\n", irq_log);
}
else if (0 == strncmp(opt, "backlight:", 10))
{
char *p = (char *)opt + 10;
unsigned int level = (unsigned int) simple_strtoul(p, &p, 10);
if (level)
{
disp_bls_set_backlight(level);
sprintf(buf, "backlight: %d\n", level);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "dump_reg:", 9))
{
char *p = (char *)opt + 9;
unsigned int module = (unsigned int) simple_strtoul(p, &p, 10);
DISP_MSG("process_dbg_opt, module=%d \n", module);
if (module<DISP_MODULE_MAX)
{
disp_dump_reg(module);
sprintf(buf, "dump_reg: %d\n", module);
} else {
DISP_MSG("process_dbg_opt2, module=%d \n", module);
goto Error;
}
}
else if (0 == strncmp(opt, "dump_aal:", 9))
{
char *p = (char *)opt + 9;
unsigned int arg = (unsigned int) simple_strtoul(p, &p, 10);
if (arg == 0)
{
int i;
unsigned int hist[LUMA_HIST_BIN];
disp_get_hist(hist);
for (i = 0; i < LUMA_HIST_BIN; i++)
{
DISP_DBG("LUMA_HIST_%02d: %d\n", i, hist[i]);
sprintf(dbg_buf + strlen(dbg_buf), "LUMA_HIST_%2d: %d\n", i, hist[i]);
}
}
else if (arg == 1)
{
int i;
DISP_AAL_PARAM param;
GetUpdateMutex();
memcpy(¶m, get_aal_config(), sizeof(DISP_AAL_PARAM));
ReleaseUpdateMutex();
DISP_DBG("pwmDuty: %lu\n", param.pwmDuty);
sprintf(dbg_buf + strlen(dbg_buf), "pwmDuty: %lu\n", param.pwmDuty);
for (i = 0; i < LUMA_CURVE_POINT; i++)
{
DISP_DBG("lumaCurve[%02d]: %lu\n", i, param.lumaCurve[i]);
sprintf(dbg_buf + strlen(dbg_buf), "lumaCurve[%02d]: %lu\n", i, param.lumaCurve[i]);
}
}
}
else if (0 == strncmp(opt, "debug:", 6))
{
char *p = (char *)opt + 6;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if(enable==1)
{
printk("[DDP] debug=1, trigger AEE\n");
aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT");
}
else if(enable==2)
{
ddp_mem_test();
}
else if(enable==3)
{
ddp_mem_test2();
}
}
else if (0 == strncmp(opt, "mmp", 3))
{
init_ddp_mmp_events();
}
else if (0 == strncmp(opt, "dpfd_ut1:", 9))
{
char *p = (char *)opt + 9;
unsigned int channel = (unsigned int) simple_strtoul(p, &p, 10);
ddpk_testfunc_1(channel);
}
else if (0 == strncmp(opt, "dpfd_ut2:", 9))
{
char *p = (char *)opt + 9;
unsigned int channel = (unsigned int) simple_strtoul(p, &p, 10);
ddpk_testfunc_2(channel);
}
else if (0 == strncmp(opt, "dpfd:log", 8))
{
}
else if (0 == strncmp(opt, "pqon", 4))
{
pq_debug_flag=0;
sprintf(buf, "Turn on PQ %d\n", pq_debug_flag);
}
else if (0 == strncmp(opt, "pqoff", 5))
{
pq_debug_flag=1;
sprintf(buf, "Turn off PQ %d\n", pq_debug_flag);
}
else if (0 == strncmp(opt, "pqdemo", 6))
{
pq_debug_flag=2;
sprintf(buf, "Turn on PQ (demo) %d\n", pq_debug_flag);
}
else if (0 == strncmp(opt, "pqstop", 6))
{
pq_debug_flag=3;
sprintf(buf, "Stop mutex update %d\n", pq_debug_flag);
}
else if (0 == strncmp(opt, "aalon", 5))
{
aal_debug_flag=0;
sprintf(buf, "resume aal update %d\n", aal_debug_flag);
}
else if (0 == strncmp(opt, "aaloff", 6))
{
aal_debug_flag=1;
sprintf(buf, "suspend aal update %d\n", aal_debug_flag);
}
else if (0 == strncmp(opt, "color_win:", 10))
{
char *p = (char *)opt + 10;
unsigned int sat_upper, sat_lower, hue_upper, hue_lower;
sat_upper = (unsigned int) simple_strtoul(p, &p, 10);
p++;
sat_lower = (unsigned int) simple_strtoul(p, &p, 10);
p++;
hue_upper = (unsigned int) simple_strtoul(p, &p, 10);
p++;
hue_lower = (unsigned int) simple_strtoul(p, &p, 10);
DISP_MSG("Set color_win: %u, %u, %u, %u\n", sat_upper, sat_lower, hue_upper, hue_lower);
disp_color_set_window(sat_upper, sat_lower, hue_upper, hue_lower);
}
else
{
goto Error;
}
return;
Error:
DISP_ERR("parse command error!\n%s\n\n%s", opt, STR_HELP);
}
void disp_bls_config_full(unsigned int width, unsigned int height)
{
unsigned int dither_bpp = DISP_GetOutputBPPforDithering();
DDP_DRV_DBG("dispsys_bypass_bls, width=%d, height=%d, reg=0x%x \n",
width, height, ((height<<16) + width));
DISP_REG_SET(DISP_REG_BLS_DEBUG ,0x00000003);
// DISP_REG_SET(DISP_REG_BLS_PWM_DUTY ,0x000003ff);
#if defined(DDP_GAMMA_SUPPORT)
DISP_REG_SET(DISP_REG_BLS_BLS_SETTING ,0x00100007); // remove gain setting here
#else
DISP_REG_SET(DISP_REG_BLS_BLS_SETTING ,0x00100000); // remove gain setting here
#endif
// DISP_REG_SET(DISP_REG_BLS_FANA_SETTING ,0x00000000);
DISP_REG_SET(DISP_REG_BLS_SRC_SIZE ,((height<<16) + width));
// DISP_REG_SET(DISP_REG_BLS_GAIN_SETTING ,0x00010001);
DISP_REG_SET(DISP_REG_BLS_GAMMA_SETTING ,0x00000001);
DISP_REG_SET(DISP_REG_BLS_GAMMA_BOUNDARY ,0x3fffffff);
#if 0
DISP_REG_SET(DISP_REG_BLS_MAXCLR_THD ,0x00002328);
DISP_REG_SET(DISP_REG_BLS_DISTPT_THD ,0x00006f54);
DISP_REG_SET(DISP_REG_BLS_MAXCLR_LIMIT ,0x00fa00b0);
DISP_REG_SET(DISP_REG_BLS_DISTPT_LIMIT ,0x00800020);
DISP_REG_SET(DISP_REG_BLS_AVE_SETTING ,0x00000010);
DISP_REG_SET(DISP_REG_BLS_AVE_LIMIT ,0x00f00060);
DISP_REG_SET(DISP_REG_BLS_DISTPT_SETTING ,0x00000000);
DISP_REG_SET(DISP_REG_BLS_SC_DIFF_THD ,0x00001770);
DISP_REG_SET(DISP_REG_BLS_SC_BIN_THD ,0x00000008);
DISP_REG_SET(DISP_REG_BLS_MAXCLR_GRADUAL ,0x00020001);
DISP_REG_SET(DISP_REG_BLS_DISTPT_GRADUAL ,0x00040001);
DISP_REG_SET(DISP_REG_BLS_FAST_IIR_XCOEFF ,0x01a201a2);
DISP_REG_SET(DISP_REG_BLS_FAST_IIR_YCOEFF ,0x00003cbc);
DISP_REG_SET(DISP_REG_BLS_SLOW_IIR_XCOEFF ,0x01500150);
DISP_REG_SET(DISP_REG_BLS_SLOW_IIR_YCOEFF ,0x00003d60);
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY ,0x000003ff);
DISP_REG_SET(DISP_REG_BLS_PWM_GRADUAL ,0x00000000); // default 0x80001
DISP_REG_SET(DISP_REG_BLS_PWM_CON ,0x00000000); // default 0x00001
#endif
/* BLS Luminance LUT */
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(0) ,0x00000000);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(1) ,0x00000004);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(2) ,0x00000010);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(3) ,0x00000024);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(4) ,0x00000040);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(5) ,0x00000064);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(6) ,0x00000090);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(7) ,0x000000C4);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(8) ,0x00000100);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(9) ,0x00000144);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(10) ,0x00000190);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(11) ,0x000001E4);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(12) ,0x00000240);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(13) ,0x00000244);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(14) ,0x00000310);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(15) ,0x00000384);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(16) ,0x00000400);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(17) ,0x00000484);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(18) ,0x00000510);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(19) ,0x000005A4);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(20) ,0x00000640);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(21) ,0x000006E4);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(22) ,0x00000790);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(23) ,0x00000843);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(24) ,0x000008FF);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(25) ,0x000009C3);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(26) ,0x00000A8F);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(27) ,0x00000B63);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(28) ,0x00000C3F);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(29) ,0x00000D23);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(30) ,0x00000E0F);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(31) ,0x00000F03);
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(32) ,0x00000FFF);
/* BLS Luminance 255 */
DISP_REG_SET(DISP_REG_BLS_LUMINANCE_255 ,0x00000FDF);
/* Dither */
DISP_REG_SET(DISP_REG_BLS_DITHER(5) ,0x00000000);
DISP_REG_SET(DISP_REG_BLS_DITHER(6) ,0x00003004);
DISP_REG_SET(DISP_REG_BLS_DITHER(7) ,0x00000000);
DISP_REG_SET(DISP_REG_BLS_DITHER(8) ,0x00000000);
DISP_REG_SET(DISP_REG_BLS_DITHER(9) ,0x00000000);
DISP_REG_SET(DISP_REG_BLS_DITHER(10) ,0x00000000);
DISP_REG_SET(DISP_REG_BLS_DITHER(11) ,0x00000000);
DISP_REG_SET(DISP_REG_BLS_DITHER(12) ,0x00000011);
DISP_REG_SET(DISP_REG_BLS_DITHER(13) ,0x00000000);
DISP_REG_SET(DISP_REG_BLS_DITHER(14) ,0x00000000);
/* output RGB888 */
if (dither_bpp == 16) // 565
{
DISP_REG_SET(DISP_REG_BLS_DITHER(15), 0x50500001);
DISP_REG_SET(DISP_REG_BLS_DITHER(16), 0x50504040);
DISP_REG_SET(DISP_REG_BLS_DITHER(0), 0x00000001);
}
else if (dither_bpp == 18) // 666
{
DISP_REG_SET(DISP_REG_BLS_DITHER(15), 0x40400001);
DISP_REG_SET(DISP_REG_BLS_DITHER(16), 0x40404040);
DISP_REG_SET(DISP_REG_BLS_DITHER(0), 0x00000001);
}
else if (dither_bpp == 24) // 888
{
DISP_REG_SET(DISP_REG_BLS_DITHER(15), 0x20200001);
DISP_REG_SET(DISP_REG_BLS_DITHER(16), 0x20202020);
DISP_REG_SET(DISP_REG_BLS_DITHER(0), 0x00000001);
}
else
{
DISP_MSG("error diter bpp = %d\n", dither_bpp);
DISP_REG_SET(DISP_REG_BLS_DITHER(0), 0x00000000);
}
DISP_REG_SET(DISP_REG_BLS_INTEN ,0x0000000f); // no scene change
DISP_REG_SET(DISP_REG_BLS_EN ,0x00010001);
DISP_REG_SET(DISP_REG_BLS_DEBUG ,0x00000000);
}
static void process_dbg_opt(const char *opt)
{
char *buf = dbg_buf + strlen(dbg_buf);
if (0 == strncmp(opt, "regr:", 5))
{
char *p = (char *)opt + 5;
unsigned int addr = (unsigned int) simple_strtoul(p, &p, 16);
if (addr)
{
unsigned int regVal = DISP_REG_GET(addr);
DISP_MSG("regr: 0x%08X = 0x%08X\n", addr, regVal);
sprintf(buf, "regr: 0x%08X = 0x%08X\n", addr, regVal);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "regw:", 5))
{
char *p = (char *)opt + 5;
unsigned int addr = (unsigned int) simple_strtoul(p, &p, 16);
unsigned int val = (unsigned int) simple_strtoul(p + 1, &p, 16);
if (addr)
{
unsigned int regVal;
DISP_REG_SET(addr, val);
regVal = DISP_REG_GET(addr);
DISP_DBG("regw: 0x%08X, 0x%08X = 0x%08X\n", addr, val, regVal);
sprintf(buf, "regw: 0x%08X, 0x%08X = 0x%08X\n", addr, val, regVal);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "dbg_log:", 8))
{
char *p = (char *)opt + 8;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
dbg_log = 1;
else
dbg_log = 0;
sprintf(buf, "dbg_log: %d\n", dbg_log);
}
else if (0 == strncmp(opt, "irq_log:", 8))
{
char *p = (char *)opt + 8;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
irq_log = 1;
else
irq_log = 0;
sprintf(buf, "irq_log: %d\n", irq_log);
}
else if (0 == strncmp(opt, "irq_err_log:", 12))
{
char *p = (char *)opt + 12;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
irq_err_log = 1;
else
irq_err_log = 0;
sprintf(buf, "irq_err_log: %d\n", irq_err_log);
}
else if (0 == strncmp(opt, "backlight:", 10))
{
char *p = (char *)opt + 10;
unsigned int level = (unsigned int) simple_strtoul(p, &p, 10);
if (level)
{
disp_bls_set_backlight(level);
sprintf(buf, "backlight: %d\n", level);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "dump_reg:", 9))
{
char *p = (char *)opt + 9;
unsigned int module = (unsigned int) simple_strtoul(p, &p, 10);
DISP_MSG("process_dbg_opt, module=%d \n", module);
if (module<DISP_MODULE_MAX)
{
disp_dump_reg(module);
sprintf(buf, "dump_reg: %d\n", module);
} else {
DISP_MSG("process_dbg_opt2, module=%d \n", module);
goto Error;
}
}
else if (0 == strncmp(opt, "dump_aal:", 9))
{
char *p = (char *)opt + 9;
unsigned int arg = (unsigned int) simple_strtoul(p, &p, 10);
if (arg == 0)
{
int i;
unsigned int hist[LUMA_HIST_BIN];
disp_get_hist(hist);
for (i = 0; i < LUMA_HIST_BIN; i++)
{
DISP_DBG("LUMA_HIST_%02d: %d\n", i, hist[i]);
sprintf(dbg_buf + strlen(dbg_buf), "LUMA_HIST_%2d: %d\n", i, hist[i]);
}
}
else if (arg == 1)
{
int i;
DISP_AAL_PARAM param;
GetUpdateMutex();
memcpy(¶m, get_aal_config(), sizeof(DISP_AAL_PARAM));
ReleaseUpdateMutex();
DISP_DBG("pwmDuty: %lu\n", param.pwmDuty);
sprintf(dbg_buf + strlen(dbg_buf), "pwmDuty: %lu\n", param.pwmDuty);
for (i = 0; i < LUMA_CURVE_POINT; i++)
{
DISP_DBG("lumaCurve[%02d]: %lu\n", i, param.lumaCurve[i]);
sprintf(dbg_buf + strlen(dbg_buf), "lumaCurve[%02d]: %lu\n", i, param.lumaCurve[i]);
}
}
}
else if (0 == strncmp(opt, "debug:", 6))
{
char *p = (char *)opt + 6;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if(enable==1)
{
printk("[DDP] debug=1, trigger AEE\n");
aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT");
}
else if(enable==2)
{
ddp_mem_test();
}
else if(enable==3)
{
ddp_mem_test2();
}
else if(enable==4)
{
DDP_IRQ_ERR("test 4");
}
else if(enable==5)
{
DISP_MSG("SMI_LARB_MON_REQ0=0x%x, SMI_LARB_MON_REQ1=0x%x, SMI_0=0x%x, SMI_600=0x%x, SMI_604=0x%x, SMI_610=0x%x, SMI_614=0x%x, \
color_h_cnt=%d, color_line_cnt=%d, ovl_add_con=0x%x, ovl_ctrl_flow=0x%x \n",
*(volatile unsigned int*)0xf4010450,
*(volatile unsigned int*)0xf4010454,
*(volatile unsigned int*)0xf4010000,
*(volatile unsigned int*)0xf4010600,
*(volatile unsigned int*)0xf4010604,
*(volatile unsigned int*)0xf4010610,
*(volatile unsigned int*)0xf4010614,
*(volatile unsigned int*)0xf400b404,
*(volatile unsigned int*)0xf400b408,
DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG),
DISP_REG_GET(DISP_REG_OVL_FLOW_CTRL_DBG));
sprintf(dbg_buf + strlen(dbg_buf), "SMI_LARB_MON_REQ0=0x%x, SMI_LARB_MON_REQ1=0x%x, SMI_0=0x%x, SMI_600=0x%x, SMI_604=0x%x, SMI_610=0x%x, SMI_614=0x%x,"
"color_h_cnt=%d, color_line_cnt=%d, ovl_add_con=0x%x, ovl_ctrl_flow=0x%x \n",
*(volatile unsigned int*)0xf4010450,
*(volatile unsigned int*)0xf4010454,
*(volatile unsigned int*)0xf4010000,
*(volatile unsigned int*)0xf4010600,
*(volatile unsigned int*)0xf4010604,
*(volatile unsigned int*)0xf4010610,
*(volatile unsigned int*)0xf4010614,
*(volatile unsigned int*)0xf400b404,
*(volatile unsigned int*)0xf400b408,
DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG),
DISP_REG_GET(DISP_REG_OVL_FLOW_CTRL_DBG));
}
