irqreturn_t decon_t_irq_handler(int irq, void *dev_data) { struct decon_device *decon = dev_data; u32 irq_sts_reg; spin_lock(&decon->slock); if ((decon->state == DECON_STATE_OFF) || (decon->state == DECON_STATE_LPD)) { goto irq_end; } irq_sts_reg = decon_reg_get_interrupt_and_clear(decon->id); if (irq_sts_reg & INTERRUPT_FIFO_LEVEL_INT_EN) { DISP_SS_EVENT_LOG(DISP_EVT_UNDERRUN, &decon->sd, ktime_set(0, 0)); decon_err("DECON_T FIFO underrun\n"); } if (irq_sts_reg & INTERRUPT_FRAME_DONE_INT_EN) { decon_lpd_trig_reset(decon); DISP_SS_EVENT_LOG(DISP_EVT_DECON_FRAMEDONE, &decon->sd, ktime_set(0, 0)); decon_dbg("%s Frame Done is occured. timeline:%d, %d\n", __func__, decon->timeline->value, decon->timeline_max); } if (irq_sts_reg & INTERRUPT_RESOURCE_CONFLICT_INT_EN) DISP_SS_EVENT_LOG(DISP_EVT_RSC_CONFLICT, &decon->sd, ktime_set(0, 0)); irq_end: spin_unlock(&decon->slock); return IRQ_HANDLED; }
static int vpp_wait_for_update(struct vpp_dev *vpp) { int update_cnt; int ret; if (test_bit(VPP_POWER_ON, &vpp->state)) { update_cnt = vpp->update_cnt_prev; ret = wait_event_interruptible_timeout(vpp->update_queue, (update_cnt != vpp->update_cnt), msecs_to_jiffies(17)); if (ret == 0) { dev_err(DEV, "timeout of shadow update(%d, %d)\n", update_cnt, vpp->update_cnt); return -ETIMEDOUT; } DISP_SS_EVENT_LOG(DISP_EVT_VPP_UPDATE_DONE, vpp->sd, ktime_set(0, 0)); } return 0; }
irqreturn_t decon_ext_dsi_irq_handler(int irq, void *dev_data) { struct decon_device *decon = dev_data; ktime_t timestamp = ktime_get(); u32 irq_sts_reg; u32 wb_irq_sts_reg; spin_lock(&decon->slock); irq_sts_reg = decon_read(decon->id, VIDINTCON1); wb_irq_sts_reg = decon_read(decon->id, VIDINTCON3); if (irq_sts_reg & VIDINTCON1_INT_FRAME) { /* VSYNC interrupt, accept it */ decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_FRAME); decon->vsync_info.timestamp = timestamp; wake_up_interruptible_all(&decon->vsync_info.wait); } if (irq_sts_reg & VIDINTCON1_INT_FIFO) { decon_err("DECON-ext FIFO underrun\n"); decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_FIFO); } if (irq_sts_reg & VIDINTCON1_INT_I80) { decon_write_mask(decon->id, VIDINTCON1, ~0, VIDINTCON1_INT_I80); wake_up_interruptible_all(&decon->wait_frmdone); } #if 0 if (wb_irq_sts_reg & VIDINTCON3_WB_FRAME_DONE) { decon_dbg("write-back frame done\n"); DISP_SS_EVENT_LOG(DISP_EVT_WB_FRAME_DONE, &decon->sd, ktime_set(0, 0)); decon_write_mask(decon->id, VIDINTCON3, ~0, VIDINTCON3_WB_FRAME_DONE); atomic_set(&decon->wb_done, STATE_DONE); wake_up_interruptible_all(&decon->wait_frmdone); decon_reg_per_frame_off(decon->id); decon_reg_update_standalone(decon->id); decon_reg_wb_swtrigger(decon->id); decon_reg_wait_stop_status_timeout(decon->id, 20 * 1000); } #endif spin_unlock(&decon->slock); return IRQ_HANDLED; }