DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8), DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"), DIV_A(sclk_apll, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3, "sclk_apll"), DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, CLK_SET_RATE_PARENT, 0), DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0), DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0), DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0), DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0), }; /* list of divider clocks supported in exynos4210 soc */
};
static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
/*
* NOTE: Following table is sorted by (clock domain, register address,
* bitfield shift) triplet in ascending order. When adding new entries,
* please make sure that the order is kept, to avoid merge conflicts
* and make further work with defined data easier.
*/
/*
* CMU_CPU
*/
DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
/*
* CMU_TOP
*/
DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
24, 3),
DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3),
DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
DIV(none, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), DIV(none, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), DIV(none, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), DIV(none, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), DIV(none, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), DIV(none, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), DIV(none, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), DIV(none, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), DIV(none, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), DIV(none, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), DIV(none, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), DIV(none, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), DIV_A(none, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3, "aclk300_disp1"), DIV(none, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), /* DISP1 Block */ DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), DIV(dout_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), /* Audio Block */ DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), DIV(none, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), /* USB3.0 */ DIV(none, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), DIV(none, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4), DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4), DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4), DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4), DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4), DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4), DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4), DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4), DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8), DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4), DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8), DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6), DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6), DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4), DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"), DIV_F(none, "div_mipi1_pre", "div_mipi1", DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0), DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0), DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0), DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0), DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0), DIV_F(none, "div_spi_pre0", "div_spi0", DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0), DIV_F(none, "div_spi_pre1", "div_spi1", DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0), DIV_F(none, "div_spi_pre2", "div_spi2",
