void gdma1_check_mpu_violation(u32 addr, int wr_vio)
{
printk(KERN_CRIT "GDMA1 checks EMI MPU violation.\n");
printk(KERN_CRIT "addr = 0x%x, %s violation.\n", addr, wr_vio? "Write": "Read");
printk(KERN_CRIT "DMA SRC = 0x%x.\n", readl(DMA_SRC(DMA_BASE_CH(0))));
printk(KERN_CRIT "DMA DST = 0x%x.\n", readl(DMA_DST(DMA_BASE_CH(0))));
printk(KERN_CRIT "DMA COUNT = 0x%x.\n", readl(DMA_LEN1(DMA_BASE_CH(0))));
printk(KERN_CRIT "DMA CON = 0x%x.\n", readl(DMA_CON(DMA_BASE_CH(0))));
}
int mt65xx_start_gdma(int channel)
{
if ((channel < GDMA_START) || (channel >= (GDMA_START + NR_GDMA_CHANNEL))) {
return -DMA_ERR_INVALID_CH;
}else if (dma_ctrl[channel].in_use == 0) {
return -DMA_ERR_CH_FREE;
}
writel(DMA_INT_FLAG_CLR_BIT, DMA_INT_FLAG(DMA_BASE_CH(channel)));
mt65xx_reg_sync_writel(DMA_START_BIT, DMA_START(DMA_BASE_CH(channel)));
return 0;
}
int mt65xx_stop_gdma(int channel)
{
if (channel < GDMA_START) {
return -DMA_ERR_INVALID_CH;
}
if (channel >= (GDMA_START + NR_GDMA_CHANNEL)) {
return -DMA_ERR_INVALID_CH;
}
if (dma_ctrl[channel].in_use == 0) {
return -DMA_ERR_CH_FREE;
}
writel(DMA_FLUSH_BIT, DMA_FLUSH(DMA_BASE_CH(channel)));
while (readl(DMA_START(DMA_BASE_CH(channel))));
writel(DMA_FLUSH_CLR_BIT, DMA_FLUSH(DMA_BASE_CH(channel)));
mt65xx_reg_sync_writel(DMA_INT_FLAG_CLR_BIT, DMA_INT_FLAG(DMA_BASE_CH(channel)));
return 0;
}
static irqreturn_t gdma1_irq_handler(int irq, void *dev_id)
{
const unsigned glbsta = readl(DMA_GLOBAL_INT_FLAG);
dbgmsg(KERN_DEBUG"DMA Module - %s ISR Start\n", __func__);
dbgmsg(KERN_DEBUG"DMA Module - GLBSTA = 0x%x\n", glbsta);
if (glbsta & DMA_GLBSTA_IT(G_DMA_1)){
if (dma_ctrl[G_DMA_1].isr_cb) {
dma_ctrl[G_DMA_1].isr_cb(dma_ctrl[G_DMA_1].data);
}
mt65xx_reg_sync_writel(DMA_INT_FLAG_CLR_BIT, DMA_INT_FLAG(DMA_BASE_CH(G_DMA_1)));
#if(DMA_DEBUG == 1)
glbsta = readl(DMA_GLOBAL_INT_FLAG);
printk(KERN_DEBUG"DMA Module - GLBSTA after ack = 0x%x\n", glbsta);
#endif
}
dbgmsg(KERN_DEBUG"DMA Module - %s ISR END\n", __func__);
return IRQ_HANDLED;
}
static void mt_irda_start_tx(struct mt_irda_framer *framer);
static ssize_t mt_irda_show_stat(struct device *dev, struct device_attribute *attr, char *buf);
static ssize_t mt_irda_store_stat(struct device *dev, struct device_attribute *attr,const char *buf, size_t count);
static int mt_irda_change_speed(struct mt_irda_framer *framer);
struct mt_irda_framer *framer_dev;
static int rx_invert=0;
static int tx_invert=0;
static int hard_ware=1;
module_param(tx_invert,int,0664);
module_param(rx_invert,int,0664);
module_param(hard_ware,int,0664);
#ifdef MT6573
static DMA_CHAN irda_dma=
{
.baseAddr =DMA_BASE_CH(P_DMA_IRDA),
.chan_num =P_DMA_IRDA,
.registered =1,
.type =DMA_HALF_CHANNEL,
.callback=irda_dma_callback;
};
#elif defined(MT6575)
static struct irda_dma_conf irda_dma ;
#endif
static const struct net_device_ops mt_irda_netdev_ops=
{
.ndo_open = mt_irda_net_open,
.ndo_stop = mt_irda_net_close,
int mt65xx_config_gdma(int channel, struct mt65xx_gdma_conf *config, DMA_CONF_FLAG flag)
{
unsigned int dma_con = 0x0, limiter = 0;
if ((channel < GDMA_START) || (channel >= (GDMA_START + NR_GDMA_CHANNEL))) {
return -DMA_ERR_INVALID_CH;
}
if (dma_ctrl[channel].in_use == 0) {
return -DMA_ERR_CH_FREE;
}
if (!config) {
return -DMA_ERR_INV_CONFIG;
}
// if (!(config->sinc) && ((config->src) % 8)) {
// printk("GDMA fixed address mode requires 8-bytes aligned address\n");
if (!config->sinc)
{
printk("GMDA fixed adress mode doesn't support\n");
return -DMA_ERR_INV_CONFIG;
}
// if (!(config->dinc) && ((config->dst) % 8)) {
// printk("GDMA fixed address mode requires 8-bytes aligned address\n");
if (!config->dinc)
{
printk("GMDA fixed adress mode doesn't support\n");
return -DMA_ERR_INV_CONFIG;
}
switch (flag) {
case ALL:
writel(config->src, DMA_SRC(DMA_BASE_CH(channel)));
writel(config->dst, DMA_DST(DMA_BASE_CH(channel)));
writel((config->wplen) & DMA_GDMA_LEN_MAX_MASK, DMA_LEN2(DMA_BASE_CH(channel)));
writel(config->wpto, DMA_JUMP_ADDR(DMA_BASE_CH(channel)));
writel((config->count) & DMA_GDMA_LEN_MAX_MASK, DMA_LEN1(DMA_BASE_CH(channel)));
/*setup coherence bus*/
if (config->cohen){
writel((DMA_READ_COHER_BIT|readl(DMA_AXIATTR(DMA_BASE_CH(channel)))), DMA_AXIATTR(DMA_BASE_CH(channel)));
writel((DMA_WRITE_COHER_BIT|readl(DMA_AXIATTR(DMA_BASE_CH(channel)))), DMA_AXIATTR(DMA_BASE_CH(channel)));
}
/*setup security channel */
if (config->sec){
printk("1:GMDA GSEC:%x, ChSEC:%x\n",readl(DMA_GLOBAL_GSEC_EN),readl(DMA_GDMA_SEC_EN(channel)));
writel((DMA_GSEC_EN_BIT|readl(DMA_GLOBAL_GSEC_EN)), DMA_GLOBAL_GSEC_EN);
writel((DMA_SEC_EN_BIT|readl(DMA_GDMA_SEC_EN(channel))), DMA_GDMA_SEC_EN(channel));
printk("2:GMDA GSEC:%x, ChSEC:%x\n",readl(DMA_GLOBAL_GSEC_EN),readl(DMA_GDMA_SEC_EN(channel)));
}
else
{
printk("1:GMDA GSEC:%x, ChSEC:%x\n",readl(DMA_GLOBAL_GSEC_EN),readl(DMA_GDMA_SEC_EN(channel)));
writel(((~DMA_GSEC_EN_BIT)&readl(DMA_GLOBAL_GSEC_EN)), DMA_GLOBAL_GSEC_EN);
printk("2:GMDA GSEC:%x, ChSEC:%x\n",readl(DMA_GLOBAL_GSEC_EN),readl(DMA_GDMA_SEC_EN(channel)));
}
if (config->wpen) {
dma_con |= DMA_CON_WPEN;
}
if (config->wpsd) {
dma_con |= DMA_CON_WPSD;
}
if (config->iten) {
writel(DMA_INT_EN_BIT, DMA_INT_EN(DMA_BASE_CH(channel)));
}else {
writel(DMA_INT_EN_CLR_BIT, DMA_INT_EN(DMA_BASE_CH(channel)));
}
if (config->dinc && config->sinc) {
dma_con |= (config->burst & DMA_CON_BURST_MASK);
}else {
if (!(config->dinc)) {
dma_con |= DMA_CON_DFIX;
dma_con |= DMA_CON_WSIZE_1BYTE;
}
if (!(config->sinc)) {
dma_con |= DMA_CON_SFIX;
dma_con |= DMA_CON_RSIZE_1BYTE;
}
// fixed src/dst mode only supports burst type SINGLE
dma_con |= DMA_CON_BURST_SINGLE;
}
if (config->limiter) {
limiter = (config->limiter) & DMA_CON_SLOW_MAX_MASK;
dma_con |= limiter << DMA_CON_SLOW_OFFSET;
dma_con |= DMA_CON_SLOW_EN;
}
writel(dma_con, DMA_CON(DMA_BASE_CH(channel)));
break;
case SRC:
writel(config->src, DMA_SRC(DMA_BASE_CH(channel)));
break;
case DST:
writel(config->dst, DMA_DST(DMA_BASE_CH(channel)));
break;
case SRC_AND_DST:
writel(config->src, DMA_SRC(DMA_BASE_CH(channel)));
writel(config->dst, DMA_DST(DMA_BASE_CH(channel)));
break;
default:
break;
}
/* use the data synchronization barrier to ensure that all writes are completed */
dsb();
return 0;
}