/** * @brief Send a frame on the ethernet DMA channel in FIFO mode. * @param DstBuf: pouinter to destination array. * @param BufferSize: size of the transmission. * @param SrcBuf: pointer to source array. * @retval None */ void ETH_DMAFrameTx(uint32_t * DstBuf, uint32_t BufferSize, uint32_t * SrcBuf) { __IO uint32_t * ptrControltable; uint32_t tmpval; MDR_DMA->CHNL_PRIORITY_SET |= 1 << DMA_Channel_SW2; DMA_ControlTable[DMA_Channel_SW2].DMA_SourceEndAddr = (uint32_t)SrcBuf + 4*(BufferSize-1); DMA_ControlTable[DMA_Channel_SW2].DMA_DestEndAddr = (uint32_t)DstBuf; DMA_ControlTable[DMA_Channel_SW2].DMA_Control = DMA_DestIncNo | DMA_SourceIncWord | DMA_MemoryDataSize_Word | DMA_Mode_AutoRequest | DMA_Transfers_1024 | ((BufferSize - 1) << 4); /* Run channel */ DMA_Cmd(DMA_Channel_SW2, ENABLE); DMA_Request(DMA_Channel_SW2); /* Get pointer to DMA control struct */ ptrControltable = (uint32_t *)&DMA_ControlTable[DMA_Channel_SW2].DMA_Control; /* Wait while DMA running */ while( 1 ){ tmpval = (*ptrControltable)&0x3; if(tmpval == 0) break; } /* Disable DMA channel */ DMA_Cmd(DMA_Channel_SW2, DISABLE); }
void main(void) #endif { DMA_ChannelInitTypeDef DMA_InitStr; DMA_CtrlDataInitTypeDef DMA_PriCtrlStr; DMA_CtrlDataInitTypeDef DMA_AltCtrlStr; uint32_t DMA_Channel = 3; RST_CLK_DeInit(); RST_CLK_PCLKcmd(RST_CLK_PCLK_DMA, ENABLE); /* Init RAM */ Init_RAM (DestBuf, SIZE); Init_RAM (PriBuf, SIZE); Init_RAM (AltBuf, SIZE); /* Reset all settings */ DMA_DeInit(); DMA_StructInit(&DMA_InitStr); /* Set Primary Control Data */ DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)PriBuf; DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)DestBuf; DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncWord; DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncWord; DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; DMA_PriCtrlStr.DMA_Mode = DMA_Mode_Basic; DMA_PriCtrlStr.DMA_CycleSize = SIZE; DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_16; DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged; DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged; /* Set Alternate Control Data */ DMA_AltCtrlStr.DMA_SourceBaseAddr = (uint32_t)AltBuf; DMA_AltCtrlStr.DMA_DestBaseAddr = (uint32_t)DestBuf; DMA_AltCtrlStr.DMA_SourceIncSize = DMA_SourceIncWord; DMA_AltCtrlStr.DMA_DestIncSize = DMA_DestIncWord; DMA_AltCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; DMA_AltCtrlStr.DMA_Mode = DMA_Mode_AutoRequest; DMA_AltCtrlStr.DMA_CycleSize = SIZE; DMA_AltCtrlStr.DMA_NumContinuous = DMA_Transfers_16; DMA_AltCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged; DMA_AltCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged; /* Set Channel Structure */ DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr; DMA_InitStr.DMA_AltCtrlData = &DMA_AltCtrlStr; DMA_InitStr.DMA_Priority = DMA_Priority_Default; DMA_InitStr.DMA_UseBurst = DMA_BurstClear; DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY; /* Init DMA channel */ DMA_Init(DMA_Channel, &DMA_InitStr); /* Run channel */ DMA_Cmd(DMA_Channel, ENABLE); DMA_Request(DMA_Channel); /* Transfer complete */ while (DMA_GetFlagStatus(DMA_Channel, DMA_FLAG_CHNL_ENA)) { if((MDR_DMA->STATUS & 0x000000F0)==0x00000000) { DMA_Request(DMA_Channel); } } /* Check the corectness of written data */ TransferStatus1 = Verif_mem(SIZE, PriBuf, DestBuf); /* TransferStatus1 = PASSED, if the data transmitted and received are correct */ /* TransferStatus1 = FAILED, if the data transmitted and received are different */ /* Set Channel Structure */ DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_ALTERNATE; /* Init DMA channel */ DMA_Init(DMA_Channel, &DMA_InitStr); /* Run channel */ DMA_Cmd(DMA_Channel, ENABLE); DMA_Request(DMA_Channel); /* Transfer complete */ while (DMA_GetFlagStatus(DMA_Channel, DMA_FLAG_CHNL_ENA)) { } /* Check the corectness of written data */ TransferStatus2 = Verif_mem(SIZE, AltBuf, DestBuf); /* TransferStatus2 = PASSED, if the data transmitted and received are correct */ /* TransferStatus2 = FAILED, if the data transmitted and received are different */ while (1) { } }