static void exynos_dp_get_adjust_train(struct exynos_dp_device *dp, u8 adjust_request[2]) { int lane; int lane_count; u8 voltage_swing; u8 pre_emphasis; u8 training_lane; lane_count = dp->link_train.lane_count; for (lane = 0; lane < lane_count; lane++) { voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( adjust_request, lane); training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3 || pre_emphasis == PRE_EMPHASIS_LEVEL_3) { training_lane |= DPCD_MAX_SWING_REACHED; training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; } dp->link_train.training_lane[lane] = training_lane; } }
static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, u8 adjust_request[2]) { int lane, lane_count; u8 voltage_swing, pre_emphasis, training_lane; lane_count = dp->link_train.lane_count; for (lane = 0; lane < lane_count; lane++) { voltage_swing = analogix_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( adjust_request, lane); training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) training_lane |= DP_TRAIN_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; dp->link_train.training_lane[lane] = training_lane; } }
static int rk32_edp_process_equalizer_training(struct rk32_edp *edp) { u8 link_status[2]; u8 link_align[3]; int lane; int lane_count; u32 reg; u8 adjust_request[2]; u8 voltage_swing; u8 pre_emphasis; u8 training_lane; int retval; udelay(400); lane_count = edp->link_train.lane_count; retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_LANE0_1_STATUS, 2, link_status); if (retval < 0) { dev_err(edp->dev, "failed to read lane status!\n"); return retval; } if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) { link_align[0] = link_status[0]; link_align[1] = link_status[1]; retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_LANE_ALIGN_STATUS_UPDATED, &link_align[2]); if (retval < 0) { dev_err(edp->dev, "failed to read lane aligne status!\n"); return retval; } for (lane = 0; lane < lane_count; lane++) { retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_ADJUST_REQUEST_LANE0_1, 2, adjust_request); if (retval < 0) { dev_err(edp->dev, "failed to read adjust request!\n"); return retval; } voltage_swing = rk32_edp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis( adjust_request, lane); training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) training_lane |= DPCD_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; edp->link_train.training_lane[lane] = training_lane; } if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) { /* traing pattern Set to Normal */ retval = rk32_edp_training_pattern_dis(edp); if (retval < 0) { dev_err(edp->dev, "failed to disable training pattern!\n"); return retval; } dev_info(edp->dev, "Link Training success!\n"); rk32_edp_get_link_bandwidth(edp, ®); edp->link_train.link_rate = reg; dev_dbg(edp->dev, "final bandwidth = %.2x\n", edp->link_train.link_rate); rk32_edp_get_lane_count(edp, ®); edp->link_train.lane_count = reg; dev_dbg(edp->dev, "final lane count = %.2x\n", edp->link_train.lane_count); edp->link_train.lt_state = FINISHED; } else { /* not all locked */ edp->link_train.eq_loop++; if (edp->link_train.eq_loop > MAX_EQ_LOOP) { dev_err(edp->dev, "EQ Max loop\n"); goto reduce_link_rate; } for (lane = 0; lane < lane_count; lane++) rk32_edp_set_lane_link_training(edp, edp->link_train.training_lane[lane], lane); retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_TRAINING_LANE0_SET, lane_count, edp->link_train.training_lane); if (retval < 0) { dev_err(edp->dev, "failed to set training lane!\n"); return retval; } } } else { goto reduce_link_rate; } return 0; reduce_link_rate: rk32_edp_reduce_link_rate(edp); return -EIO; }
static int rk32_edp_process_clock_recovery(struct rk32_edp *edp) { u8 link_status[2]; int lane; int lane_count; u8 adjust_request[2]; u8 voltage_swing; u8 pre_emphasis; u8 training_lane; int retval; udelay(100); lane_count = edp->link_train.lane_count; retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_LANE0_1_STATUS, 2, link_status); if (retval < 0) { dev_err(edp->dev, "failed to read lane status!\n"); return retval; } if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) { /* set training pattern 2 for EQ */ rk32_edp_set_training_pattern(edp, TRAINING_PTN2); for (lane = 0; lane < lane_count; lane++) { retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_ADJUST_REQUEST_LANE0_1, 2, adjust_request); if (retval < 0) { dev_err(edp->dev, "failed to read adjust request!\n"); return retval; } voltage_swing = rk32_edp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis( adjust_request, lane); training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) training_lane |= DPCD_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; edp->link_train.training_lane[lane] = training_lane; rk32_edp_set_lane_link_training(edp, edp->link_train.training_lane[lane], lane); } retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_TRAINING_PATTERN_SET, DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2); if (retval < 0) { dev_err(edp->dev, "failed to set training pattern 2!\n"); return retval; } retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_TRAINING_LANE0_SET, lane_count, edp->link_train.training_lane); if (retval < 0) { dev_err(edp->dev, "failed to set training lane!\n"); return retval; } dev_info(edp->dev, "Link Training Clock Recovery success\n"); edp->link_train.lt_state = LT_EQ_TRAINING; } else { for (lane = 0; lane < lane_count; lane++) { training_lane = rk32_edp_get_lane_link_training( edp, lane); retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_ADJUST_REQUEST_LANE0_1, 2, adjust_request); if (retval < 0) { dev_err(edp->dev, "failed to read adjust request!\n"); return retval; } voltage_swing = rk32_edp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis( adjust_request, lane); if (voltage_swing == VOLTAGE_LEVEL_3 || pre_emphasis == PRE_EMPHASIS_LEVEL_3) { dev_err(edp->dev, "voltage or pre emphasis reached max level\n"); goto reduce_link_rate; } if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) && (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis)) { edp->link_train.cr_loop[lane]++; if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) { dev_err(edp->dev, "CR Max loop\n"); goto reduce_link_rate; } } training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) training_lane |= DPCD_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; edp->link_train.training_lane[lane] = training_lane; rk32_edp_set_lane_link_training(edp, edp->link_train.training_lane[lane], lane); } retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_TRAINING_LANE0_SET, lane_count, edp->link_train.training_lane); if (retval < 0) { dev_err(edp->dev, "failed to set training lane!\n"); return retval; } } return 0; reduce_link_rate: rk32_edp_reduce_link_rate(edp); return -EIO; }
static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) { u8 link_status[2]; u8 link_align[3]; int lane; int lane_count; u32 reg; u8 adjust_request[2]; u8 voltage_swing; u8 pre_emphasis; u8 training_lane; usleep_range(400, 401); lane_count = dp->link_train.lane_count; exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 2, link_status); if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { link_align[0] = link_status[0]; link_align[1] = link_status[1]; exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED, &link_align[2]); for (lane = 0; lane < lane_count; lane++) { exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( adjust_request, lane); training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) training_lane |= DPCD_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; dp->link_train.training_lane[lane] = training_lane; } if (exynos_dp_channel_eq_ok(link_align, lane_count) == 0) { /* traing pattern Set to Normal */ exynos_dp_training_pattern_dis(dp); dev_info(dp->dev, "Link Training success!\n"); exynos_dp_get_link_bandwidth(dp, ®); dp->link_train.link_rate = reg; dev_dbg(dp->dev, "final bandwidth = %.2x\n", dp->link_train.link_rate); exynos_dp_get_lane_count(dp, ®); dp->link_train.lane_count = reg; dev_dbg(dp->dev, "final lane count = %.2x\n", dp->link_train.lane_count); /* set enhanced mode if available */ exynos_dp_set_enhanced_mode(dp); dp->link_train.lt_state = FINISHED; } else { /* not all locked */ dp->link_train.eq_loop++; if (dp->link_train.eq_loop > MAX_EQ_LOOP) { dev_err(dp->dev, "EQ Max loop\n"); goto reduce_link_rate; } for (lane = 0; lane < lane_count; lane++) exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, lane_count, dp->link_train.training_lane); } } else { goto reduce_link_rate; } return 0; reduce_link_rate: exynos_dp_reduce_link_rate(dp); return -EIO; }
static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) { u8 link_status[2]; int lane; int lane_count; u8 adjust_request[2]; u8 voltage_swing; u8 pre_emphasis; u8 training_lane; usleep_range(100, 101); lane_count = dp->link_train.lane_count; exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 2, link_status); if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { /* set training pattern 2 for EQ */ exynos_dp_set_training_pattern(dp, TRAINING_PTN2); for (lane = 0; lane < lane_count; lane++) { exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( adjust_request, lane); training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) training_lane |= DPCD_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; dp->link_train.training_lane[lane] = training_lane; exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); } exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2); exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, lane_count, dp->link_train.training_lane); dev_info(dp->dev, "Link Training Clock Recovery success\n"); dp->link_train.lt_state = EQUALIZER_TRAINING; } else { for (lane = 0; lane < lane_count; lane++) { training_lane = exynos_dp_get_lane_link_training( dp, lane); exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( adjust_request, lane); if (voltage_swing == VOLTAGE_LEVEL_3 || pre_emphasis == PRE_EMPHASIS_LEVEL_3) { dev_err(dp->dev, "voltage or pre emphasis reached max level\n"); goto reduce_link_rate; } if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) && (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis)) { dp->link_train.cr_loop[lane]++; if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP) { dev_err(dp->dev, "CR Max loop\n"); goto reduce_link_rate; } } training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) training_lane |= DPCD_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; dp->link_train.training_lane[lane] = training_lane; exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); } exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, lane_count, dp->link_train.training_lane); } return 0; reduce_link_rate: exynos_dp_reduce_link_rate(dp); return -EIO; }