void usb_phy_switch_to_usb(void)
{
int var;
/* Set RG_UART_EN to 0 */
var = USB_PHY_Read_Register8(0x6E);
DBG(0, "[MUSB]addr: 0x6E, value: %x\n", var);
USB_PHY_Write_Register8(var & ~0x01, 0x6E);
DBG(0, "[MUSB]addr: 0x6E, value after: %x\n", USB_PHY_Read_Register8(0x6E));
/* Set RG_USB20_DM_100K_EN to 0 */
var = USB_PHY_Read_Register8(0x22);
DBG(0, "[MUSB]addr: 0x22, value: %x\n", var);
USB_PHY_Write_Register8(var & ~0x02, 0x22);
DBG(0, "[MUSB]addr: 0x22, value after: %x\n", USB_PHY_Read_Register8(0x22));
var = DRV_Reg8(UART1_BASE + 0x90);
DBG(0, "[MUSB]addr: 0x11002090 (UART1), value: %x\n", var);
DRV_WriteReg8(UART1_BASE + 0x90, var & ~0x01);
DBG(0, "[MUSB]addr: 0x11002090 (UART1), value after: %x\n\n", DRV_Reg8(UART1_BASE + 0x90));
#if 0
/* SW connect */
var = USB_PHY_Read_Register8(0x68);
DBG(0, "[MUSB]addr: 0x68, value: %x\n", var);
USB_PHY_Write_Register8(0x0, 0x68);
DBG(0, "[MUSB]addr: 0x68, value after: %x\n", USB_PHY_Read_Register8(0x68));
var = USB_PHY_Read_Register8(0x6A);
DBG(0, "[MUSB]addr: 0x6A, value: %x\n", var);
USB_PHY_Write_Register8(0x0, 0x6A);
DBG(0, "[MUSB]addr: 0x6A, value after: %x\n", USB_PHY_Read_Register8(0x6A));
/* SW connect */
#endif
/* SW connect */
mt_usb_connect();
}
void usb_phy_switch_to_uart(void)
{
int var;
#if 0
/* SW disconnect */
var = USB_PHY_Read_Register8(0x68);
DBG(0, "[MUSB]addr: 0x68, value: %x\n", var);
USB_PHY_Write_Register8(0x15, 0x68);
DBG(0, "[MUSB]addr: 0x68, value after: %x\n", USB_PHY_Read_Register8(0x68));
var = USB_PHY_Read_Register8(0x6A);
DBG(0, "[MUSB]addr: 0x6A, value: %x\n", var);
USB_PHY_Write_Register8(0x0, 0x6A);
DBG(0, "[MUSB]addr: 0x6A, value after: %x\n", USB_PHY_Read_Register8(0x6A));
/* SW disconnect */
#endif
/* Set ru_uart_mode to 2'b01 */
var = USB_PHY_Read_Register8(0x6B);
DBG(0, "[MUSB]addr: 0x6B, value: %x\n", var);
USB_PHY_Write_Register8(var | 0x7C, 0x6B);
DBG(0, "[MUSB]addr: 0x6B, value after: %x\n", USB_PHY_Read_Register8(0x6B));
/* Set RG_UART_EN to 1 */
var = USB_PHY_Read_Register8(0x6E);
DBG(0, "[MUSB]addr: 0x6E, value: %x\n", var);
USB_PHY_Write_Register8(var | 0x07, 0x6E);
DBG(0, "[MUSB]addr: 0x6E, value after: %x\n", USB_PHY_Read_Register8(0x6E));
/* Set RG_USB20_DM_100K_EN to 1 */
var = USB_PHY_Read_Register8(0x22);
DBG(0, "[MUSB]addr: 0x22, value: %x\n", var);
USB_PHY_Write_Register8(var | 0x02, 0x22);
DBG(0, "[MUSB]addr: 0x22, value after: %x\n", USB_PHY_Read_Register8(0x22));
var = DRV_Reg8(UART1_BASE + 0x90);
DBG(0, "[MUSB]addr: 0x11002090 (UART1), value: %x\n", var);
DRV_WriteReg8(UART1_BASE + 0x90, var | 0x01);
DBG(0, "[MUSB]addr: 0x11002090 (UART1), value after: %x\n\n", DRV_Reg8(UART1_BASE + 0x90));
/* SW disconnect */
mt_usb_disconnect();
}
kal_uint32 drv_reg_dbg_trace_read8(kal_uint16 line, kal_uint32 addr)
{
kal_uint8 value;
kal_uint32 savedMask;
savedMask = SaveAndSetIRQMask();
value = DRV_Reg8(addr);
drv_reg_dbg_trace(0, line, addr, value);
RestoreIRQMask(savedMask);
return value;
}
void MT6302_Writer_LCD(kal_uint8 data)
{
kal_uint32 i, loopIndex;
if(0 != MT6302_getSPIInterface())
ASSERT(0);
i = SaveAndSetIRQMask();
if(DRVPDN_CON1_LCD & DRV_Reg(DRVPDN_CON1)){
RestoreIRQMask(i);
ASSERT(0);
}
if(0xc != REG_LCD_SERIAL_CONFIG){
RestoreIRQMask(i);
ASSERT(0);
}
if(KAL_FALSE == MT6302_checkSPIMode()){
RestoreIRQMask(i);
ASSERT(0);
}
/* becareful that SW will hang on here until LCD controller return RDY signal on bus
* accoring to the measurement, in the slowest timing setting, LCD takes 2us to send on byte
*/
//DRV_Reg8(MT6302_SPI_LCDSerialData) = data;
DRV_WriteReg8((MT6302_SPI_LCDSerialData), data);
/*dummy read to make sure former byte has been written on SPI*/
MT6302_LCD_dummyReadValue = DRV_Reg8(MT6302_SPI_LCDSerialData);
RestoreIRQMask(i);
// 285 OK
// 250 FAIL
if( 0x60 == (0xE0 & data))
//noke_drv_mt6302_delay_us(300);
noke_drv_mt6302_delay_us(450);
}
void drv_idc_get_pm_config(kal_bool start, kal_uint8 *priority, kal_uint8 *priority_bit_en, kal_uint8 *pattern, kal_uint8 *pattern_bit_en)
{
switch(start)
{
case KAL_FALSE:
*priority = DRV_Reg8(IDC_UART_FINISH_PRI);
*priority_bit_en = DRV_Reg8(IDC_UART_FINISH_PRI_BITEN);
*pattern = DRV_Reg8(IDC_UART_FINISH_PAT);
*pattern_bit_en = DRV_Reg8(IDC_UART_FINISH_PAT_BITEN);
break;
case KAL_TRUE:
*priority = DRV_Reg8(IDC_UART_START_PRI);
*priority_bit_en = DRV_Reg8(IDC_UART_START_PRI_BITEN);
*pattern = DRV_Reg8(IDC_UART_START_PAT);
*pattern_bit_en = DRV_Reg8(IDC_UART_START_PAT_BITEN);
break;
default:
ASSERT(0);
break;
}
return;
}
void idc_send_rx_data_by_ilm(void)
{
while(DRV_Reg(IDC_UART_LSR) & IDC_UART_LSR_DR)
{
// read bytes from IDC UART FIFO to SW buffer
idc_port.rx_buf = (idc_port.rx_buf << 16) | (1 << 8) | DRV_Reg8(IDC_UART_RBR);
idc_read_RBR = KAL_TRUE;
idc_rx_history[idc_rx_count] = (kal_uint8)(idc_port.rx_buf & 0xFF);
idc_rx_history_time[idc_rx_count] = DRV_Reg32(FRC_VAL_R);
idc_rx_count++;
if (idc_rx_count == 20)
{
idc_rx_count = 0;
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_INFO, 0, IDC_RX_HISTORY_MSG,
idc_rx_history[0], idc_rx_history[1], idc_rx_history[2], idc_rx_history[3], idc_rx_history[4],
idc_rx_history[5], idc_rx_history[6], idc_rx_history[7], idc_rx_history[8], idc_rx_history[9],
idc_rx_history[10], idc_rx_history[11], idc_rx_history[12], idc_rx_history[13], idc_rx_history[14],
idc_rx_history[15], idc_rx_history[16], idc_rx_history[17], idc_rx_history[18], idc_rx_history[19]
);
#else
kal_sprintf(idc_dbg_str, "drv_idc: Receive %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n\r",
idc_rx_history[0], idc_rx_history[1], idc_rx_history[2], idc_rx_history[3], idc_rx_history[4],
idc_rx_history[5], idc_rx_history[6], idc_rx_history[7], idc_rx_history[8], idc_rx_history[9],
idc_rx_history[10], idc_rx_history[11], idc_rx_history[12], idc_rx_history[13], idc_rx_history[14],
idc_rx_history[15], idc_rx_history[16], idc_rx_history[17], idc_rx_history[18], idc_rx_history[19]
);
DT_IDC_PRINTF(idc_dbg_str);
#endif
}
// if there are two-byte data in fifo and data is valid, send them by ilm
if((idc_port.rx_buf & 0x01010101) == 0x01000101)
{
IDC_ILM_MSG_T tmp;
tmp.type = (idc_port.rx_buf & 0x001E0000) >> 17;
tmp.msg = ((idc_port.rx_buf & 0x00E00000) >> 21) | ((idc_port.rx_buf & 0x000000FE) << 2);
//DT_IDC_PRINTF("%x %x\n\r", tmp.type, tmp.msg);
if (tmp.type == 0)
{
if (KAL_TRUE == idc_count_start)
{
idc_80211_rx_count++;
dhl_trace(TRACE_INFO, 0, IDC_RX_80211_RX_MSG, tmp.type, tmp.msg);
}
}
else if (tmp.type == 1)
{
if (KAL_TRUE == idc_count_start)
{
idc_80211_tx_count++;
dhl_trace(TRACE_INFO, 0, IDC_RX_80211_TX_MSG, tmp.type, tmp.msg);
}
}
else
{
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_INFO, 0, IDC_RX_SEND_ILM_MSG, idc_port.rx_buf, tmp.type, tmp.msg);
#else
kal_sprintf(idc_dbg_str, "drv_idc: MSG Send to EL1: %x, type:%x, msg:%x\n\r", idc_port.rx_buf, tmp.type, tmp.msg);
DT_IDC_PRINTF(idc_dbg_str);
#endif
msg_send_inline6(MOD_DRV_HISR, idc_port.owner_id, DRIVER_PS_SAP | INLINE_ILM_FLAG_SAP, MSG_ID_IDC_RX_DATA, (void *) &tmp, sizeof(IDC_ILM_MSG_T));
}
idc_port.rx_buf = 0;
}
}
void drv_idc_set_dcb_config(IDC_CTRL_DCB_CONFIG_T idc_config)
{
kal_uint8 tmp_lcr, tmp_ier;
IRQMask(MD_IRQID_IDC2ARM);
tmp_ier = DRV_Reg8(IDC_UART_IER);
DRV_WriteReg8(IDC_UART_IER, IDC_UART_IER_ALLOFF);
IRQUnmask(MD_IRQID_IDC2ARM);
// set baud rate
drv_idc_set_baudrate(idc_config.u4Baud);
tmp_lcr = DRV_Reg32(IDC_UART_LCR);
tmp_lcr &= ~0x3F;
// set number of bits per character
switch(idc_config.u1DataBits)
{
case len_5:
tmp_lcr |= IDC_UART_WLS_5;
break;
case len_6:
tmp_lcr |= IDC_UART_WLS_6;
break;
case len_7:
tmp_lcr |= IDC_UART_WLS_7;
break;
case len_8:
tmp_lcr |= IDC_UART_WLS_8;
break;
default:
break;
}
switch(idc_config.u1StopBits)
{
case sb_1:
tmp_lcr |= IDC_UART_1_STOP;
break;
case sb_2:
tmp_lcr |= IDC_UART_2_STOP;
break;
case sb_1_5:
tmp_lcr |= IDC_UART_1_5_STOP;
break;
default:
break;
}
switch(idc_config.u1Parity)
{
case pa_none:
tmp_lcr |= IDC_UART_NONE_PARITY;
break;
case pa_odd:
tmp_lcr |= IDC_UART_ODD_PARITY;
break;
case pa_even:
tmp_lcr |= IDC_UART_EVEN_PARITY;
break;
default:
break;
}
DRV_WriteReg32(IDC_UART_LCR, tmp_lcr);
kal_mem_cpy((void *) &idc_port.DCB, (void *) &idc_config, sizeof(IDC_CTRL_DCB_CONFIG_T));
IRQMask(MD_IRQID_IDC2ARM);
DRV_WriteReg8(IDC_UART_IER, tmp_ier);
IRQUnmask(MD_IRQID_IDC2ARM);
}
