void mt_pmic_low_power_init(void)
{
unsigned int volt = 0;
/********************
* PMIC VPROC setting
*********************/
upmu_buck_vosel_srclken_0(BUCK_VPROC, 0x08); // VPROC 0.9V in sleep mode
if (get_chip_ver() >= CHIP_6577_E1)
{
volt = mt_pmic_cpu_max_volt();
if ((DRV_Reg32(HW_RESV) & (0x1 << 23)) && ((DRV_Reg32(HW_RESV) & (0x1 << 20)) == 0))
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, volt);
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x17); // 1.275V DVS_VOL_10
}
else
{
if (DRV_Reg32(HW_RESV) & (0x1 << 12))
{
if ((DRV_Reg32(HW_RESV) & (0x1 << 17)) && ((DRV_Reg32(HW_RESV) & (0x1 << 16)) == 0))
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, volt);
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x17); // 1.275V DVS_VOL_10
}
else
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x08); // 0.900V DVS_VOL_01
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10
upmu_buck_vosel_dvs_11(BUCK_VPROC, volt);
}
}
else
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x08); // 0.900V DVS_VOL_01
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10
upmu_buck_vosel_dvs_11(BUCK_VPROC, volt);
}
}
}
else if (get_chip_ver() >= CHIP_6575_E2)
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x0B);
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F);
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13);
if ((DRV_Reg32(HW_RESV) & (0x1 << 29)))
{
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x17);
}
else
{
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x16);
}
}
else if (get_chip_ver() >= CHIP_6575_E1)
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x13);
if ((DRV_Reg32(HW_RESV) & (0x1 << 29)))
{
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x17);
}
else
{
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x16);
}
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13);
if ((DRV_Reg32(HW_RESV) & (0x1 << 29)))
{
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x17);
}
else
{
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x16);
}
}
else
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x16);
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x16);
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x16);
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x16);
}
DRV_WriteReg32(SC_AP_DVFS_CON, ((DRV_Reg32(SC_AP_DVFS_CON) & 0xFFFFFFFC) | 0x03)); // set cpu to top voltage
upmu_buck_ctrl(BUCK_VPROC, 0x3); // VPROC controlled by SRCLKEN and AP_DVFS_CON1/0
/********************
* PMIC VCORE setting
*********************/
if ((DRV_Reg32(HW_RESV) & (0x1 << 19)))
{
upmu_buck_vosel(BUCK_VCORE, UPMU_VOLT_0_8_0_0_V); // VCORE 0.8V in sleep mode
}
else
{
upmu_buck_vosel(BUCK_VCORE, UPMU_VOLT_0_9_0_0_V); // VCORE 0.9V in sleep mode
}
/********************
* PMIC Other setting
*********************/
pmic_config_interface(0x8B, 0x08, 0x1F, 0x0); // VM12_INT 0.9V in sleep mode
pmic_config_interface(0x8C, 0x10, 0x1F, 0x0); // VM12_INT_LOW_BOUND
pmic_config_interface(0x8F, 0x01, 0x01, 0x4); // VM12_INT Tracking VPROC
pmic_config_interface(0x90, 0x01, 0x01, 0x0); // VM12_INT_LP_SEL HW control
pmic_config_interface(0x85, 0x01, 0x01, 0x0); // VM12_1_LP_SEL HW control
pmic_config_interface(0x89, 0x01, 0x01, 0x0); // VM12_2_LP_SEL HW control
pmic_config_interface(0xA9, 0x01, 0x01, 0x0); // VMC_LP_SEL HW control
pmic_config_interface(0xAD, 0x01, 0x01, 0x0); // VMCH_LP_SEL HW control
pmic_config_interface(0xC6, 0x01, 0x01, 0x0); // VA1_LP_SEL HW control
pmic_config_interface(0xC1, 0x01, 0x01, 0x1); // VTCXO_ON_CTRL HW control
pmic_config_interface(0x4F, 0x01, 0x01, 0x6); // BUCK clock keep 2MHz select
pmic_config_interface(0x4F, 0x01, 0x01, 0x7); // OSC10M and 2M auto select function enable
}
/**
* To initialize TV out module
*
* @param None.
*
* @return None.
*/
void init_tv(void)
{
tv_power_on();
tv_output_owner=TV_OUT_OWNER_MMI;
tv_output_config_data.tv_output_mode=0;/*TV_FORMAT_NTSCTV_OUTPUT_DISABLE*/
tv_output_config_data.tv_output_format=0;/*TV_FORMAT_NTSC*/
tv_output_config_data.tv_output_offset_x=0;
tv_output_config_data.tv_output_offset_y=0;
/* configure TV encoder mode */
/*?????=> don't change*/
DISABLE_TV_UV_SWAP;
DISABLE_TV_BLACKER_MODE;
DISABLE_TV_HORIZONTAL_SLEW;
SET_TV_SYDELAY_BIT;
SET_TV_Y_DELAY(2);
DISABLE_TV_CHROMA_UP_SAMPLE;
DISABLE_TV_LUMA_LPF;
ENABLE_TV_CHROMA_LPF;
SET_TV_CHROMA_LPF0;
SET_TV_ENC_SCALE_BLANK(4);
/* configure TV controller contorl register */
/*?????*/
SET_TV_CON_WRITE_SINGLE_BUFFER;
DISABLE_TV_CON_BURST_MODE;
#if defined(DRV_TVOUT_6228_SERIES)
ENABLE_TV_CON_DEEPER_BUFFER;
#elif defined(DRV_TVOUT_6238_SERIES)
//KKKKK, need to confirm with designer
ENABLE_TV_CON_HIGHER_BUS_PRIORITY;
ENABLE_TV_CTRL_HANDSHAKE_WTITH_VIDEC;
DISABLE_TV_CTRL_PREFETCH;
SET_TV_CON_READ_ACTIVE_BUFFER;
ENABLE_TV_CTRL_AVG_MODE;
ENABLE_TV_CTRL_CLIP_MODE;
DISABLE_TV_CTRL_CHKLINE_INT_MODE;
DISABLE_TV_CTRL_OVR_INT_MODE;
/*TVC slow control, may need to fine tune*/
DRV_WriteReg32(TV_CON_SLOW_CTRL_REG,(4<<24)|(4<<20)|(2<<16)|(400));
#endif
ENABLE_TV_CON_FILL_BLACK_PIXEL;
if (custom_ifLPSDRAM()==KAL_TRUE)
{
ENABLE_TV_CON_VERTICAL_INTERPOLATION;
}
else
{
DISABLE_TV_CON_VERTICAL_INTERPOLATION;
}
SET_TV_CON_READ_WRITE_BUFFER;
/*可讓邊緣不sharp*/
#if defined(DRV_TVOUT_6228_SERIES)
ENABLE_TV_CON_MAGIC_SWITCH;
#elif defined(DRV_TVOUT_6238_SERIES)
//KKKKK, need to confirm with DE
//this resiger doesn't exist anymore
#endif
/*enable handshake between tv out and mpeg4*/
ENABLE_TV_CTRL_HANDSHAKE_WTITH_VIDEC;
ENABLE_TV_DAC_MAGIC_SWITCH;
/*sleep mode*/
if (tv_sleep_mode_handler==0xFF)
tv_sleep_mode_handler=L1SM_GetHandle();
L1SM_SleepDisable(tv_sleep_mode_handler);
} /* init_tv() */
static void mt_mempll_init(void)
{
#if defined(__FPGA__)
// Set Clock, temporary solution for FPGA Version: 20120814
// Bit[3:0] 0: 1x RAMC clock
// 1: 2x RAMC clock
// Bit[11:8] 0x0: 17.25MHz
// 0x1: 18.75MHz
// 0x2: 20MHz
// 0x3: 24MHz
// 0x4: 25MHz
// 0x5: 30MHz
// 0x6: 37.5MHz
// 0x7: 40MHz
// 0x8: 34.5MHz
// 0x9: 37.5Mhz
// 0xA: 40MHz
// 0xB: 48MHz
// 0xC: 50MHz
// 0xD: 60MHz
// 0xE: 75MHz
// 0xF: 80MHz
DRV_WriteReg32(REG_MDCLKCTL_FPGA_EMICTL, 0x00000701);
#else // if !defined(__FPGA__)
unsigned int reg_val;
unsigned int pll234_fb_type;
unsigned int pll234_c0_fbksel;
unsigned int pll234_c1_fb_mck_sel;
unsigned int bypass_mempll1;
unsigned int ddrphy_multi_pll_mode;
unsigned int seal_ring_mode;
unsigned int emidds_sdm_pcw_400;
unsigned int pll234_c0_fbdiv_400;
unsigned int pll234_c1_m4pdiv_400;
unsigned int emidds_sdm_pcw_333_5;
unsigned int pll234_c0_fbdiv_333_5;
unsigned int pll234_c1_m4pdiv_333_5;
unsigned int emidds_sdm_pcw_266_5;
unsigned int pll234_c0_fbdiv_266_5;
unsigned int pll234_c1_m4pdiv_266_5;
unsigned int emidds_sdm_pcw_200;
unsigned int pll234_c0_fbdiv_200;
unsigned int pll234_c1_m4pdiv_200;
unsigned int emidds_sdm_pcw;
unsigned int pll2_c0_fbdiv;
unsigned int pll2_c1_m4pdiv;
unsigned int pll3_c0_fbdiv;
unsigned int pll3_c1_m4pdiv;
unsigned int pop_pll3_c0_fbdiv;
unsigned int pop_pll3_c1_m4pdiv;
unsigned int pll4_c0_fbdiv;
unsigned int pll4_c1_m4pdiv;
/*************************************************************
* (0) check mempll is enabled and initialize local variable.
*************************************************************/
// check MEMPLL_RDY_GATING is set to HW control mode.
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL) & MEMPLL_CTL_MEMPLL_RDY_GATING;
if (0 == reg_val) {
return;
}
if (TRUE == is_mt6290m) {
bypass_mempll1 = TRUE;
// NOTE!! With MT6290M, we must use multi-pll mode, because of HW limitation.
ddrphy_multi_pll_mode = TRUE;
seal_ring_mode = FALSE;
} else {
bypass_mempll1 = TRUE;
ddrphy_multi_pll_mode = TRUE;
seal_ring_mode = FALSE;
}
if (TRUE == ddrphy_multi_pll_mode) {
// External Loop
pll234_fb_type = 1;
} else {
// Internal Loop
pll234_fb_type = 0;
}
if (1 == pll234_fb_type) {
emidds_sdm_pcw_400 = 0xf6276 << 0; // 25 MHz
pll234_c0_fbdiv_400 = 0x08 << 16;
pll234_c1_m4pdiv_400 = 0x0 << 28;
emidds_sdm_pcw_333_5 = 0x111a41 << 0; // 27.79167MHz
pll234_c0_fbdiv_333_5 = 0x06 << 16;
pll234_c1_m4pdiv_333_5 = 0x0 << 28;
emidds_sdm_pcw_266_5 = 0x106666 << 0; // 26.65MHz
pll234_c0_fbdiv_266_5 = 0x05 << 16;
pll234_c1_m4pdiv_266_5 = 0x1 << 28;
emidds_sdm_pcw_200 = 0xf6276 << 0; // 25MHz
pll234_c0_fbdiv_200 = 0x04 << 16;
pll234_c1_m4pdiv_200 = 0x1 << 28;
} else {
emidds_sdm_pcw_400 = 0xf6276 << 0; // 25 MHz
pll234_c0_fbdiv_400 = 0x10 << 16;
pll234_c1_m4pdiv_400 = 0x0 << 28;
emidds_sdm_pcw_333_5 = 0xfc975 << 0; // 25.6538MHz
pll234_c0_fbdiv_333_5 = 0x0d << 16;
pll234_c1_m4pdiv_333_5 = 0x0 << 28;
emidds_sdm_pcw_266_5 = 0xee8ba << 0; // 24.2272MHz
pll234_c0_fbdiv_266_5 = 0x16 << 16;
pll234_c1_m4pdiv_266_5 = 0x1 << 28;
emidds_sdm_pcw_200 = 0xf6276 << 0; // 25MHz
pll234_c0_fbdiv_200 = 0x10 << 16;
pll234_c1_m4pdiv_200 = 0x1 << 28;
}
// Warning for set-but-not-used.
if (emidds_sdm_pcw_400) {}
if (pll234_c0_fbdiv_400) {}
if (pll234_c1_m4pdiv_400) {}
if (emidds_sdm_pcw_333_5) {}
if (pll234_c0_fbdiv_333_5) {}
if (pll234_c1_m4pdiv_333_5) {}
if (emidds_sdm_pcw_266_5) {}
if (pll234_c0_fbdiv_266_5) {}
if (pll234_c1_m4pdiv_266_5) {}
if (emidds_sdm_pcw_200) {}
if (pll234_c0_fbdiv_200) {}
if (pll234_c1_m4pdiv_200) {}
/****************************************
* (1) Setup Common Setting
****************************************/
reg_val = PLL_C0_PREDIV | PLL_C0_POSDIV | PLL_C0_SDM_DI_EN;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_CTL0, reg_val);
reg_val = POP_PLL_C0_PREDIV | POP_PLL_C0_POSDIV | POP_PLL_C0_SDM_DI_EN;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL_CTL0, reg_val);
reg_val = PLL_C1_RESERVE1;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_CTL1, reg_val);
reg_val = POP_PLL_C1_RESERVE1;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL_CTL1, reg_val);
reg_val = PLL_C2_RESERVE | PLL_C2_DIV;
if (FALSE == bypass_mempll1) {
reg_val |= 0x04 << 24;
}
if (TRUE == seal_ring_mode) {
reg_val |= 0x10 << 24;
}
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_CTL2, reg_val);
reg_val = POP_PLL_C2_RESERVE | POP_PLL_C2_DIV;
if (FALSE == bypass_mempll1) {
reg_val |= 0x04 << 24;
}
if (TRUE == seal_ring_mode) {
reg_val |= 0x10 << 24;
}
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL_CTL2, reg_val);
reg_val = PLL_PCW_N_INFO;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_PCW, reg_val);
reg_val = POP_PLL_PCW_N_INFO;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL_PCW, reg_val);
reg_val = EMIDDS_SDM_FRA_EN | EMIDDS_POSDIV;
DRV_WriteReg32(REG_MDCLKCTL_EMIDDS_CTL, reg_val);
if (1 == pll234_fb_type) {
// External Loop
pll234_c0_fbksel = (0x0 << 24);
} else {
// Internal Loop
pll234_c0_fbksel = (0x1 << 24);
}
reg_val = PLL2_C0_PREDIV | PLL2_C0_POSDIV | PLL2_C0_VCO_DIV_SEL;
reg_val |= pll234_c0_fbksel;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL0, reg_val);
reg_val = PLL3_C0_PREDIV | PLL3_C0_POSDIV | PLL3_C0_VCO_DIV_SEL;
reg_val |= pll234_c0_fbksel;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL0, reg_val);
reg_val = POP_PLL3_C0_PREDIV | POP_PLL3_C0_POSDIV | POP_PLL3_C0_VCO_DIV_SEL;
reg_val |= pll234_c0_fbksel;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL0, reg_val);
reg_val = PLL4_C0_PREDIV | PLL4_C0_POSDIV | PLL4_C0_VCO_DIV_SEL;
reg_val |= pll234_c0_fbksel;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL0, reg_val);
if (1 == pll234_fb_type) {
// External Loop
pll234_c1_fb_mck_sel = (0x1 << 25);
} else {
// Internal Loop
pll234_c1_fb_mck_sel = (0x0 << 25);
}
reg_val = PLL2_C1_RESERVE | PLL2_C1_REF_DL | PLL2_C1_FB_DL;
reg_val |= pll234_c1_fb_mck_sel;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL1, reg_val);
reg_val = PLL3_C1_RESERVE | PLL3_C1_REF_DL | PLL3_C1_FB_DL;
reg_val |= pll234_c1_fb_mck_sel;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL1, reg_val);
reg_val = POP_PLL3_C1_RESERVE | POP_PLL3_C1_REF_DL | POP_PLL3_C1_FB_DL;
reg_val |= pll234_c1_fb_mck_sel;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1, reg_val);
reg_val = PLL4_C1_RESERVE | PLL4_C1_REF_DL | PLL4_C1_FB_DL;
reg_val |= pll234_c1_fb_mck_sel;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL1, reg_val);
DRV_WriteReg32(DRAMC_ACTIM0, EMI_INFO[0].dramc_actim0_val);
DRV_WriteReg32(DRAMC_DDR2CTL, EMI_INFO[0].dramc_ddr2ctl_val);
/*******************************************************************************************
* (2) Setup MEMPLL operation case & frequency, May set according to dram type & frequency
*******************************************************************************************/
if (TRUE == is_mt6290m) {
#if 1
emidds_sdm_pcw = emidds_sdm_pcw_400;
pll2_c0_fbdiv = pll234_c0_fbdiv_400;
pll2_c1_m4pdiv = pll234_c1_m4pdiv_400;
pll3_c0_fbdiv = pll234_c0_fbdiv_400;
pll3_c1_m4pdiv = pll234_c1_m4pdiv_400;
pop_pll3_c0_fbdiv = pll234_c0_fbdiv_400;
pop_pll3_c1_m4pdiv = pll234_c1_m4pdiv_400;
pll4_c0_fbdiv = pll234_c0_fbdiv_400;
pll4_c1_m4pdiv = pll234_c1_m4pdiv_400;
#endif
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
} else {
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
#if 1
emidds_sdm_pcw = emidds_sdm_pcw_333_5;
pll2_c0_fbdiv = pll234_c0_fbdiv_333_5;
pll2_c1_m4pdiv = pll234_c1_m4pdiv_333_5;
pll3_c0_fbdiv = pll234_c0_fbdiv_333_5;
pll3_c1_m4pdiv = pll234_c1_m4pdiv_333_5;
pop_pll3_c0_fbdiv = pll234_c0_fbdiv_333_5;
pop_pll3_c1_m4pdiv = pll234_c1_m4pdiv_333_5;
pll4_c0_fbdiv = pll234_c0_fbdiv_333_5;
pll4_c1_m4pdiv = pll234_c1_m4pdiv_333_5;
#endif
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
}
reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_CTL) | emidds_sdm_pcw;
DRV_WriteReg32(REG_MDCLKCTL_EMIDDS_CTL, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL2_CTL0) | pll2_c0_fbdiv;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL0, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL3_CTL0) | pll3_c0_fbdiv;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL0, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL3_CTL0) | pop_pll3_c0_fbdiv;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL0, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL4_CTL0) | pll4_c0_fbdiv;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL0, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL2_CTL1) | pll2_c1_m4pdiv;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL1, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL3_CTL1) | pll3_c1_m4pdiv;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL1, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1) | pop_pll3_c1_m4pdiv;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL4_CTL1) | pll4_c1_m4pdiv;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL1, reg_val);
/*************************************
* (3) Setup MEMPLL power on sequence
*************************************/
reg_val = DRV_Reg32(DRAMC_MEMPLL_DIVIDER) | DRAMC_MEMPLL_DIVIDER_DMBYP_PLL4;
if (1 == pll234_fb_type) {
reg_val |= DRAMC_MEMPLL_DIVIDER_DMPLL2CLK_EN;
}
if (TRUE == ddrphy_multi_pll_mode) {
reg_val &= ~DRAMC_MEMPLL_DIVIDER_DMBYP_PLL3_DDRPHY;
} else {
reg_val |= DRAMC_MEMPLL_DIVIDER_DMBYP_PLL3_DDRPHY;
}
DRV_WriteReg32(DRAMC_MEMPLL_DIVIDER, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL) & (~(MEMPLL_CTL_MEMPLL_SW_MEMPLL_ISO_EN));
if (TRUE == is_mt6290m) {
reg_val &= ~(MEMPLL_CTL_MEMPLL_SW_POP_MEMPLL_ISO_EN);
}
reg_val |= MEMPLL_CTL_MEMPLL_RDY_GATING;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_CTL, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_FH_CTL1) | EMIDDS_FH_CTL1_EMIDDS_FSM_EN;
DRV_WriteReg32(REG_MDCLKCTL_EMIDDS_FH_CTL1, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_CTL) | EMIDDS_SDM_PCW_CHG;
DRV_WriteReg32_NPW(REG_MDCLKCTL_EMIDDS_CTL, reg_val);
// Delay 20 us
BL_GPT_UDELAY(20);
if (FALSE == bypass_mempll1) {
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_PCW) | PCW_N_INFO_CHG;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_PCW, reg_val);
if (TRUE == is_mt6290m) {
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL_PCW) | POP_PCW_N_INFO_CHG;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL_PCW, reg_val);
}
reg_val = DRV_Reg32(REG_MDCLKCTL_PLL_ON_CTL1) | PLL_ON_CTL1_SW_EMIDDS_PWR_ON;
DRV_WriteReg32_NPW(REG_MDCLKCTL_PLL_ON_CTL1, reg_val);
// Delay 30 ns
BL_GPT_UDELAY(1);
}
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL1) | PLL_C1_BIAS_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_MEMPLL_CTL1, reg_val);
if (TRUE == is_mt6290m) {
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL_CTL1) | POP_PLL_C1_BIAS_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_POP_MEMPLL_CTL1, reg_val);
}
// Delay 2 us
BL_GPT_UDELAY(2);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL1) | PLL_C1_BIAS_LPF_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_MEMPLL_CTL1, reg_val);
if (TRUE == is_mt6290m) {
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL_CTL1) | POP_PLL_C1_BIAS_LPF_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_POP_MEMPLL_CTL1, reg_val);
}
// Delay 1 ms
BL_GPT_UDELAY(1000);
if ((FALSE == bypass_mempll1) || (TRUE == seal_ring_mode)) {
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL0) | PLL_C0_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_MEMPLL_CTL0, reg_val);
if (TRUE == is_mt6290m) {
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL_CTL0) | POP_PLL_C0_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_POP_MEMPLL_CTL0, reg_val);
}
// Delay 20 us
BL_GPT_UDELAY(20);
}
if (FALSE == bypass_mempll1) {
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL2) | PLL_C2_DIV_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_MEMPLL_CTL2, reg_val);
if (TRUE == is_mt6290m) {
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL_CTL2) | POP_PLL_C2_DIV_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_POP_MEMPLL_CTL2, reg_val);
}
// Delay 1 us
BL_GPT_UDELAY(1);
}
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL2_CTL0) | PLL2_C0_EN;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL0, reg_val);
if (TRUE == ddrphy_multi_pll_mode) {
if (TRUE == is_mt6290m) {
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL3_CTL0) | POP_PLL3_C0_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_POP_MEMPLL3_CTL0, reg_val);
} else {
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL3_CTL0) | PLL3_C0_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_MEMPLL3_CTL0, reg_val);
}
}
// Delay 20 us
BL_GPT_UDELAY(20);
reg_val = DRV_Reg32(DRAMC_MEMPLL_DIVIDER) | DRAMC_MEMPLL_DIVIDER_DMPLL2CLK_EN | DRAMC_MEMPLL_DIVIDER_DMALLCLK_EN;
DRV_WriteReg32_NPW(DRAMC_MEMPLL_DIVIDER, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL) & (~MEMPLL_CTL_MEMPLL_RDY_GATING);
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_CTL, reg_val);
// Simulation is about 1.1 us
BL_GPT_UDELAY(3);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL) | MEMPLL_CTL_MEMPLL_MEMPLL_HW_CTL_MODE;
if (TRUE == is_mt6290m) {
reg_val |= MEMPLL_CTL_MEMPLL_POP_MEMPLL_HW_CTL_MODE;
}
DRV_WriteReg32_NPW(REG_MDCLKCTL_MEMPLL_CTL, reg_val);
#endif // end if defined(__FPGA__)
Data_Mem_Barrier();
}
static int mt_mempll_cali(void)
{
#if defined(__FPGA__)
return 0;
#else // if !defined(__FPGA__)
int one_count = 0, zero_count = 0;
int pll2_done = 0, pll3_done = 0, pll4_done = 0, pop_pll3_done = 0, ret = 0;
unsigned int temp = 0, pll2_dl = 0, pll3_dl = 0, pll4_dl = 0, pop_pll3_dl = 0;
int pll2_phase=0, pll3_phase=0, pll4_phase=0, pop_pll3_phase=0;
// [-Werror=unused-but-set-variable]
if (one_count){}
if (zero_count){}
/***********************************************************
* 1. Bypass some pll calibration because pll is turned off.
***********************************************************/
if (0 == (DRV_Reg32(REG_MDCLKCTL_MEMPLL2_CTL0)&PLL2_C0_EN)) {
pll2_done = 1;
}
if (0 == (DRV_Reg32(REG_MDCLKCTL_MEMPLL3_CTL0)&PLL3_C0_EN)) {
pll3_done = 1;
}
if (0 == (DRV_Reg32(REG_MDCLKCTL_MEMPLL4_CTL0)&PLL4_C0_EN)) {
pll4_done = 1;
}
if (0 == (DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL3_CTL0)&POP_PLL3_C0_EN)) {
pop_pll3_done = 1;
}
/***********************************************
* 2. Set jitter meter count number
************************************************/
// Set jitter meter count to 1024
temp = (DRV_Reg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL) & MEMPLL_JMETER_CTL_CNT_MASK) | MEMPLL_JMETER_CTL_CNT(MEMPLL_JMETER_CNT);
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL, temp);
while(1)
{
/***********************************************
* 3. Adjust delay chain tap number
************************************************/
if (!pll2_done)
{
if (pll2_phase == 0) // initial phase set to 0 for REF and FBK
{
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL2_CTL1) & ~MEMPLL2_CTL1_REF_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL1, (temp | MEMPLL2_CTL1_REF_DL(0x0)));
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL2_CTL1) & ~MEMPLL2_CTL1_FB_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL1, (temp | MEMPLL2_CTL1_FB_DL(0x0)));
}
else if (pll2_phase == 1) // REF lead FBK, delay FBK
{
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL2_CTL1) & ~MEMPLL2_CTL1_REF_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL1, (temp | MEMPLL2_CTL1_REF_DL(0x0)));
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL2_CTL1) & ~MEMPLL2_CTL1_FB_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL1, (temp | MEMPLL2_CTL1_FB_DL(pll2_dl)));
}
else // REF lag FBK, delay REF
{
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL2_CTL1) & ~MEMPLL2_CTL1_REF_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL1, (temp | MEMPLL2_CTL1_REF_DL(pll2_dl)));
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL2_CTL1) & ~MEMPLL2_CTL1_FB_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL1, (temp | MEMPLL2_CTL1_FB_DL(0x0)));
}
}
if (!pll3_done)
{
if (pll3_phase == 0) // initial phase set to 0 for REF and FBK
{
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL3_CTL1) & ~MEMPLL3_CTL1_REF_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL1, (temp | MEMPLL3_CTL1_REF_DL(0x0)));
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL3_CTL1) & ~MEMPLL3_CTL1_FB_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL1, (temp | MEMPLL3_CTL1_FB_DL(0x0)));
}
else if (pll3_phase == 1) // REF lead FBK, delay FBK
{
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL3_CTL1) & ~MEMPLL3_CTL1_REF_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL1, (temp | MEMPLL3_CTL1_REF_DL(0x0)));
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL3_CTL1) & ~MEMPLL3_CTL1_FB_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL1, (temp | MEMPLL3_CTL1_FB_DL(pll3_dl)));
}
else // REF lag FBK, delay REF
{
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL3_CTL1) & ~MEMPLL3_CTL1_REF_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL1, (temp | MEMPLL3_CTL1_REF_DL(pll3_dl)));
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL3_CTL1) & ~MEMPLL3_CTL1_FB_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL1, (temp | MEMPLL3_CTL1_FB_DL(0x0)));
}
}
if (!pll4_done)
{
if (pll4_phase == 0) // initial phase set to 0 for REF and FBK
{
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL4_CTL1) & ~MEMPLL4_CTL1_REF_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL1, (temp | MEMPLL4_CTL1_REF_DL(0x0)));
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL4_CTL1) & ~MEMPLL4_CTL1_FB_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL1, (temp | MEMPLL4_CTL1_FB_DL(0x0)));
}
else if (pll4_phase == 1) // REF lead FBK, delay FBK
{
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL4_CTL1) & ~MEMPLL4_CTL1_REF_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL1, (temp | MEMPLL4_CTL1_REF_DL(0x0)));
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL4_CTL1) & ~MEMPLL4_CTL1_FB_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL1, (temp | MEMPLL4_CTL1_FB_DL(pll4_dl)));
}
else // REF lag FBK, delay REF
{
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL4_CTL1) & ~MEMPLL4_CTL1_REF_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL1, (temp | MEMPLL4_CTL1_REF_DL(pll4_dl)));
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL4_CTL1) & ~MEMPLL4_CTL1_FB_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL1, (temp | MEMPLL4_CTL1_FB_DL(0x0)));
}
}
if (!pop_pll3_done)
{
if (pop_pll3_phase == 0) // initial phase set to 0 for REF and FBK
{
temp = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1) & ~POP_MEMPLL3_CTL1_REF_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1, (temp | POP_MEMPLL3_CTL1_REF_DL(0x0)));
temp = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1) & ~POP_MEMPLL3_CTL1_FB_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1, (temp | POP_MEMPLL3_CTL1_FB_DL(0x0)));
}
else if (pop_pll3_phase == 1) // REF lead FBK, delay FBK
{
temp = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1) & ~POP_MEMPLL3_CTL1_REF_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1, (temp | POP_MEMPLL3_CTL1_REF_DL(0x0)));
temp = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1) & ~POP_MEMPLL3_CTL1_FB_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1, (temp | POP_MEMPLL3_CTL1_FB_DL(pop_pll3_dl)));
}
else // REF lag FBK, delay REF
{
temp = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1) & ~POP_MEMPLL3_CTL1_REF_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1, (temp | POP_MEMPLL3_CTL1_REF_DL(pop_pll3_dl)));
temp = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1) & ~POP_MEMPLL3_CTL1_FB_DL_MASK;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1, (temp | POP_MEMPLL3_CTL1_FB_DL(0x0)));
}
}
// Delay 20 us
BL_GPT_UDELAY(20);
/***********************************************
* 4. Enable jitter meter
************************************************/
if (!pll2_done)
{
// enable pll2 jitter meter
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL) | MEMPLL_JMETER_CTL_EN(0);
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL, temp);
}
if (!pll3_done)
{
// enable pll3 jitter meter
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL) | MEMPLL_JMETER_CTL_EN(1);
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL, temp);
}
if (!pll4_done)
{
// enable pll4 jitter meter
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL) | MEMPLL_JMETER_CTL_EN(2);
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL, temp);
}
if (!pop_pll3_done)
{
// enable pop_pll3 jitter meter
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL) | MEMPLL_JMETER_CTL_EN(3);
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL, temp);
}
// wait for jitter meter done
if (!pll2_done) {
while (!(DRV_Reg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL)&MEMPLL_JMETER_CTL_DONE(0)));
}
if (!pll3_done) {
while (!(DRV_Reg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL)&MEMPLL_JMETER_CTL_DONE(1)));
}
if (!pll4_done) {
while (!(DRV_Reg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL)&MEMPLL_JMETER_CTL_DONE(2)));
}
if (!pop_pll3_done) {
while (!(DRV_Reg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL)&MEMPLL_JMETER_CTL_DONE(3)));
}
/***********************************************
* 5. Check jitter meter counter value
************************************************/
if (!pll2_done)
{
one_count = MEMPLLn_JMETER_STS_ONES_CNT_VAL(0);
zero_count = MEMPLLn_JMETER_STS_ZEROS_CNT_VAL(0);
if (pll2_phase == 0)
{
if (zero_count > (one_count+MEMPLL_JMETER_CONFIDENCE_CNT))
{
// REF lead FBK
pll2_phase = 1;
pll2_dl++;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL2 initial phase: REF lead FBK, one_cnt/zero_cnt = %d/%d\r\n", one_count, zero_count);
}
else if (one_count > (zero_count+MEMPLL_JMETER_CONFIDENCE_CNT))
{
// REF lag FBK
pll2_phase = 2;
pll2_dl++;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL2 initial phase: REF lag FBK, one_cnt/zero_cnt = %d/%d\r\n", one_count, zero_count);
}
else
{
// in phase at initial
pll2_done = 1;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL2 initial phase: REF in-phase FBK, one_cnt/zero_cnt = %d/%d\r\n", one_count, zero_count);
}
}
else if (pll2_phase == 1)
{
if ((one_count+MEMPLL_JMETER_CONFIDENCE_CNT) >= zero_count)
{
pll2_done = 1;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL2 REF_DL: 0x0, FBK_DL: 0x%x, one_cnt/zero_cnt = %d/%d\n", pll2_dl, one_count, zero_count);
}
else
{
pll2_dl++;
}
}
else
{
if ((zero_count+MEMPLL_JMETER_CONFIDENCE_CNT) >= one_count)
{
pll2_done = 1;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL2 REF_DL: 0x%x, FBK_DL: 0x0, one_cnt/zero_cnt = %d/%d\n", pll2_dl, one_count, zero_count);
}
else
{
pll2_dl++;
}
}
}
if (!pll3_done)
{
one_count = MEMPLLn_JMETER_STS_ONES_CNT_VAL(1);
zero_count = MEMPLLn_JMETER_STS_ZEROS_CNT_VAL(1);
if (pll3_phase == 0)
{
if (zero_count > (one_count+MEMPLL_JMETER_CONFIDENCE_CNT))
{
// REF lead FBK
pll3_phase = 1;
pll3_dl++;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL3 initial phase: REF lead FBK, one_cnt/zero_cnt = %d/%d\r\n", one_count, zero_count);
}
else if (one_count > (zero_count+MEMPLL_JMETER_CONFIDENCE_CNT))
{
// REF lag FBK
pll3_phase = 2;
pll3_dl++;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL3 initial phase: REF lag FBK, one_cnt/zero_cnt = %d/%d\r\n", one_count, zero_count);
}
else
{
// in phase at initial
pll3_done = 1;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL3 initial phase: REF in-phase FBK, one_cnt/zero_cnt = %d/%d\r\n", one_count, zero_count);
}
}
else if (pll3_phase == 1)
{
if ((one_count+MEMPLL_JMETER_CONFIDENCE_CNT) >= zero_count)
{
pll3_done = 1;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL3 REF_DL: 0x0, FBK_DL: 0x%x, one_cnt/zero_cnt = %d/%d\n", pll3_dl, one_count, zero_count);
}
else
{
pll3_dl++;
}
}
else
{
if ((zero_count+MEMPLL_JMETER_CONFIDENCE_CNT) >= one_count)
{
pll3_done = 1;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL3 REF_DL: 0x%x, FBK_DL: 0x0, one_cnt/zero_cnt = %d/%d\n", pll3_dl, one_count, zero_count);
}
else
{
pll3_dl++;
}
}
}
if (!pll4_done)
{
one_count = MEMPLLn_JMETER_STS_ONES_CNT_VAL(2);
zero_count = MEMPLLn_JMETER_STS_ZEROS_CNT_VAL(2);
if (pll4_phase == 0)
{
if (zero_count > (one_count+MEMPLL_JMETER_CONFIDENCE_CNT))
{
// REF lead FBK
pll4_phase = 1;
pll4_dl++;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL4 initial phase: REF lead FBK, one_cnt/zero_cnt = %d/%d\r\n", one_count, zero_count);
}
else if (one_count > (zero_count+MEMPLL_JMETER_CONFIDENCE_CNT))
{
// REF lag FBK
pll4_phase = 2;
pll4_dl++;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL4 initial phase: REF lag FBK, one_cnt/zero_cnt = %d/%d\r\n", one_count, zero_count);
}
else
{
// in phase at initial
pll4_done = 1;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL4 initial phase: REF in-phase FBK, one_cnt/zero_cnt = %d/%d\r\n", one_count, zero_count);
}
}
else if (pll4_phase == 1)
{
if ((one_count+MEMPLL_JMETER_CONFIDENCE_CNT) >= zero_count)
{
pll4_done = 1;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL4 REF_DL: 0x0, FBK_DL: 0x%x, one_cnt/zero_cnt = %d/%d\n", pll4_dl, one_count, zero_count);
}
else
{
pll4_dl++;
}
}
else
{
if ((zero_count+MEMPLL_JMETER_CONFIDENCE_CNT) >= one_count)
{
pll4_done = 1;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] PLL4 REF_DL: 0x%x, FBK_DL: 0x0, one_cnt/zero_cnt = %d/%d\n", pll4_dl, one_count, zero_count);
}
else
{
pll4_dl++;
}
}
}
if (!pop_pll3_done)
{
one_count = MEMPLLn_JMETER_STS_ONES_CNT_VAL(3);
zero_count = MEMPLLn_JMETER_STS_ZEROS_CNT_VAL(3);
if (pop_pll3_phase == 0)
{
if (zero_count > (one_count+MEMPLL_JMETER_CONFIDENCE_CNT))
{
// REF lead FBK
pop_pll3_phase = 1;
pop_pll3_dl++;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] POP_PLL3 initial phase: REF lead FBK, one_cnt/zero_cnt = %d/%d\r\n", one_count, zero_count);
}
else if (one_count > (zero_count+MEMPLL_JMETER_CONFIDENCE_CNT))
{
// REF lag FBK
pop_pll3_phase = 2;
pop_pll3_dl++;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] POP_PLL3 initial phase: REF lag FBK, one_cnt/zero_cnt = %d/%d\r\n", one_count, zero_count);
}
else
{
// in phase at initial
pop_pll3_done = 1;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] POP_PLL3 initial phase: REF in-phase FBK, one_cnt/zero_cnt = %d/%d\r\n", one_count, zero_count);
}
}
else if (pop_pll3_phase == 1)
{
if ((one_count+MEMPLL_JMETER_CONFIDENCE_CNT) >= zero_count)
{
pop_pll3_done = 1;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] POP_PLL3 REF_DL: 0x0, FBK_DL: 0x%x, one_cnt/zero_cnt = %d/%d\n", pop_pll3_dl, one_count, zero_count);
}
else
{
pop_pll3_dl++;
}
}
else
{
if ((zero_count+MEMPLL_JMETER_CONFIDENCE_CNT) >= one_count)
{
pop_pll3_done = 1;
BL_PRINT(LOG_INFO, "[PLL_Phase_Calib] POP_PLL3 REF_DL: 0x%x, FBK_DL: 0x0, one_cnt/zero_cnt = %d/%d\n", pop_pll3_dl, one_count, zero_count);
}
else
{
pop_pll3_dl++;
}
}
}
/***********************************************
* 6. Reset jitter meter value
************************************************/
// disable pll jitter meter
temp = DRV_Reg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL) &
~(MEMPLL_JMETER_CTL_EN(0) | MEMPLL_JMETER_CTL_EN(1) | MEMPLL_JMETER_CTL_EN(2) | MEMPLL_JMETER_CTL_EN(3));
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_JMETER_CTL, temp);
/*************************************************************
* 7. Check Result
* Return to step 1 to adjust next delay chain tap value.
* Until we have ~ 50% of one or zero count on jitter meter
**************************************************************/
if (pll2_done && pll3_done && pll4_done && pop_pll3_done)
{
ret = 0;
break;
}
if (pll2_dl >= 32 || pll3_dl >= 32 || pll4_dl >= 32 || pop_pll3_dl >= 32)
{
BL_PRINT(LOG_ERROR, "[mt_pll_init] MEMPLL calibration fail (%d-%d/%d-%d/%d-%d/%d-%d)\r\n",
pll2_done, pll2_dl, pll3_done, pll3_dl, pll4_done, pll4_dl, pop_pll3_done, pop_pll3_dl);
// We always return pass even if MEMPLL phase calibration is failed.
ret = 0;
break;
}
}
return ret;
#endif // end if defined(__FPGA__)
}
unsigned int abist_meter(int val)
{
#if 0
int output = 0, i = 0;
unsigned int temp, clk26cali_0, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1;
clk_dbg_cfg = DRV_Reg32(CLK_DBG_CFG);
pminit_write(CLK_DBG_CFG, val<<16); //sel abist_cksw and enable freq meter sel abist
clk_misc_cfg_0 = DRV_Reg32(CLK_MISC_CFG_0);
if(val == 16)
DRV_WriteReg32(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (0x1 << 24)); // select divider
else
DRV_WriteReg32(CLK_MISC_CFG_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (0x7 << 24)); // select divider
clk26cali_1 = DRV_Reg32(CLK26CALI_1);
if(val == 16)
pminit_write(CLK26CALI_1, 0x000f0000); //
else
pminit_write(CLK26CALI_1, 0x00ff0000); //
clk26cali_0 = DRV_Reg32(CLK26CALI_0);
if(val == 16)
{
pminit_write(CLK26CALI_0, 0x1100);
pminit_write(CLK26CALI_0, 0x1110);
}
else
{
pminit_write(CLK26CALI_0, 0x1000);
pminit_write(CLK26CALI_0, 0x1010);
}
/* wait frequency meter finish */
while (DRV_Reg32(CLK26CALI_0) & 0x10)
{
mdelay(10);
i++;
if(i > 10)
break;
}
temp = DRV_Reg32(CLK26CALI_1) & 0xFFFF;
if(val == 16)
output = (((16 * 26000) ) / temp)*2; // Khz
else
output = (((temp * 26000) ) / 256)*8; // Khz
pminit_write(CLK_DBG_CFG, clk_dbg_cfg);
pminit_write(CLK_MISC_CFG_0, clk_misc_cfg_0);
pminit_write(CLK26CALI_0, clk26cali_0);
pminit_write(CLK26CALI_1, clk26cali_1);
printk("measure= %d, freq = %d\n", temp, output);
if(i>10)
return 0;
else
return output;
#endif
}
int mtk_pmic_dvfs_wrapper_test(int loop_count)
{
int i = 0, try_count = 0, ap_dvfs_con = 0;
//PWRAPFUC();
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR0, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR1, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR2, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR3, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR4, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR5, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR6, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR7, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA0, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA1, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA2, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA3, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA4, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA5, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA6, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA7, 0x58);
while (loop_count--)
{
for (i = 0; i < 8; i++)
{
ap_dvfs_con = DRV_Reg32(AP_DVFS_CON_SET);
DRV_WriteReg32(AP_DVFS_CON_SET, (ap_dvfs_con & ~(0x7)) | i);
while ((DRV_Reg32(AP_DVFS_CON_SET) & 0x80000000) == 0)
{
try_count++;
if (try_count >= MAX_RETRY_COUNT)
{
switch ( raw_smp_processor_id())
{
case 0:
g_spm_fail_cpu0++;
break;
case 1:
g_spm_fail_cpu1++;
break;
case 2:
g_spm_fail_cpu2++;
break;
case 3:
g_spm_fail_cpu3++;
break;
default:
break;
}
//PWRAPLOG("FAIL: no response from PMIC wrapper\n");
return -1;
}
//PWRAPLOG("wait for PMIC response an ACK signal, retry count = %d\n", try_count);
msleep(10);
}
try_count = 0;
}
}
switch ( raw_smp_processor_id())
{
case 0:
g_spm_pass_cpu0++;
break;
case 1:
g_spm_pass_cpu1++;
break;
case 2:
g_spm_pass_cpu2++;
break;
case 3:
g_spm_pass_cpu3++;
break;
default:
break;
}
//PWRAPLOG("PASS: PMIC DVFS Wrapper stress pass\n");
return 0;
}
void platform_post_init(void)
{
boot_arg_t *bootarg;
struct ram_console_buffer *ram_console;
#ifdef PL_PROFILING
u32 profiling_time;
profiling_time = 0;
#endif
bootarg = (boot_arg_t*)BOOT_ARGUMENT_ADDR;
#if CFG_BATTERY_DETECT
#ifdef PL_PROFILING
profiling_time = get_timer(0);
#endif
/* normal boot to check battery exists or not */
if (g_boot_mode == NORMAL_BOOT && !hw_check_battery() && usb_accessory_in()) {
print("%s Wait for battery inserted...\n", MOD);
/* disable pmic pre-charging led */
pl_close_pre_chr_led();
/* enable force charging mode */
pl_charging(1);
do {
mdelay(300);
/* check battery exists or not */
if (hw_check_battery())
break;
/* kick all watchdogs */
platform_wdt_all_kick();
} while(1);
/* disable force charging mode */
pl_charging(0);
}
#ifdef PL_PROFILING
printf("#T#bat_detc=%d\n", get_timer(profiling_time));
#endif
#endif
#if !CFG_FPGA_PLATFORM
#ifdef PL_PROFILING
profiling_time = get_timer(0);
#endif
/* security check */
sec_lib_read_secro();
sec_boot_check();
device_APC_dom_setup();
#ifdef PL_PROFILING
printf("#T#sec_init=%d\n", get_timer(profiling_time));
#endif
#endif
/* Note that the powering on MD is AP CCCI's task. */
/* Because the following code is for MT6589, */
/* although CFG_MDJTAG_SWITCH should not be defined, */
/* we still disable the following code just in case */
#if 0
#if CFG_MDJTAG_SWITCH
unsigned int md_pwr_con;
/* md0 default power on and clock on */
/* md1 default power on and clock off */
/* ungate md1 */
/* rst_b = 0 */
md_pwr_con = DRV_Reg32(0x10006280);
md_pwr_con &= ~0x1;
DRV_WriteReg32(0x10006280, md_pwr_con);
/* enable clksq2 for md1 */
DRV_WriteReg32(0x10209000, 0x00001137);
udelay(200);
DRV_WriteReg32(0x10209000, 0x0000113f);
/* rst_b = 1 */
md_pwr_con = DRV_Reg32(0x10006280);
md_pwr_con |= 0x1;
DRV_WriteReg32(0x10006280, md_pwr_con);
/* switch to MD legacy JTAG */
/* this step is not essentially required */
#endif
#endif
/* Note that the triggering MD META modeis AP CCCI's task. */
/* Because the following code is for MT6589, */
/* although CFG_MDMETA_DETECT should not be defined, */
/* we still disable the following code just in case */
#if 0
#if CFG_MDMETA_DETECT
if (g_boot_mode == META_BOOT || g_boot_mode == ADVMETA_BOOT) {
/* trigger md0 to enter meta mode */
DRV_WriteReg32(0x20000010, 0x1);
/* trigger md1 to enter meta mode */
DRV_WriteReg32(0x30000010, 0x1);
} else {
/* md0 does not enter meta mode */
DRV_WriteReg32(0x20000010, 0x0);
/* md1 does not enter meta mode */
DRV_WriteReg32(0x30000010, 0x0);
}
#endif
#endif
#if CFG_RAM_CONSOLE
ram_console = (struct ram_console_buffer *)RAM_CONSOLE_ADDR;
if (ram_console->sig == RAM_CONSOLE_SIG) {
print("%s ram_console->start=0x%x\n", MOD, ram_console->start);
if (ram_console->start > RAM_CONSOLE_MAX_SIZE)
ram_console->start = 0;
ram_console->hw_status = g_rgu_status;
print("%s ram_console(0x%x)=0x%x (boot reason)\n", MOD,
ram_console->hw_status, g_rgu_status);
}
#endif
#if defined(CFG_MEM_PRESERVED_MODE)
//wake up core 1 and flush core 1 cache
print("%s core1 flush start\n", MOD);
bootup_slave_cpu();
print("%s core1 flush done\n", MOD);
//flush core 1 cache
print("%s core0 flush start\n", MOD);
#if 0
{
u32 i;
volatile u32 tmp;
tmp = 1;
// for verify cache flush, write in LK, flush in preloader
do {
}while(tmp);
for (i=0;i<0x100;i=i+4)
{
*(volatile u32 *)(CFG_DRAM_ADDR + 0x120000 + i) = 0xFFFFFFFF;
}
}
#endif
apmcu_dcache_clean_invalidate();
print("%s core0 flush done\n", MOD);
// while(1);
#endif //#if !defined(CFG_MEM_PRESERVED_MODE)
#if CFG_BOOT_ARGUMENT
//set UART1 GPIO to mode5, MD
mt_gpio_init_post(1);
bootarg->magic = BOOT_ARGUMENT_MAGIC;
bootarg->mode = g_boot_mode;
//efuse should use seclib_get_devinfo_with_index(),
//no need check 3G in 72
bootarg->e_flag = 0;
bootarg->log_port = CFG_UART_LOG;
bootarg->log_baudrate = CFG_LOG_BAUDRATE;
bootarg->log_enable = (u8)log_status();
bootarg->dram_rank_num = get_dram_rank_nr();
get_dram_rank_size(bootarg->dram_rank_size);
bootarg->boot_reason = g_boot_reason;
bootarg->meta_com_type = (u32)g_meta_com_type;
bootarg->meta_com_id = g_meta_com_id;
bootarg->boot_time = get_timer(g_boot_time);
print("\n%s boot reason: %d\n", MOD, g_boot_reason);
print("%s boot mode: %d\n", MOD, g_boot_mode);
print("%s META COM%d: %d\n", MOD, bootarg->meta_com_id, bootarg->meta_com_type);
print("%s <0x%x>: 0x%x\n", MOD, &bootarg->e_flag, bootarg->e_flag);
print("%s boot time: %dms\n", MOD, bootarg->boot_time);
#endif
}
void platform_init(void)
{
u32 ret, tmp;
boot_reason_t reason;
#ifdef PL_PROFILING
u32 profiling_time;
profiling_time = 0;
#endif
#if !defined(CFG_MEM_PRESERVED_MODE)
#ifdef PL_PROFILING
profiling_time = get_timer(0);
#endif
/* init watch dog, will enable AP watch dog */
mtk_wdt_init();
#ifdef PL_PROFILING
printf("#T#wdt_init=%d\n", get_timer(profiling_time));
profiling_time = get_timer(0); //for next
#endif
/*init kpd PMIC mode support*/
set_kpd_pmic_mode();
#ifdef PL_PROFILING
printf("#T#kpd_pmic=%d\n", get_timer(profiling_time));
#endif
#else
//Memory Preserved mode, disable WDT
DRV_WriteReg32(0x10007000, 0x22000000);
#endif
#if CFG_MDWDT_DISABLE
/* no need to disable MD WDT, the code here is for backup reason */
/* disable MD0 watch dog. */
DRV_WriteReg32(0x20050000, 0x2200);
#endif
#if !defined(CFG_MEM_PRESERVED_MODE)
#ifdef PL_PROFILING
profiling_time = get_timer(0);
#endif
//ALPS00427972, implement the analog register formula
//Set the calibration after power on
//Add here for eFuse, chip version checking -> analog register calibration
mt_usb_calibraion();
//ALPS00427972, implement the analog register formula
/* make usb11 phy enter savecurrent mode */
// USB11, USB host need it, 72 with host ip, but not list in feature list,
// USB20, USB target for target,
// access with UM (throught CPU) will mett all '?', means protect
// access with PM (BUS, not CPU) will mett all '0', means clock or Power is gating
//mt_usb11_phy_savecurrent();
#ifdef PL_PROFILING
printf("#T#usb calib=%d\n", get_timer(profiling_time));
profiling_time = get_timer(0); //for next
#endif
g_boot_reason = reason = platform_boot_status();
if (reason == BR_RTC || reason == BR_POWER_KEY || reason == BR_USB || reason == BR_WDT || reason == BR_WDT_BY_PASS_PWK
#ifdef RTC_2SEC_REBOOT_ENABLE
|| reason == BR_2SEC_REBOOT
#endif //#ifdef RTC_2SEC_REBOOT_ENABLE
)
rtc_bbpu_power_on();
#ifdef PL_PROFILING
printf("#T#BR&bbpu on=%d\n", get_timer(profiling_time));
profiling_time = get_timer(0); //for next
#endif
enable_PMIC_kpd_clock();
#ifdef PL_PROFILING
printf("#T#enable PMIC kpd clk=%d\n", get_timer(profiling_time));
#endif
#else
rtc_bbpu_power_on();
#endif
#if !defined(CFG_MEM_PRESERVED_MODE)
#if CFG_EMERGENCY_DL_SUPPORT
#ifdef PL_PROFILING
profiling_time = get_timer(0);
#endif
/* check if to enter emergency download mode */
if (mtk_detect_dl_keys()) {
platform_emergency_download(CFG_EMERGENCY_DL_TIMEOUT_MS);
}
#ifdef PL_PROFILING
printf("#T#chk_emgdwl=%d\n", get_timer(profiling_time));
#endif
#endif
#ifdef PL_PROFILING
profiling_time = get_timer(0);
#endif
/* init memory */
mt_mem_init();
#ifdef PL_PROFILING
printf("#T#mem_init&tst=%d\n", get_timer(profiling_time));
#endif
#endif
#ifdef MTK_MT8193_SUPPORT
mt8193_init();
#endif
#ifdef PL_PROFILING
profiling_time = get_timer(0);
#endif
/* init device storeage */
ret = boot_device_init();
print("%s Init Boot Device: %s(%d)\n", MOD, ret ? "FAIL" : "OK", ret);
#ifdef PL_PROFILING
printf("#T#bootdev_init=%d\n", get_timer(profiling_time));
#endif
#if CFG_REBOOT_TEST
mtk_wdt_sw_reset();
while(1);
#endif
}
void platform_pre_init(void)
{
u32 ret;
u32 pmic_ret;
u32 pwrap_ret,i;
#ifdef PL_PROFILING
u32 profiling_time;
profiling_time = 0;
#endif
pwrap_ret = 0;
i = 0;
ret = 0;
/* init timer */
mtk_timer_init();
/* init boot time */
g_boot_time = get_timer(0);
#if 0 /* FIXME */
/*
* NoteXXX: CPU 1 may not be reset clearly after power-ON.
* Need to apply a S/W workaround to manualy reset it first.
*/
{
U32 val;
val = DRV_Reg32(0xC0009010);
DRV_WriteReg32(0xC0009010, val | 0x2);
gpt_busy_wait_us(10);
DRV_WriteReg32(0xC0009010, val & ~0x2);
gpt_busy_wait_us(10);
}
#ifndef SLT_BOOTLOADER
/* power off cpu1 for power saving */
power_off_cpu1();
#endif
#endif
ptp_init1();
/* move pll code to audio_sys_ram */
memcpy((char *)&Image$$PLL_INIT$$Base, &__load_start_pll_text,
&__load_stop_pll_text - &__load_start_pll_text);
/* init pll */
/* for memory preserved mode */
// do not init pll/emi in memory preserved mode, due to code is located in EMI
// set all pll except EMI
mtk_pll_init();
/*GPIO init*/
#if (!(CFG_FPGA_PLATFORM)) && defined(DUMMY_AP_BOOTLOADER)
mt_gpio_set_default();
#endif
//set UART1 GPIO to mode1, AP
mt_gpio_init_post(0);
/* init uart baudrate when pll on */
mtk_uart_init(UART_SRC_CLK_FRQ, CFG_LOG_BAUDRATE);
/* init pmic i2c interface and pmic */
/* no need in MT6572*/
//i2c_ret = i2c_v1_init();
//retry 3 times for pmic wrapper init
#ifdef PL_PROFILING
profiling_time = get_timer(0);
#endif
pwrap_init_preloader();
/* check is uart cable in*/
#if (CFG_USB_UART_SWITCH)
platform_vusb_on();
if (is_uart_cable_inserted()) {
print("\n%s Switch to UART Mode\n", MOD);
mt_usb_set_to_uart_mode();
} else {
print("\n%s Keep stay in USB Mode\n", MOD);
}
#endif
if (platform_sram_repair_enable_check())
{
//MM SRAM Repair
ret = MFG_MM_SRAM_repair();
if (ret < 0 )
printf("MFG_MM_SRAM_repair fail\n");
else
printf("MFG_MM_SRAM_repair OK\n");
}
#ifdef PL_PROFILING
printf("#T#pwrap_init=%d\n", get_timer(profiling_time));
profiling_time = get_timer(0); //for next
#endif
pmic_ret = pmic_init();
//enable long press reboot function***************
#ifndef CFG_EVB_PLATFORM
#ifdef KPD_PMIC_LPRST_TD
#ifdef ONEKEY_REBOOT_NORMAL_MODE_PL
printf("ONEKEY_REBOOT_NORMAL_MODE_PL OK\n");
pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT);//pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT);
pmic_config_interface(TOP_RST_MISC, (U32)KPD_PMIC_LPRST_TD, PMIC_RG_PWRKEY_RST_TD_MASK, PMIC_RG_PWRKEY_RST_TD_SHIFT);
#endif
#endif
#endif
//************************************************
#ifdef PL_PROFILING
printf("#T#pmic_init=%d\n", get_timer(profiling_time));
#endif
print("%s Init PWRAP: %s(%d)\n", MOD, pwrap_ret ? "FAIL" : "OK", pwrap_ret);
print("%s Init PMIC: %s(%d)\n", MOD, pmic_ret ? "FAIL" : "OK", pmic_ret);
print("%s chip[%x]\n", MOD, platform_chip_ver());
}
