void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk) { // determine the SPI to use uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); obj->spi.instance = pinmap_merge(spi_data, spi_sclk); MBED_ASSERT((int)obj->spi.instance != NC); CLOCK_SYS_EnableSpiClock(obj->spi.instance); uint32_t spi_address[] = SPI_BASE_ADDRS; obj->spi.address = spi_address[obj->spi.instance]; DSPI_HAL_Init(obj->spi.address); DSPI_HAL_Disable(obj->spi.address); // set default format and frequency spi_format(obj, 8, 0, SPI_MSB); // 8 bits, mode 0 DSPI_HAL_SetDelay(obj->spi.address, kDspiCtar0, 0, 0, kDspiPcsToSck); spi_frequency(obj, 1000000); DSPI_HAL_Enable(obj->spi.address); DSPI_HAL_StartTransfer(obj->spi.address); // pin out the spi pins pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(miso, PinMap_SPI_MISO); pinmap_pinout(sclk, PinMap_SPI_SCLK); }
/*! * @brief DSPI master Polling. * * Thid function uses DSPI master to send an array to slave * and receive the array back from slave, * thencompare whether the two buffers are the same. */ int main(void) { uint32_t i; uint32_t loopCount = 1; SPI_Type * dspiBaseAddr = (SPI_Type*)SPI0_BASE; uint32_t dspiSourceClock; uint32_t calculatedBaudRate; dspi_device_t masterDevice; dspi_command_config_t commandConfig = { .isChipSelectContinuous = false, .whichCtar = kDspiCtar0, .whichPcs = kDspiPcs0, .clearTransferCount = true, .isEndOfQueue = false }; // Init hardware hardware_init(); // Init OSA layer, used in DSPI_DRV_MasterTransferBlocking. OSA_Init(); // Call this function to initialize the console UART. This function // enables the use of STDIO functions (printf, scanf, etc.) dbg_uart_init(); // Print a note. printf("\r\n DSPI board to board polling example"); printf("\r\n This example run on instance 0 "); printf("\r\n Be sure DSPI0-DSPI0 are connected "); // Configure SPI pins. configure_spi_pins(DSPI_MASTER_INSTANCE); // Enable DSPI clock. CLOCK_SYS_EnableSpiClock(DSPI_MASTER_INSTANCE); // Initialize the DSPI module registers to default value, which disables the module DSPI_HAL_Init(dspiBaseAddr); // Set to master mode. DSPI_HAL_SetMasterSlaveMode(dspiBaseAddr, kDspiMaster); // Configure for continuous SCK operation DSPI_HAL_SetContinuousSckCmd(dspiBaseAddr, false); // Configure for peripheral chip select polarity DSPI_HAL_SetPcsPolarityMode(dspiBaseAddr, kDspiPcs0, kDspiPcs_ActiveLow); // Disable FIFO operation. DSPI_HAL_SetFifoCmd(dspiBaseAddr, false, false); // Initialize the configurable delays: PCS-to-SCK, prescaler = 0, scaler = 1 DSPI_HAL_SetDelay(dspiBaseAddr, kDspiCtar0, 0, 1, kDspiPcsToSck); // DSPI system enable DSPI_HAL_Enable(dspiBaseAddr); // Configure baudrate. masterDevice.dataBusConfig.bitsPerFrame = 8; masterDevice.dataBusConfig.clkPhase = kDspiClockPhase_FirstEdge; masterDevice.dataBusConfig.clkPolarity = kDspiClockPolarity_ActiveHigh; masterDevice.dataBusConfig.direction = kDspiMsbFirst; DSPI_HAL_SetDataFormat(dspiBaseAddr, kDspiCtar0, &masterDevice.dataBusConfig); // Get DSPI source clock. dspiSourceClock = CLOCK_SYS_GetSpiFreq(DSPI_MASTER_INSTANCE); calculatedBaudRate = DSPI_HAL_SetBaudRate(dspiBaseAddr, kDspiCtar0, TRANSFER_BAUDRATE, dspiSourceClock); printf("\r\n Transfer at baudrate %lu \r\n", calculatedBaudRate); while(1) { // Initialize the transmit buffer. for (i = 0; i < TRANSFER_SIZE; i++) { sendBuffer[i] = i + loopCount; } // Print out transmit buffer. printf("\r\n Master transmit:"); for (i = 0; i < TRANSFER_SIZE; i++) { // Print 16 numbers in a line. if ((i & 0x0F) == 0) { printf("\r\n "); } printf(" %02X", sendBuffer[i]); } // Reset the receive buffer. for (i = 0; i < TRANSFER_SIZE; i++) { receiveBuffer[i] = 0; } // Restart the transfer by stop then start again, this will clear out the shift register DSPI_HAL_StopTransfer(dspiBaseAddr); // Flush the FIFOs DSPI_HAL_SetFlushFifoCmd(dspiBaseAddr, true, true); // Clear status flags that may have been set from previous transfers. DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxComplete); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiEndOfQueue); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoUnderflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoFillRequest); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoOverflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest); // Clear the transfer count. DSPI_HAL_PresetTransferCount(dspiBaseAddr, 0); // Start the transfer process in the hardware DSPI_HAL_StartTransfer(dspiBaseAddr); // Send the data to slave. for (i = 0; i < TRANSFER_SIZE; i++) { // Write data to PUSHR DSPI_HAL_WriteDataMastermodeBlocking(dspiBaseAddr, &commandConfig, sendBuffer[i]); // Delay to wait slave is ready. OSA_TimeDelay(1); } // Delay to wait slave is ready. OSA_TimeDelay(10); // Restart the transfer by stop then start again, this will clear out the shift register DSPI_HAL_StopTransfer(dspiBaseAddr); // Flush the FIFOs DSPI_HAL_SetFlushFifoCmd(dspiBaseAddr, true, true); //Clear status flags that may have been set from previous transfers. DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxComplete); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiEndOfQueue); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoUnderflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoFillRequest); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoOverflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest); // Clear the transfer count. DSPI_HAL_PresetTransferCount(dspiBaseAddr, 0); // Start the transfer process in the hardware DSPI_HAL_StartTransfer(dspiBaseAddr); // Receive the data from slave. for (i = 0; i < TRANSFER_SIZE; i++) { // Write command to PUSHR. DSPI_HAL_WriteDataMastermodeBlocking(dspiBaseAddr, &commandConfig, 0); // Check RFDR flag while (DSPI_HAL_GetStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest)== false) {} // Read data from POPR receiveBuffer[i] = DSPI_HAL_ReadData(dspiBaseAddr); // Clear RFDR flag DSPI_HAL_ClearStatusFlag(dspiBaseAddr,kDspiRxFifoDrainRequest); // Delay to wait slave is ready. OSA_TimeDelay(1); } // Print out receive buffer. printf("\r\n Master receive:"); for (i = 0; i < TRANSFER_SIZE; i++) { // Print 16 numbers in a line. if ((i & 0x0F) == 0) { printf("\r\n "); } printf(" %02X", receiveBuffer[i]); } // Check receiveBuffer. for (i = 0; i < TRANSFER_SIZE; ++i) { if (receiveBuffer[i] != sendBuffer[i]) { // Master received incorrect. printf("\r\n ERROR: master received incorrect "); return -1; } } printf("\r\n DSPI Master Sends/ Recevies Successfully"); // Wait for press any key. printf("\r\n Press any key to run again"); getchar(); // Increase loop count to change transmit buffer. loopCount++; } }
/*FUNCTION********************************************************************** * * Function Name : DSPI_DRV_DmaMasterInit * Description : Initializes a DSPI instance for master mode operation to work with DMA. * This function uses a dma driven method for transferring data. * This function initializes the run-time state structure to track the ongoing * transfers, ungates the clock to the DSPI module, resets the DSPI module, initializes the module * to user defined settings and default settings, configures the IRQ state structure, enables * the module-level interrupt to the core, and enables the DSPI module. * The CTAR parameter is special in that it allows the user to have different SPI devices * connected to the same DSPI module instance in addition to different peripheral chip * selects. Each CTAR contains the bus attributes associated with that particular SPI device. * For most use cases where only one SPI device is connected per DSPI module * instance, use CTAR0. * This is an example to set up and call the DSPI_DRV_DmaMasterInit function by passing * in these parameters: * dspi_dma_master_state_t dspiDmaState; <- the user simply allocates memory for this struct * uint32_t calculatedBaudRate; * dspi_dma_master_user_config_t userConfig; <- the user fills out members for this struct * userConfig.isChipSelectContinuous = false; * userConfig.isSckContinuous = false; * userConfig.pcsPolarity = kDspiPcs_ActiveLow; * userConfig.whichCtar = kDspiCtar0; * userConfig.whichPcs = kDspiPcs0; * DSPI_DRV_DmaMasterInit(masterInstance, &dspiDmaState, &userConfig); * *END**************************************************************************/ dspi_status_t DSPI_DRV_DmaMasterInit(uint32_t instance, dspi_dma_master_state_t * dspiDmaState, const dspi_dma_master_user_config_t * userConfig) { uint32_t dspiSourceClock; SPI_Type *base = g_dspiBase[instance]; dma_request_source_t dspiTxDmaRequest = kDmaRequestMux0Disable; dma_request_source_t dspiRxDmaRequest = kDmaRequestMux0Disable; /* Check parameter pointers to make sure there are not NULL */ if ((dspiDmaState == NULL) || (userConfig == NULL)) { return kStatus_DSPI_InvalidParameter; } /* Clear the run-time state struct for this instance.*/ memset(dspiDmaState, 0, sizeof(* dspiDmaState)); /* Note, remember to first enable clocks to the DSPI module before making any register accesses * Enable clock for DSPI */ CLOCK_SYS_EnableSpiClock(instance); /* Get module clock freq*/ dspiSourceClock = CLOCK_SYS_GetSpiFreq(instance); /* Configure the run-time state struct with the DSPI source clock */ dspiDmaState->dspiSourceClock = dspiSourceClock; /* Configure the run-time state struct with the data command parameters*/ dspiDmaState->whichCtar = userConfig->whichCtar; /* set the dspiDmaState struct CTAR*/ dspiDmaState->whichPcs = userConfig->whichPcs; /* set the dspiDmaState struct whichPcs*/ dspiDmaState->isChipSelectContinuous = userConfig->isChipSelectContinuous; /* continuous PCS*/ /* Initialize the DSPI module registers to default value, which disables the module */ DSPI_HAL_Init(base); /* Init the interrupt sync object.*/ if (OSA_SemaCreate(&dspiDmaState->irqSync, 0) != kStatus_OSA_Success) { return kStatus_DSPI_Error; } /* Set to master mode.*/ DSPI_HAL_SetMasterSlaveMode(base, kDspiMaster); /* Configure for continuous SCK operation*/ DSPI_HAL_SetContinuousSckCmd(base, userConfig->isSckContinuous); /* Configure for peripheral chip select polarity*/ DSPI_HAL_SetPcsPolarityMode(base, userConfig->whichPcs, userConfig->pcsPolarity); /* Enable fifo operation (regardless of FIFO depth) */ DSPI_HAL_SetFifoCmd(base, true, true); /* Initialize the configurable delays: PCS-to-SCK, prescaler = 0, scaler = 1 */ DSPI_HAL_SetDelay(base, userConfig->whichCtar, 0, 1, kDspiPcsToSck); /* Save runtime structure pointers to irq handler can point to the correct state structure*/ g_dspiStatePtr[instance] = dspiDmaState; /* enable the interrupt*/ INT_SYS_EnableIRQ(g_dspiIrqId[instance]); /* DSPI system enable */ DSPI_HAL_Enable(base); /* Request DMA channels from the DMA peripheral driver. * Note, some MCUs have a separate RX and TX DMA request for each DSPI instance, while * other MCUs have a separate RX and TX DMA request for DSPI instance 0 only and shared DMA * requests for all other instances. Therefore, use the DSPI feature file to distinguish * how to request DMA channels between the various MCU DSPI instances. * For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel. */ switch (instance) { case 0: /* SPI0 */ #if FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(0) dspiRxDmaRequest = kDmaRequestMux0SPI0Rx; dspiTxDmaRequest = kDmaRequestMux0SPI0Tx; #else /* DMA is simple link control, so DSPI - DMA driver does not support the case that DSPI have * shared DMA channels */ return kStatus_DSPI_DMAChannelInvalid; #endif break; #if (SPI_INSTANCE_COUNT > 1) case 1: /* SPI1 */ #if FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(1) dspiRxDmaRequest = kDmaRequestMux0SPI1Rx; dspiTxDmaRequest = kDmaRequestMux0SPI1Tx; #else /* DMA is simple link control, so DSPI - DMA driver does not support the case that DSPI have * shared DMA channels */ return kStatus_DSPI_DMAChannelInvalid; #endif break; #endif #if (SPI_INSTANCE_COUNT > 2) case 2: /* SPI2 */ #if FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(2) dspiRxDmaRequest = kDmaRequestMux0SPI2Rx; dspiTxDmaRequest = kDmaRequestMux0SPI2Tx; #else /* DMA is simple link control, so DSPI - DMA driver does not support the case that DSPI have * shared DMA channels */ return kStatus_DSPI_DMAChannelInvalid; #endif break; #endif default : return kStatus_DSPI_InvalidInstanceNumber; } /* This channel transfers data from RX FIFO to receiveBuffer */ if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel, dspiRxDmaRequest, &dspiDmaState->dmaRxChannel)) { return kStatus_DSPI_DMAChannelInvalid; } /* This channel transfers data from transmitBuffer to TX FIFO */ if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel, dspiTxDmaRequest, &dspiDmaState->dmaTxDataChannel)) { return kStatus_DSPI_DMAChannelInvalid; } /* Source buffer to intermediate command/data * This channel is not activated by dma request, but by channel link. */ if (DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0Disable, &dspiDmaState->dmaTxCmdChannel) == kDmaInvalidChannel) { return kStatus_DSPI_DMAChannelInvalid; } /* Start the transfer process in the hardware */ DSPI_HAL_StartTransfer(base); return kStatus_DSPI_Success; }
int main (void) { uint8_t msg; uint32_t timeout = 0; uint32_t var; volatile uint16_t count; OSA_Init(); hardware_init(); dbg_uart_init(); configure_spi_pins(HW_SPI0); printf("dspi_edma_test_slave\r\n"); printf("\r\nDemo started...\r\n"); // Initialize configuration edma_init(); edma_dspi_rx_setup(kEDMAChannel2, (uint32_t)&g_slaveRxBuffer); dspi_slave_setup(HW_SPI0, SPI_BAUDRATE); printf("Press space bar to begin.\r\n"); msg = 'A'; while(msg != ' ') { msg = getchar(); } printf("\r\nDemo started...\r\n"); // Slave only have PCS0 PORT_HAL_SetMuxMode(PORTC_BASE, 0u, kPortMuxAlt7); // Enable eDMA channels requests to initiate DSPI transfers. EDMA_HAL_SetDmaRequestCmd(DMA_BASE, kEDMAChannel2, true); DSPI_HAL_StartTransfer(SPI0_BASE); // Waiting transfer complete printf("waiting transfer complete...\r\n"); while((bReceivedFlag == false) & (timeout < 50)) { OSA_TimeDelay(100); timeout++; } if(bReceivedFlag == false) { printf("No date received, please check connections\r\n"); } printf("received data:\r\n"); for(count = 0; count < TEST_DATA_LEN; count++) { var = g_slaveRxBuffer[count]; printf("%08X\t", (unsigned int)var); if((count + 1) % 4 == 0) { printf("\r\n"); } } printf("\r\nEnd of demo.\r\n"); }
/*! * @brief DSPI slave Polling. * * This function sends back received buffer from master through DSPI interface. */ int main(void) { uint32_t i; SPI_Type * dspiBaseAddr = (SPI_Type*)SPI0_BASE; dspi_slave_user_config_t slaveConfig; // Init hardware hardware_init(); // Init OSA layer, used in DSPI_DRV_MasterTransferBlocking. OSA_Init(); // Call this function to initialize the console UART. This function // enables the use of STDIO functions (printf, scanf, etc.) dbg_uart_init(); // Configure SPI pins. configure_spi_pins(DSPI_SLAVE_INSTANCE); // Print a note. printf("\r\n DSPI board to board polling example"); printf("\r\n This example run on instance 0 "); printf("\r\n Be sure DSPI0-DSPI0 are connected "); // Enable clock for DSPI CLOCK_SYS_EnableSpiClock(DSPI_SLAVE_INSTANCE); // Reset the DSPI module, which also disables the DSPI module DSPI_HAL_Init(dspiBaseAddr); // Set to slave mode. DSPI_HAL_SetMasterSlaveMode(dspiBaseAddr, kDspiSlave); // Set data format slaveConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge; slaveConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh; slaveConfig.dataConfig.bitsPerFrame = 8; DSPI_HAL_SetDataFormat(dspiBaseAddr, kDspiCtar0, &(slaveConfig.dataConfig)); // DSPI system enable DSPI_HAL_Enable(dspiBaseAddr); // Disable FIFO operation. DSPI_HAL_SetFifoCmd(dspiBaseAddr, false, false); while(1) { printf("\r\n Slave example is running..."); // Reset the receive buffer. for (i = 0; i < TRANSFER_SIZE; i++) { receiveBuffer[i] = 0; } // Restart the transfer by stop then start again, this will clear out the shift register DSPI_HAL_StopTransfer(dspiBaseAddr); // Flush the FIFOs DSPI_HAL_SetFlushFifoCmd(dspiBaseAddr, true, true); // Clear status flags that may have been set from previous transfers DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxComplete); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiEndOfQueue); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoUnderflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoFillRequest); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoOverflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest); // Clear the transfer count DSPI_HAL_PresetTransferCount(dspiBaseAddr, 0); // Start the transfer process in the hardware DSPI_HAL_StartTransfer(dspiBaseAddr); for (i = 0; i < TRANSFER_SIZE; i++) { // Check RFDR flag while (DSPI_HAL_GetStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest)== false) {} // Read data from POPR receiveBuffer[i] = DSPI_HAL_ReadData(dspiBaseAddr); // Clear RFDR flag DSPI_HAL_ClearStatusFlag(dspiBaseAddr,kDspiRxFifoDrainRequest); } // Restart the transfer by stop then start again, this will clear out the shift register DSPI_HAL_StopTransfer(dspiBaseAddr); // Flush the FIFOs DSPI_HAL_SetFlushFifoCmd(dspiBaseAddr, true, true); // Clear status flags that may have been set from previous transfers DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxComplete); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiEndOfQueue); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoUnderflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoFillRequest); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoOverflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest); // Clear the transfer count DSPI_HAL_PresetTransferCount(dspiBaseAddr, 0); // Start the transfer process in the hardware DSPI_HAL_StartTransfer(dspiBaseAddr); // Send the data to slave. for (i = 0; i < TRANSFER_SIZE; i++) { // Write data to PUSHR DSPI_HAL_WriteDataSlavemodeBlocking(dspiBaseAddr, receiveBuffer[i]); } // Print out receive buffer. printf("\r\n Slave receive:"); for (i = 0; i < TRANSFER_SIZE; i++) { // Print 16 numbers in a line. if ((i & 0x0F) == 0) { printf("\r\n "); } printf(" %02X", receiveBuffer[i]); } } }
/************************************************************************* * Function Name: SPI0_init * Parameters: none * Return: none * Description: SPI initialization *************************************************************************/ void SPI0_init(void) { dspi_baud_rate_divisors_t divisors; divisors.doubleBaudRate = 0; divisors.baudRateDivisor = 3; divisors.prescaleDivisor = 3; dspi_data_format_config_t config; config.clkPhase = kDspiClockPhase_SecondEdge; config.bitsPerFrame = 8; config.clkPolarity = kDspiClockPolarity_ActiveHigh; config.direction = kDspiMsbFirst; #if defined(KV10Z7_SERIES) PORT_HAL_SetMuxMode(PORTC_BASE_PTR,2,kPortMuxAsGpio);// MC33937 RESET GPIO_HAL_SetPinDir(GPIOC_BASE_PTR, 2, kGpioDigitalOutput); PORT_HAL_SetMuxMode(PORTD_BASE_PTR,7,kPortMuxAsGpio);// MC33937 DRV_EN GPIO_HAL_SetPinDir(GPIOD_BASE_PTR, 7, kGpioDigitalOutput); #elif (defined(KV10Z1287_SERIES) || defined(KV11Z7_SERIES)) PORT_HAL_SetMuxMode(PORTE_BASE_PTR,29,kPortMuxAsGpio);// MC33937 DRV_EN GPIO_HAL_SetPinDir(GPIOE_BASE_PTR, 29, kGpioDigitalOutput); #endif GPIO_HAL_SetPinOutput(GPIOC_BASE_PTR, 2);//MC33937_RESET_HIGH; #if defined(KV10Z7_SERIES) GPIO_HAL_SetPinOutput(GPIOD_BASE_PTR, 7);//MC33937_ENABLE_HIGH; #elif (defined(KV10Z1287_SERIES) || defined(KV11Z7_SERIES)) GPIO_HAL_SetPinOutput(GPIOE_BASE_PTR, 29); #endif DSPI_HAL_StopTransfer(SPI0_BASE_PTR);// halt SPI before SPI setting DSPI_HAL_Enable(SPI0_BASE_PTR);//Enables the DSPI peripheral and sets the MCR MDIS to 0. DSPI_HAL_SetMasterSlaveMode(SPI0_BASE_PTR, kDspiMaster);//Enable Master Mode DSPI_HAL_SetPcsPolarityMode(SPI0_BASE_PTR, kDspiPcs0,kDspiPcs_ActiveLow);//The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of type dspi_pcs_polarity_config_t. DSPI_HAL_SetFifoCmd(SPI0_BASE_PTR, false, false);//Disable the DSPI FIFOs. DSPI_HAL_PresetTransferCount(SPI0_BASE_PTR, 0x0000);//Pre-sets the transfer count. DSPI_HAL_SetDelay(SPI0_BASE_PTR, kDspiCtar0,3,0, kDspiPcsToSck); // CTAR0 selection option for master or slave mode DSPI_HAL_SetDelay(SPI0_BASE_PTR, kDspiCtar0,2,0, kDspiLastSckToPcs); DSPI_HAL_SetDelay(SPI0_BASE_PTR, kDspiCtar0,0,2, kDspiAfterTransfer); DSPI_HAL_SetBaudDivisors(SPI0_BASE_PTR, kDspiCtar0, &divisors); DSPI_HAL_SetDataFormat(SPI0_BASE_PTR, kDspiCtar0, &config); DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiTxComplete);///*!< TCF status/interrupt enable */ DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiEndOfQueue);///*!< EOQF status/interrupt enable*/ DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiTxFifoUnderflow);///*!< TFUF status/interrupt enable*/ DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiTxFifoFillRequest);///*!< TFFF status/interrupt enable*/ DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiRxFifoOverflow);///*!< RFOF status/interrupt enable*/ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiTxComplete, false);/*!< TCF status/interrupt disable */ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiEndOfQueue, false);/*!< EOQF status/interrupt disable */ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiTxFifoUnderflow, false);/*!< TFUF status/interrupt disable*/ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiTxFifoFillRequest, false);/*!< TFFF status/interrupt disable*/ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiRxFifoOverflow, false);/*!< RFOF status/interrupt disable*/ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiRxFifoDrainRequest, false);/*!< RFDF status/interrupt disable*/ DSPI_HAL_StartTransfer(SPI0_BASE_PTR);// Starts the DSPI transfers, clears HALT bit in MCR. PORT_HAL_SetMuxMode(PORTD_BASE_PTR, 3, kPortMuxAlt2); PORT_HAL_SetMuxMode(PORTD_BASE_PTR, 2, kPortMuxAlt2); PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 0, kPortMuxAlt7); PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 5, kPortMuxAlt2); }
/*FUNCTION********************************************************************** * * Function Name : DSPI_DRV_MasterInit * Description : Initialize a DSPI instance for master mode operation. * This function uses a CPU interrupt driven method for transferring data. * This function will initialize the run-time state structure to keep track of the on-going * transfers, ungate the clock to the DSPI module, reset the DSPI module, initialize the module * to user defined settings and default settings, configure the IRQ state structure and enable * the module-level interrupt to the core, and enable the DSPI module. * The CTAR parameter is special in that it allows the user to have different SPI devices * connected to the same DSPI module instance in conjunction with different peripheral chip * selects. Each CTAR contains the bus attributes associated with that particular SPI device. * For simplicity and for most use cases where only one SPI device is connected per DSPI module * instance, it is recommended to use CTAR0. * The following is an example of how to set up the dspi_master_state_t and the * dspi_master_user_config_t parameters and how to call the DSPI_DRV_MasterInit function by passing * in these parameters: * dspi_master_state_t dspiMasterState; <- the user simply allocates memory for this struct * uint32_t calculatedBaudRate; * dspi_master_user_config_t userConfig; <- the user fills out members for this struct * userConfig.isChipSelectContinuous = false; * userConfig.isSckContinuous = false; * userConfig.pcsPolarity = kDspiPcs_ActiveLow; * userConfig.whichCtar = kDspiCtar0; * userConfig.whichPcs = kDspiPcs0; * DSPI_DRV_MasterInit(masterInstance, &dspiMasterState, &userConfig); * *END**************************************************************************/ dspi_status_t DSPI_DRV_MasterInit(uint32_t instance, dspi_master_state_t * dspiState, const dspi_master_user_config_t * userConfig) { uint32_t dspiSourceClock; dspi_status_t errorCode = kStatus_DSPI_Success; SPI_Type *base = g_dspiBase[instance]; /* Clear the run-time state struct for this instance.*/ memset(dspiState, 0, sizeof(* dspiState)); /* Note, remember to first enable clocks to the DSPI module before making any register accesses * Enable clock for DSPI */ CLOCK_SYS_EnableSpiClock(instance); /* Get module clock freq*/ dspiSourceClock = CLOCK_SYS_GetSpiFreq(instance); /* Configure the run-time state struct with the DSPI source clock */ dspiState->dspiSourceClock = dspiSourceClock; /* Configure the run-time state struct with the data command parameters*/ dspiState->whichCtar = userConfig->whichCtar; /* set the dspiState struct CTAR*/ dspiState->whichPcs = userConfig->whichPcs; /* set the dspiState struct whichPcs*/ dspiState->isChipSelectContinuous = userConfig->isChipSelectContinuous; /* continuous PCS*/ /* Initialize the DSPI module registers to default value, which disables the module */ DSPI_HAL_Init(base); /* Init the interrupt sync object.*/ OSA_SemaCreate(&dspiState->irqSync, 0); /* Initialize the DSPI module with user config */ /* Set to master mode.*/ DSPI_HAL_SetMasterSlaveMode(base, kDspiMaster); /* Configure for continuous SCK operation*/ DSPI_HAL_SetContinuousSckCmd(base, userConfig->isSckContinuous); /* Configure for peripheral chip select polarity*/ DSPI_HAL_SetPcsPolarityMode(base, userConfig->whichPcs, userConfig->pcsPolarity); /* Enable fifo operation (regardless of FIFO depth) */ DSPI_HAL_SetFifoCmd(base, true, true); /* Initialize the configurable delays: PCS-to-SCK, prescaler = 0, scaler = 1 */ DSPI_HAL_SetDelay(base, userConfig->whichCtar, 0, 1, kDspiPcsToSck); /* Save runtime structure pointers to irq handler can point to the correct state structure*/ g_dspiStatePtr[instance] = dspiState; /* enable the interrupt*/ INT_SYS_EnableIRQ(g_dspiIrqId[instance]); /* DSPI system enable */ DSPI_HAL_Enable(base); /* Start the transfer process in the hardware */ DSPI_HAL_StartTransfer(base); return errorCode; }
/*! * @brief Initiate (start) a transfer. This is not a public API as it is called from other * driver functions */ static dspi_status_t DSPI_DRV_MasterStartTransfer(uint32_t instance, const dspi_device_t * device) { /* instantiate local variable of type dspi_master_state_t and point to global state */ dspi_master_state_t * dspiState = (dspi_master_state_t *)g_dspiStatePtr[instance]; SPI_Type *base = g_dspiBase[instance]; uint32_t calculatedBaudRate; /* Check that we're not busy.*/ if (dspiState->isTransferInProgress) { return kStatus_DSPI_Busy; } /* Configure bus for this device. If NULL is passed, we assume the caller has * preconfigured the bus using DSPI_DRV_MasterConfigureBus(). * Do nothing for calculatedBaudRate. If the user wants to know the calculatedBaudRate * then they can call this function separately. */ if (device) { DSPI_DRV_MasterConfigureBus(instance, device, &calculatedBaudRate); dspiState->bitsPerFrame = device->dataBusConfig.bitsPerFrame;/*update dspiState bits/frame*/ } /* Check the transfer byte count. If bits/frame > 8, meaning 2 bytes and if * the transfer byte count is an odd count we'll have to increase the transfer byte count * by one and assert a flag to indicate to the send and receive functions that it will * need to handle an extra byte. */ if ((dspiState->bitsPerFrame > 8) && (dspiState->remainingSendByteCount & 1UL)) { dspiState->remainingSendByteCount += 1; dspiState->remainingReceiveByteCount += 1; dspiState->extraByte = true; } else { dspiState->extraByte = false; } /* Save information about the transfer for use by the ISR.*/ dspiState->isTransferInProgress = true; /* Restart the transfer by stop then start again, this will clear out the shift register */ DSPI_HAL_StopTransfer(base); /* flush the fifos*/ DSPI_HAL_SetFlushFifoCmd(base, true, true); /* Clear status flags that may have been set from previous transfers */ DSPI_HAL_ClearStatusFlag(base, kDspiTxComplete); DSPI_HAL_ClearStatusFlag(base, kDspiEndOfQueue); DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoUnderflow); DSPI_HAL_ClearStatusFlag(base, kDspiTxFifoFillRequest); DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoOverflow); DSPI_HAL_ClearStatusFlag(base, kDspiRxFifoDrainRequest); /* Clear the transfer count */ DSPI_HAL_PresetTransferCount(base, 0); /* Start the transfer, make sure to do this before filling the FIFO */ DSPI_HAL_StartTransfer(base); /* Fill up the DSPI FIFO (even if one word deep, data still written to data buffer) */ DSPI_DRV_MasterFillupTxFifo(instance); /* RX FIFO Drain request: RFDF_RE to enable RFDF interrupt * Since SPI is a synchronous interface, we only need to enable the RX interrupt. * The IRQ handler will get the status of RX and TX interrupt flags. */ DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateIntReq, true); return kStatus_DSPI_Success; }
uint16_t SpiInOut(Spi_t *obj, uint16_t outData) { uint16_t data = 0x00; if ((obj == NULL) || (obj->Spi) == NULL) { while (1) ; } if (obj->isSlave) { } else { dspi_command_config_t commandConfig = { .isChipSelectContinuous = false, .whichCtar = kDspiCtar0, .whichPcs = kDspiPcs0, .clearTransferCount = true, .isEndOfQueue = false }; if (outData != 0x00) { // Restart the transfer by stop then start again, this will clear out the shift register DSPI_HAL_StopTransfer(obj->Spi); // Flush the FIFOs DSPI_HAL_SetFlushFifoCmd(obj->Spi, true, true); // Clear status flags that may have been set from previous transfers. DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiTxComplete); DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiEndOfQueue); DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiTxFifoUnderflow); DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiTxFifoFillRequest); DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiRxFifoOverflow); DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiRxFifoDrainRequest); // Clear the transfer count. DSPI_HAL_PresetTransferCount(obj->Spi, 0); // Start the transfer process in the hardware DSPI_HAL_StartTransfer(obj->Spi); // Send the data to slave. // Write data to PUSHR DSPI_HAL_WriteDataMastermode(obj->Spi, &commandConfig, outData); } else { // Restart the transfer by stop then start again, this will clear out the shift register DSPI_HAL_StopTransfer(obj->Spi); // Flush the FIFOs DSPI_HAL_SetFlushFifoCmd(obj->Spi, true, true); //Clear status flags that may have been set from previous transfers. DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiTxComplete); DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiEndOfQueue); DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiTxFifoUnderflow); DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiTxFifoFillRequest); DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiRxFifoOverflow); DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiRxFifoDrainRequest); // Clear the transfer count. DSPI_HAL_PresetTransferCount(obj->Spi, 0); // Start the transfer process in the hardware DSPI_HAL_StartTransfer(obj->Spi); // Write command to PUSHR. DSPI_HAL_WriteDataMastermode(obj->Spi, &commandConfig, 0); // Check RFDR flag while (DSPI_HAL_GetStatusFlag(obj->Spi, kDspiRxFifoDrainRequest) == false) { } // Read data from POPR data = DSPI_HAL_ReadData(obj->Spi); // Clear RFDR flag DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiRxFifoDrainRequest); } } return data; }