/**
* e1000_configure_tx - Configure 8254x Transmit Unit after Reset
* @adapter: board private structure
*
* Configure the Tx unit of the MAC after a reset.
**/
static void e1000_configure_tx ( struct e1000_adapter *adapter )
{
struct e1000_hw *hw = &adapter->hw;
uint32_t tctl;
DBG ( "e1000_configure_tx\n" );
E1000_WRITE_REG ( hw, E1000_TDBAH(0), 0 );
E1000_WRITE_REG ( hw, E1000_TDBAL(0), virt_to_bus ( adapter->tx_base ) );
E1000_WRITE_REG ( hw, E1000_TDLEN(0), adapter->tx_ring_size );
DBG ( "E1000_TDBAL(0): %#08x\n", E1000_READ_REG ( hw, E1000_TDBAL(0) ) );
DBG ( "E1000_TDLEN(0): %d\n", E1000_READ_REG ( hw, E1000_TDLEN(0) ) );
/* Setup the HW Tx Head and Tail descriptor pointers */
E1000_WRITE_REG ( hw, E1000_TDH(0), 0 );
E1000_WRITE_REG ( hw, E1000_TDT(0), 0 );
adapter->tx_head = 0;
adapter->tx_tail = 0;
adapter->tx_fill_ctr = 0;
/* Setup Transmit Descriptor Settings for eop descriptor */
tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) |
(E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
e1000_config_collision_dist ( hw );
E1000_WRITE_REG ( hw, E1000_TCTL, tctl );
E1000_WRITE_FLUSH ( hw );
}
/*********************************************************************
*
* Enable transmit unit.
*
**********************************************************************/
static void
igb_initialize_transmit_units(struct adapter *adapter)
{
struct tx_ring *txr = adapter->tx_rings;
struct e1000_hw *hw = &adapter->hw;
u32 tctl, txdctl;
int i;
tctl = txdctl = 0;
/* Setup the Tx Descriptor Rings */
for (i = 0; i < adapter->num_queues; i++, txr++) {
txdctl = 0;
E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
/* Setup the HW Tx Head and Tail descriptor pointers */
E1000_WRITE_REG(hw, E1000_TDT(i), 0);
E1000_WRITE_REG(hw, E1000_TDH(i), 0);
txr->queue_status = IGB_QUEUE_IDLE;
txdctl |= IGB_TX_PTHRESH;
txdctl |= IGB_TX_HTHRESH << 8;
txdctl |= IGB_TX_WTHRESH << 16;
txdctl |= E1000_TXDCTL_PRIORITY;
txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
}
}
/*------------------------------------------------------------------------
* _82545EM_configure_tx - Configure Transmit Unit after Reset
*------------------------------------------------------------------------
*/
local void _82545EM_configure_tx(
struct ether *ethptr
)
{
uint32 tctl, tipg, txdctl;
uint32 ipgr1, ipgr2;
/* Set the transmit descriptor write-back policy for both queues */
txdctl = e1000_io_readl(ethptr->iobase, E1000_TXDCTL(0));
txdctl &= ~E1000_TXDCTL_WTHRESH;
txdctl |= E1000_TXDCTL_GRAN;
e1000_io_writel(ethptr->iobase, E1000_TXDCTL(0), txdctl);
/* Program the Transmit Control Register */
tctl = e1000_io_readl(ethptr->iobase, E1000_TCTL);
tctl &= ~E1000_TCTL_CT;
tctl |= E1000_TCTL_RTLC |
E1000_TCTL_EN |
E1000_TCTL_PSP |
(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
tctl &= ~E1000_TCTL_COLD;
tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
/* Set the default values for the Tx Inter Packet Gap timer */
tipg = E1000_TIPG_IPGT_COPPER_DEFAULT;
ipgr1 = E1000_TIPG_IPGR1_DEFAULT;
ipgr2 = E1000_TIPG_IPGR2_DEFAULT;
tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
e1000_io_writel(ethptr->iobase, E1000_TIPG, tipg);
/* Set the Tx Interrupt Delay register */
e1000_io_writel(ethptr->iobase, E1000_TIDV, E1000_TIDV_DEFAULT);
e1000_io_writel(ethptr->iobase, E1000_TADV, E1000_TADV_DEFAULT);
/* Setup the HW Tx Head and Tail descriptor pointers */
e1000_io_writel(ethptr->iobase, E1000_TDBAL(0),
(uint32)ethptr->txRing);
e1000_io_writel(ethptr->iobase, E1000_TDBAH(0), 0);
e1000_io_writel(ethptr->iobase, E1000_TDLEN(0),
E1000_TDSIZE * ethptr->txRingSize);
e1000_io_writel(ethptr->iobase, E1000_TDH(0), 0);
e1000_io_writel(ethptr->iobase, E1000_TDT(0), 0);
e1000_io_writel(ethptr->iobase, E1000_TCTL, tctl);
}
/**
* e1000_transmit - Transmit a packet
*
* @v netdev Network device
* @v iobuf I/O buffer
*
* @ret rc Returns 0 on success, negative on failure
*/
static int e1000_transmit ( struct net_device *netdev, struct io_buffer *iobuf )
{
struct e1000_adapter *adapter = netdev_priv( netdev );
struct e1000_hw *hw = &adapter->hw;
uint32_t tx_curr = adapter->tx_tail;
struct e1000_tx_desc *tx_curr_desc;
DBG ("e1000_transmit\n");
if ( adapter->tx_fill_ctr == NUM_TX_DESC ) {
DBG ("TX overflow\n");
return -ENOBUFS;
}
/* Save pointer to iobuf we have been given to transmit,
netdev_tx_complete() will need it later
*/
adapter->tx_iobuf[tx_curr] = iobuf;
tx_curr_desc = ( void * ) ( adapter->tx_base ) +
( tx_curr * sizeof ( *adapter->tx_base ) );
DBG ( "tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) );
DBG ( "tx_curr_desc + 16 = %#08lx\n", virt_to_bus ( tx_curr_desc ) + 16 );
DBG ( "iobuf->data = %#08lx\n", virt_to_bus ( iobuf->data ) );
/* Add the packet to TX ring
*/
tx_curr_desc->buffer_addr =
virt_to_bus ( iobuf->data );
tx_curr_desc->lower.data =
E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP |
E1000_TXD_CMD_IFCS | iob_len ( iobuf );
tx_curr_desc->upper.data = 0;
DBG ( "TX fill: %d tx_curr: %d addr: %#08lx len: %zd\n", adapter->tx_fill_ctr,
tx_curr, virt_to_bus ( iobuf->data ), iob_len ( iobuf ) );
/* Point to next free descriptor */
adapter->tx_tail = ( adapter->tx_tail + 1 ) % NUM_TX_DESC;
adapter->tx_fill_ctr++;
/* Write new tail to NIC, making packet available for transmit
*/
wmb();
E1000_WRITE_REG ( hw, E1000_TDT(0), adapter->tx_tail );
return 0;
}
void dna_cleanup_tx_ring(struct ixgbe_ring *tx_ring) {
struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
struct e1000_hw *hw = &adapter->hw;
union e1000_adv_tx_desc *tx_desc, *shadow_tx_desc;
u32 tail;
u32 head = E1000_READ_REG(hw, E1000_TDH(tx_ring->reg_idx));
u32 i;
/* resetting all */
for (i=0; i<tx_ring->count; i++) {
tx_desc = IGB_TX_DESC(tx_ring, i);
shadow_tx_desc = IGB_TX_DESC(tx_ring, i + tx_ring->count);
tx_desc->read.olinfo_status = 0;
tx_desc->read.buffer_addr = shadow_tx_desc->read.buffer_addr;
}
tail = head; //(head + 1) % tx_ring->count;
E1000_WRITE_REG(hw, E1000_TDT(tx_ring->reg_idx), tail);
}
static void
igb_reset(struct adapter *adapter)
{
struct tx_ring *txr = adapter->tx_rings;
struct e1000_hw *hw = &adapter->hw;
u32 tctl, txdctl;
int i;
tctl = txdctl = 0;
/* Setup the Tx Descriptor Rings, leave queues idle */
for (i = 0; i < adapter->num_queues; i++, txr++) {
u64 bus_addr = txr->txdma.paddr;
/* idle the queue */
txdctl |= IGB_TX_PTHRESH;
txdctl |= IGB_TX_HTHRESH << 8;
txdctl |= IGB_TX_WTHRESH << 16;
E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
/* reset the descriptor head/tail */
E1000_WRITE_REG(hw, E1000_TDLEN(i),
adapter->num_tx_desc * sizeof(struct e1000_tx_desc));
E1000_WRITE_REG(hw, E1000_TDBAH(i),
(u_int32_t)(bus_addr >> 32));
E1000_WRITE_REG(hw, E1000_TDBAL(i),
(u_int32_t)bus_addr);
/* Setup the HW Tx Head and Tail descriptor pointers */
E1000_WRITE_REG(hw, E1000_TDT(i), 0);
E1000_WRITE_REG(hw, E1000_TDH(i), 0);
txr->queue_status = IGB_QUEUE_IDLE;
}
}
/**
* e1000_translate_register_82542 - Translate the proper register offset
* @reg: e1000 register to be read
*
* Registers in 82542 are located in different offsets than other adapters
* even though they function in the same manner. This function takes in
* the name of the register to read and returns the correct offset for
* 82542 silicon.
**/
u32 e1000_translate_register_82542(u32 reg)
{
/*
* Some of the 82542 registers are located at different
* offsets than they are in newer adapters.
* Despite the difference in location, the registers
* function in the same manner.
*/
switch (reg) {
case E1000_RA:
reg = 0x00040;
break;
case E1000_RDTR:
reg = 0x00108;
break;
case E1000_RDBAL(0):
reg = 0x00110;
break;
case E1000_RDBAH(0):
reg = 0x00114;
break;
case E1000_RDLEN(0):
reg = 0x00118;
break;
case E1000_RDH(0):
reg = 0x00120;
break;
case E1000_RDT(0):
reg = 0x00128;
break;
case E1000_RDBAL(1):
reg = 0x00138;
break;
case E1000_RDBAH(1):
reg = 0x0013C;
break;
case E1000_RDLEN(1):
reg = 0x00140;
break;
case E1000_RDH(1):
reg = 0x00148;
break;
case E1000_RDT(1):
reg = 0x00150;
break;
case E1000_FCRTH:
reg = 0x00160;
break;
case E1000_FCRTL:
reg = 0x00168;
break;
case E1000_MTA:
reg = 0x00200;
break;
case E1000_TDBAL(0):
reg = 0x00420;
break;
case E1000_TDBAH(0):
reg = 0x00424;
break;
case E1000_TDLEN(0):
reg = 0x00428;
break;
case E1000_TDH(0):
reg = 0x00430;
break;
case E1000_TDT(0):
reg = 0x00438;
break;
case E1000_TIDV:
reg = 0x00440;
break;
case E1000_VFTA:
reg = 0x00600;
break;
case E1000_TDFH:
reg = 0x08010;
break;
case E1000_TDFT:
reg = 0x08018;
break;
default:
break;
}
return reg;
}
/**
* e1000_configure_tx - Configure 8254x Transmit Unit after Reset
* @adapter: board private structure
*
* Configure the Tx unit of the MAC after a reset.
**/
static void e1000e_configure_tx ( struct e1000_adapter *adapter )
{
struct e1000_hw *hw = &adapter->hw;
u32 tctl, tipg, tarc;
u32 ipgr1, ipgr2;
DBGP ( "e1000_configure_tx\n" );
/* disable transmits while setting up the descriptors */
tctl = E1000_READ_REG ( hw, E1000_TCTL );
E1000_WRITE_REG ( hw, E1000_TCTL, tctl & ~E1000_TCTL_EN );
e1e_flush();
mdelay(10);
E1000_WRITE_REG ( hw, E1000_TDBAH(0), 0 );
E1000_WRITE_REG ( hw, E1000_TDBAL(0), virt_to_bus ( adapter->tx_base ) );
E1000_WRITE_REG ( hw, E1000_TDLEN(0), adapter->tx_ring_size );
DBG ( "E1000_TDBAL(0): %#08x\n", E1000_READ_REG ( hw, E1000_TDBAL(0) ) );
DBG ( "E1000_TDLEN(0): %d\n", E1000_READ_REG ( hw, E1000_TDLEN(0) ) );
/* Setup the HW Tx Head and Tail descriptor pointers */
E1000_WRITE_REG ( hw, E1000_TDH(0), 0 );
E1000_WRITE_REG ( hw, E1000_TDT(0), 0 );
adapter->tx_head = 0;
adapter->tx_tail = 0;
adapter->tx_fill_ctr = 0;
/* Set the default values for the Tx Inter Packet Gap timer */
tipg = DEFAULT_82543_TIPG_IPGT_COPPER; /* 8 */
ipgr1 = DEFAULT_82543_TIPG_IPGR1; /* 8 */
ipgr2 = DEFAULT_82543_TIPG_IPGR2; /* 6 */
if (adapter->flags & FLAG_TIPG_MEDIUM_FOR_80003ESLAN)
ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; /* 7 */
tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
ew32(TIPG, tipg);
/* Program the Transmit Control Register */
tctl = er32(TCTL);
tctl &= ~E1000_TCTL_CT;
tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
tarc = er32(TARC(0));
/*
* set the speed mode bit, we'll clear it if we're not at
* gigabit link later
*/
#define SPEED_MODE_BIT (1 << 21)
tarc |= SPEED_MODE_BIT;
ew32(TARC(0), tarc);
}
/* errata: program both queues to unweighted RR */
if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
tarc = er32(TARC(0));
tarc |= 1;
ew32(TARC(0), tarc);
tarc = er32(TARC(1));
tarc |= 1;
ew32(TARC(1), tarc);
}
/* Setup Transmit Descriptor Settings for eop descriptor */
adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
/* enable Report Status bit */
adapter->txd_cmd |= E1000_TXD_CMD_RS;
/*
* enable transmits in the hardware, need to do this
* after setting TARC(0)
*/
tctl |= E1000_TCTL_EN;
ew32(TCTL, tctl);
e1e_flush();
e1000e_config_collision_dist(hw);
}
int
igb_xmit(device_t *dev, unsigned int queue_index, struct igb_packet *packet)
{
struct adapter *adapter;
struct tx_ring *txr;
struct igb_tx_buffer *tx_buffer;
union e1000_adv_tx_desc *txd = NULL;
u32 cmd_type_len, olinfo_status = 0;
int i, first, last = 0;
int error = 0;
if (NULL == dev) return EINVAL;
adapter = (struct adapter *)dev->private_data;
if (NULL == adapter) return ENXIO;
txr = &adapter->tx_rings[queue_index];
if( !txr ) return EINVAL;
if (queue_index > adapter->num_queues)
return EINVAL;
if (NULL == packet)
return EINVAL;
if( sem_wait( adapter->memlock ) != 0 ) {
return errno;
}
packet->next = NULL; /* used for cleanup */
/* Set basic descriptor constants */
cmd_type_len = E1000_ADVTXD_DTYP_DATA;
cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
/* cmd_type_len |= E1000_ADVTXD_DCMD_VLE; to enable VLAN insertion */
/*
* Map the packet for DMA
*
* Capture the first descriptor index,
* this descriptor will have the index
* of the EOP which is the only one that
* now gets a DONE bit writeback.
*/
first = txr->next_avail_desc;
tx_buffer = &txr->tx_buffers[first];
/*
** Make sure we don't overrun the ring,
** we need nsegs descriptors and one for
** the context descriptor used for the
** offloads.
*/
if (txr->tx_avail <= 2) {
error = ENOSPC;
goto unlock;
}
/*
* Set up the context descriptor to specify
* launchtimes for the packet.
*/
igb_tx_ctx_setup(txr, packet);
/*
* for performance monitoring, report the DMA time of the tx desc wb
*/
olinfo_status |= E1000_TXD_DMA_TXDWB;
/* set payload length */
olinfo_status |= packet->len << E1000_ADVTXD_PAYLEN_SHIFT;
/* Set up our transmit descriptors */
i = txr->next_avail_desc;
/* we assume every packet is contiguous */
tx_buffer = &txr->tx_buffers[i];
txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
txd->read.buffer_addr = htole64(packet->map.paddr + packet->offset);
txd->read.cmd_type_len = htole32(cmd_type_len | packet->len);
txd->read.olinfo_status = htole32(olinfo_status);
last = i;
if (++i == adapter->num_tx_desc)
i = 0;
tx_buffer->packet = NULL;
tx_buffer->next_eop = -1;
txr->next_avail_desc = i;
txr->tx_avail-- ;
tx_buffer->packet = packet;
/*
* Last Descriptor of Packet
* needs End Of Packet (EOP)
* and Report Status (RS)
*/
txd->read.cmd_type_len |=
htole32(E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS);
/*
* Keep track in the first buffer which
* descriptor will be written back
*/
tx_buffer = &txr->tx_buffers[first];
tx_buffer->next_eop = last;
/*
* Advance the Transmit Descriptor Tail (TDT), this tells the E1000
* that this frame is available to transmit.
*/
E1000_WRITE_REG(&adapter->hw, E1000_TDT(txr->me), i);
++txr->tx_packets;
unlock:
if( sem_post( adapter->memlock ) != 0 ) {
return errno;
}
return(error);
}
/*------------------------------------------------------------------------
* ethwrite - write a packet to an E1000E device
*------------------------------------------------------------------------
*/
devcall ethwrite(
struct dentry *devptr, /* entry in device switch table */
void *buf, /* buffer that holds a packet */
uint32 len /* length of buffer */
)
{
struct ethcblk *ethptr; /* ptr to entry in ethertab */
struct eth_tx_desc *descptr;/* ptr to ring descriptor */
char *pktptr; /* ptr used during packet copy */
uint32 tail; /* index of ring buffer for pkt */
uint32 tdt;
ethptr = ðertab[devptr->dvminor];
/* Verify Ethernet interface is up and arguments are valid */
if ((ETH_STATE_UP != ethptr->state)
|| (len < ETH_HDR_LEN)
|| (len > ETH_MAX_PKT_LEN) ) {
return SYSERR;
}
/* If padding of short packet is enabled, the value in TX */
/* descriptor length feild should be not less than 17 */
/* bytes */
if (len < 17)
return SYSERR;
/* Wait for a free ring slot */
wait(ethptr->osem);
/* Find the tail of the ring to insert packet */
tail = ethptr->txTail;
descptr = (struct eth_tx_desc *)ethptr->txRing + tail;
/* Copy packet to transmit ring buffer */
pktptr = (char *)((uint32)descptr->buffer_addr & ADDR_BIT_MASK);
memcpy(pktptr, buf, len);
/* Insert transmitting command and length */
descptr->lower.data &= E1000_TXD_CMD_DEXT;
descptr->lower.data = E1000_TXD_CMD_IDE |
E1000_TXD_CMD_RS |
E1000_TXD_CMD_IFCS |
E1000_TXD_CMD_EOP |
len;
descptr->upper.data = 0;
/* Add descriptor by advancing the tail pointer */
tdt = eth_io_readl(ethptr->iobase, E1000_TDT(0));
tdt = (tdt + 1) % ethptr->txRingSize;
eth_io_writel(ethptr->iobase, E1000_TDT(0), tdt);
/* Advance the ring tail pointing to the next available ring */
/* descriptor */
ethptr->txTail = (ethptr->txTail + 1) % ethptr->txRingSize;
return len;
}
/*
* mac_dump - dump important mac registers
*/
void
mac_dump(void *instance)
{
struct e1000g *Adapter = (struct e1000g *)instance;
struct e1000_hw *hw = &Adapter->shared;
int i;
/* {name, offset} for each mac register */
Regi_t macreg[NUM_REGS] = {
{"CTRL", E1000_CTRL}, {"STATUS", E1000_STATUS},
{"EECD", E1000_EECD}, {"EERD", E1000_EERD},
{"CTRL_EXT", E1000_CTRL_EXT}, {"FLA", E1000_FLA},
{"MDIC", E1000_MDIC}, {"SCTL", E1000_SCTL},
{"FCAL", E1000_FCAL}, {"FCAH", E1000_FCAH},
{"FCT", E1000_FCT}, {"VET", E1000_VET},
{"ICR", E1000_ICR}, {"ITR", E1000_ITR},
{"ICS", E1000_ICS}, {"IMS", E1000_IMS},
{"IMC", E1000_IMC}, {"IAM", E1000_IAM},
{"RCTL", E1000_RCTL}, {"FCTTV", E1000_FCTTV},
{"TXCW", E1000_TXCW}, {"RXCW", E1000_RXCW},
{"TCTL", E1000_TCTL}, {"TIPG", E1000_TIPG},
{"AIT", E1000_AIT}, {"LEDCTL", E1000_LEDCTL},
{"PBA", E1000_PBA}, {"PBS", E1000_PBS},
{"EEMNGCTL", E1000_EEMNGCTL}, {"ERT", E1000_ERT},
{"FCRTL", E1000_FCRTL}, {"FCRTH", E1000_FCRTH},
{"PSRCTL", E1000_PSRCTL}, {"RDBAL(0)", E1000_RDBAL(0)},
{"RDBAH(0)", E1000_RDBAH(0)}, {"RDLEN(0)", E1000_RDLEN(0)},
{"RDH(0)", E1000_RDH(0)}, {"RDT(0)", E1000_RDT(0)},
{"RDTR", E1000_RDTR}, {"RXDCTL(0)", E1000_RXDCTL(0)},
{"RADV", E1000_RADV}, {"RDBAL(1)", E1000_RDBAL(1)},
{"RDBAH(1)", E1000_RDBAH(1)}, {"RDLEN(1)", E1000_RDLEN(1)},
{"RDH(1)", E1000_RDH(1)}, {"RDT(1)", E1000_RDT(1)},
{"RXDCTL(1)", E1000_RXDCTL(1)}, {"RSRPD", E1000_RSRPD},
{"RAID", E1000_RAID}, {"CPUVEC", E1000_CPUVEC},
{"TDFH", E1000_TDFH}, {"TDFT", E1000_TDFT},
{"TDFHS", E1000_TDFHS}, {"TDFTS", E1000_TDFTS},
{"TDFPC", E1000_TDFPC}, {"TDBAL(0)", E1000_TDBAL(0)},
{"TDBAH(0)", E1000_TDBAH(0)}, {"TDLEN(0)", E1000_TDLEN(0)},
{"TDH(0)", E1000_TDH(0)}, {"TDT(0)", E1000_TDT(0)},
{"TIDV", E1000_TIDV}, {"TXDCTL(0)", E1000_TXDCTL(0)},
{"TADV", E1000_TADV}, {"TARC(0)", E1000_TARC(0)},
{"TDBAL(1)", E1000_TDBAL(1)}, {"TDBAH(1)", E1000_TDBAH(1)},
{"TDLEN(1)", E1000_TDLEN(1)}, {"TDH(1)", E1000_TDH(1)},
{"TDT(1)", E1000_TDT(1)}, {"TXDCTL(1)", E1000_TXDCTL(1)},
{"TARC(1)", E1000_TARC(1)}, {"ALGNERRC", E1000_ALGNERRC},
{"RXERRC", E1000_RXERRC}, {"MPC", E1000_MPC},
{"SCC", E1000_SCC}, {"ECOL", E1000_ECOL},
{"MCC", E1000_MCC}, {"LATECOL", E1000_LATECOL},
{"COLC", E1000_COLC}, {"DC", E1000_DC},
{"TNCRS", E1000_TNCRS}, {"SEC", E1000_SEC},
{"CEXTERR", E1000_CEXTERR}, {"RLEC", E1000_RLEC},
{"XONRXC", E1000_XONRXC}, {"XONTXC", E1000_XONTXC},
{"XOFFRXC", E1000_XOFFRXC}, {"XOFFTXC", E1000_XOFFTXC},
{"FCRUC", E1000_FCRUC}, {"PRC64", E1000_PRC64},
{"PRC127", E1000_PRC127}, {"PRC255", E1000_PRC255},
{"PRC511", E1000_PRC511}, {"PRC1023", E1000_PRC1023},
{"PRC1522", E1000_PRC1522}, {"GPRC", E1000_GPRC},
{"BPRC", E1000_BPRC}, {"MPRC", E1000_MPRC},
{"GPTC", E1000_GPTC}, {"GORCL", E1000_GORCL},
{"GORCH", E1000_GORCH}, {"GOTCL", E1000_GOTCL},
{"GOTCH", E1000_GOTCH}, {"RNBC", E1000_RNBC},
{"RUC", E1000_RUC}, {"RFC", E1000_RFC},
{"ROC", E1000_ROC}, {"RJC", E1000_RJC},
{"MGTPRC", E1000_MGTPRC}, {"MGTPDC", E1000_MGTPDC},
{"MGTPTC", E1000_MGTPTC}, {"TORL", E1000_TORL},
{"TORH", E1000_TORH}, {"TOTL", E1000_TOTL},
{"TOTH", E1000_TOTH}, {"TPR", E1000_TPR},
{"TPT", E1000_TPT}, {"PTC64", E1000_PTC64},
{"PTC127", E1000_PTC127}, {"PTC255", E1000_PTC255},
{"PTC511", E1000_PTC511}, {"PTC1023", E1000_PTC1023},
{"PTC1522", E1000_PTC1522}, {"MPTC", E1000_MPTC},
{"BPTC", E1000_BPTC}, {"TSCTC", E1000_TSCTC},
{"TSCTFC", E1000_TSCTFC}, {"IAC", E1000_IAC},
{"ICRXPTC", E1000_ICRXPTC}, {"ICRXATC", E1000_ICRXATC},
{"ICTXPTC", E1000_ICTXPTC}, {"ICTXATC", E1000_ICTXATC},
{"ICTXQEC", E1000_ICTXQEC}, {"ICTXQMTC", E1000_ICTXQMTC},
{"ICRXDMTC", E1000_ICRXDMTC}, {"ICRXOC", E1000_ICRXOC},
{"RXCSUM", E1000_RXCSUM}, {"RFCTL", E1000_RFCTL},
{"WUC", E1000_WUC}, {"WUFC", E1000_WUFC},
{"WUS", E1000_WUS}, {"MRQC", E1000_MRQC},
{"MANC", E1000_MANC}, {"IPAV", E1000_IPAV},
{"MANC2H", E1000_MANC2H}, {"RSSIM", E1000_RSSIM},
{"RSSIR", E1000_RSSIR}, {"WUPL", E1000_WUPL},
{"GCR", E1000_GCR}, {"GSCL_1", E1000_GSCL_1},
{"GSCL_2", E1000_GSCL_2}, {"GSCL_3", E1000_GSCL_3},
{"GSCL_4", E1000_GSCL_4}, {"FACTPS", E1000_FACTPS},
{"FWSM", E1000_FWSM},
};
e1000g_log(Adapter, CE_CONT, "Begin MAC dump\n");
for (i = 0; i < NUM_REGS; i++) {
e1000g_log(Adapter, CE_CONT,
"macreg %10s offset: 0x%x value: 0x%x\n",
macreg[i].name, macreg[i].offset,
e1000_read_reg(hw, macreg[i].offset));
}
}
