static UINT32 READ_EA_32(m68ki_cpu_core *m68k, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); switch (mode) { case 0: // Dn { return REG_D[reg]; } case 2: // (An) { UINT32 ea = REG_A[reg]; return m68ki_read_32(m68k, ea); } case 3: // (An)+ { UINT32 ea = EA_AY_PI_32(m68k); return m68ki_read_32(m68k, ea); } case 5: // (d16, An) { UINT32 ea = EA_AY_DI_32(m68k); return m68ki_read_32(m68k, ea); } case 6: // (An) + (Xn) + d8 { UINT32 ea = EA_AY_IX_32(m68k); return m68ki_read_32(m68k, ea); } case 7: { switch (reg) { case 1: // (xxx).L { UINT32 d1 = OPER_I_16(m68k); UINT32 d2 = OPER_I_16(m68k); UINT32 ea = (d1 << 16) | d2; return m68ki_read_32(m68k, ea); } case 2: // (d16, PC) { UINT32 ea = EA_PCDI_32(m68k); return m68ki_read_32(m68k, ea); } case 4: // #<data> { return OPER_I_32(m68k); } default: fatalerror("MC68040: READ_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } break; } default: fatalerror("MC68040: READ_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } return 0; }
static UINT64 READ_EA_64(m68ki_cpu_core *m68k, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); UINT32 h1, h2; switch (mode) { case 2: // (An) { UINT32 ea = REG_A[reg]; h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 3: // (An)+ { UINT32 ea = REG_A[reg]; REG_A[reg] += 8; h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 5: // (d16, An) { UINT32 ea = EA_AY_DI_32(m68k); h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 7: { switch (reg) { case 4: // #<data> { h1 = OPER_I_32(m68k); h2 = OPER_I_32(m68k); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 2: // (d16, PC) { UINT32 ea = EA_PCDI_32(m68k); h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } default: fatalerror("MC68040: READ_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } break; } default: fatalerror("MC68040: READ_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } return 0; }
static void WRITE_EA_32(m68ki_cpu_core *m68k, int ea, UINT32 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); switch (mode) { case 0: // Dn { REG_D[reg] = data; break; } case 2: // (An) { UINT32 ea = REG_A[reg]; m68ki_write_32(m68k, ea, data); break; } case 3: // (An)+ { UINT32 ea = EA_AY_PI_32(m68k); m68ki_write_32(m68k, ea, data); break; } case 4: // -(An) { UINT32 ea = EA_AY_PD_32(m68k); m68ki_write_32(m68k, ea, data); break; } case 5: // (d16, An) { UINT32 ea = EA_AY_DI_32(m68k); m68ki_write_32(m68k, ea, data); break; } case 6: // (An) + (Xn) + d8 { UINT32 ea = EA_AY_IX_32(m68k); m68ki_write_32(m68k, ea, data); break; } case 7: { switch (reg) { case 1: // (xxx).L { UINT32 d1 = OPER_I_16(m68k); UINT32 d2 = OPER_I_16(m68k); UINT32 ea = (d1 << 16) | d2; m68ki_write_32(m68k, ea, data); break; } case 2: // (d16, PC) { UINT32 ea = EA_PCDI_32(m68k); m68ki_write_32(m68k, ea, data); break; } default: fatalerror("MC68040: WRITE_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } break; } default: fatalerror("MC68040: WRITE_EA_32: unhandled mode %d, reg %d, data %08X at %08X\n", mode, reg, data, REG_PC); } }
static floatx80 READ_EA_FPE(m68000_base_device *m68k, int ea) { floatx80 fpr; int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); switch (mode) { case 2: // (An) { UINT32 ea = REG_A(m68k)[reg]; fpr = load_extended_float80(m68k, ea); break; } case 3: // (An)+ { UINT32 ea = REG_A(m68k)[reg]; REG_A(m68k)[reg] += 12; fpr = load_extended_float80(m68k, ea); break; } case 4: // -(An) { UINT32 ea = REG_A(m68k)[reg]-12; REG_A(m68k)[reg] -= 12; fpr = load_extended_float80(m68k, ea); break; } case 5: // (d16, An) { // FIXME: will fail for fmovem UINT32 ea = EA_AY_DI_32(m68k); fpr = load_extended_float80(m68k, ea); break; } case 6: // (An) + (Xn) + d8 { // FIXME: will fail for fmovem UINT32 ea = EA_AY_IX_32(m68k); fpr = load_extended_float80(m68k, ea); break; } case 7: // extended modes { switch (reg) { case 2: // (d16, PC) { UINT32 ea = EA_PCDI_32(m68k); fpr = load_extended_float80(m68k, ea); } break; case 3: // (d16,PC,Dx.w) { UINT32 ea = EA_PCIX_32(m68k); fpr = load_extended_float80(m68k, ea); } break; default: fatalerror("M68kFPU: READ_EA_FPE: unhandled mode %d, reg %d, at %08X\n", mode, reg, REG_PC(m68k)); break; } } break; default: fatalerror("M68kFPU: READ_EA_FPE: unhandled mode %d, reg %d, at %08X\n", mode, reg, REG_PC(m68k)); break; } return fpr; }
static UINT64 READ_EA_64(m68000_base_device *m68k, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); UINT32 h1, h2; switch (mode) { case 2: // (An) { UINT32 ea = REG_A(m68k)[reg]; h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 3: // (An)+ { UINT32 ea = REG_A(m68k)[reg]; REG_A(m68k)[reg] += 8; h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 4: // -(An) { UINT32 ea = REG_A(m68k)[reg]-8; REG_A(m68k)[reg] -= 8; h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 5: // (d16, An) { UINT32 ea = EA_AY_DI_32(m68k); h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 6: // (An) + (Xn) + d8 { UINT32 ea = EA_AY_IX_32(m68k); h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 7: { switch (reg) { case 1: // (xxx).L { UINT32 d1 = OPER_I_16(m68k); UINT32 d2 = OPER_I_16(m68k); UINT32 ea = (d1 << 16) | d2; return (UINT64)(m68ki_read_32(m68k, ea)) << 32 | (UINT64)(m68ki_read_32(m68k, ea+4)); } case 3: // (PC) + (Xn) + d8 { UINT32 ea = EA_PCIX_32(m68k); h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 4: // #<data> { h1 = OPER_I_32(m68k); h2 = OPER_I_32(m68k); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 2: // (d16, PC) { UINT32 ea = EA_PCDI_32(m68k); h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } default: fatalerror("M68kFPU: READ_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC(m68k)); } break; } default: fatalerror("M68kFPU: READ_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC(m68k)); } return 0; }
static void WRITE_EA_64(m68000_base_device *m68k, int ea, UINT64 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); switch (mode) { case 2: // (An) { UINT32 ea = REG_A(m68k)[reg]; m68ki_write_32(m68k, ea, (UINT32)(data >> 32)); m68ki_write_32(m68k, ea+4, (UINT32)(data)); break; } case 3: // (An)+ { UINT32 ea = REG_A(m68k)[reg]; REG_A(m68k)[reg] += 8; m68ki_write_32(m68k, ea+0, (UINT32)(data >> 32)); m68ki_write_32(m68k, ea+4, (UINT32)(data)); break; } case 4: // -(An) { UINT32 ea; REG_A(m68k)[reg] -= 8; ea = REG_A(m68k)[reg]; m68ki_write_32(m68k, ea+0, (UINT32)(data >> 32)); m68ki_write_32(m68k, ea+4, (UINT32)(data)); break; } case 5: // (d16, An) { UINT32 ea = EA_AY_DI_32(m68k); m68ki_write_32(m68k, ea+0, (UINT32)(data >> 32)); m68ki_write_32(m68k, ea+4, (UINT32)(data)); break; } case 6: // (An) + (Xn) + d8 { UINT32 ea = EA_AY_IX_32(m68k); m68ki_write_32(m68k, ea+0, (UINT32)(data >> 32)); m68ki_write_32(m68k, ea+4, (UINT32)(data)); break; } case 7: { switch (reg) { case 1: // (xxx).L { UINT32 d1 = OPER_I_16(m68k); UINT32 d2 = OPER_I_16(m68k); UINT32 ea = (d1 << 16) | d2; m68ki_write_32(m68k, ea+0, (UINT32)(data >> 32)); m68ki_write_32(m68k, ea+4, (UINT32)(data)); break; } case 2: // (d16, PC) { UINT32 ea = EA_PCDI_32(m68k); m68ki_write_32(m68k, ea+0, (UINT32)(data >> 32)); m68ki_write_32(m68k, ea+4, (UINT32)(data)); break; } default: fatalerror("M68kFPU: WRITE_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC(m68k)); } break; } default: fatalerror("M68kFPU: WRITE_EA_64: unhandled mode %d, reg %d, data %08X%08X at %08X\n", mode, reg, (UINT32)(data >> 32), (UINT32)(data), REG_PC(m68k)); } }