#endif /* DRV_TIMER_M85XX */
struct intrCtlrInputs ppcIntCtlrInputs[] = {
{ 0, "epic", 0, 0 },
};
const struct hcfResource ppcIntCtlr0Resources[] = {
{ VXB_REG_BASE, HCF_RES_INT, { (void *)TRUE} },
{ "input", HCF_RES_ADDR, { (void *)&ppcIntCtlrInputs[0] } },
{ "inputTableSize", HCF_RES_INT, { (void *)NELEMENTS(ppcIntCtlrInputs) } },
};
#define ppcIntCtlr0Num NELEMENTS(ppcIntCtlr0Resources)
#ifdef INCLUDE_EHCI
const struct hcfResource usbEhci0Resources[] = {
{ VXB_REG_BASE, HCF_RES_INT, { (void *)EHCI_CAPLENGTH(USB1_BASE) } },
{ "ehciInit", HCF_RES_ADDR, { (void *)ehci0Init } },
{ "dataSwap", HCF_RES_ADDR, { (void *)vxbSwap32 } },
};
#define usbEhci0Num NELEMENTS(usbEhci0Resources)
const struct hcfResource usbEhci1Resources[] = {
{ VXB_REG_BASE, HCF_RES_INT, { (void *)EHCI_CAPLENGTH(USB2_BASE) } },
{ "ehciInit", HCF_RES_ADDR, { (void *)ehci1Init } },
{ "dataSwap", HCF_RES_ADDR, { (void *)vxbSwap32 } },
};
#define usbEhci1Num NELEMENTS(usbEhci1Resources)
#endif /* INCLUDE_EHCI */
#ifdef DRV_TIMER_OPENPIC
const struct hcfResource openPicTimerDevAresources[] =
static int
ar71xx_ehci_attach(device_t self)
{
struct ar71xx_ehci_softc *isc = device_get_softc(self);
ehci_softc_t *sc = &isc->base;
int err;
int rid;
/* initialise some bus fields */
sc->sc_bus.parent = self;
sc->sc_bus.devices = sc->sc_devices;
sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
sc->sc_bus.dma_bits = 32;
/* get all DMA memory */
if (usb_bus_mem_alloc_all(&sc->sc_bus,
USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
return (ENOMEM);
}
sc->sc_bus.usbrev = USB_REV_2_0;
/* NB: hints fix the memory location and irq */
rid = 0;
sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
if (!sc->sc_io_res) {
device_printf(self, "Could not map memory\n");
goto error;
}
/*
* Craft special resource for bus space ops that handle
* byte-alignment of non-word addresses.
*/
sc->sc_io_tag = ar71xx_bus_space_reversed;
sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
sc->sc_io_size = rman_get_size(sc->sc_io_res);
rid = 0;
sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
RF_ACTIVE | RF_SHAREABLE);
if (sc->sc_irq_res == NULL) {
device_printf(self, "Could not allocate irq\n");
goto error;
}
sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
if (!sc->sc_bus.bdev) {
device_printf(self, "Could not add USB device\n");
goto error;
}
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR);
sprintf(sc->sc_vendor, "Atheros");
err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
NULL, ar71xx_ehci_intr, sc, &sc->sc_intr_hdl);
if (err) {
device_printf(self, "Could not setup irq, %d\n", err);
sc->sc_intr_hdl = NULL;
goto error;
}
/*
* Arrange to force Host mode, select big-endian byte alignment,
* and arrange to not terminate reset operations (the adapter
* will ignore it if we do but might as well save a reg write).
* Also, the controller has an embedded Transaction Translator
* which means port speed must be read from the Port Status
* register following a port enable.
*/
sc->sc_flags = EHCI_SCFLG_SETMODE;
switch (ar71xx_soc) {
case AR71XX_SOC_AR7241:
case AR71XX_SOC_AR7242:
case AR71XX_SOC_AR9130:
case AR71XX_SOC_AR9132:
case AR71XX_SOC_AR9330:
case AR71XX_SOC_AR9331:
case AR71XX_SOC_AR9341:
case AR71XX_SOC_AR9342:
case AR71XX_SOC_AR9344:
case AR71XX_SOC_QCA9533:
case AR71XX_SOC_QCA9533_V2:
case AR71XX_SOC_QCA9556:
case AR71XX_SOC_QCA9558:
sc->sc_flags |= EHCI_SCFLG_TT | EHCI_SCFLG_NORESTERM;
break;
default:
/* fallthrough */
break;
}
/*
* ehci_reset() needs the correct offset to access the host controller
* registers. The AR724x/AR913x offsets aren't 0.
*/
sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
(void) ehci_reset(sc);
err = ehci_init(sc);
if (!err) {
err = device_probe_and_attach(sc->sc_bus.bdev);
}
if (err) {
device_printf(self, "USB init failed err=%d\n", err);
goto error;
}
return (0);
error:
ar71xx_ehci_detach(self);
return (ENXIO);
}
