// --------------------------------------------------
// Initialize external SDRAM memory Micron K4S561632J, 256Mbit(8M x 32)
void Init_SDRAM( void )
{
volatile uint32_t i;
volatile unsigned long Dummy;
EMC_DYN_MEM_Config_Type config;
TIM_TIMERCFG_Type TIM_ConfigStruct;
TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL;
TIM_ConfigStruct.PrescaleValue = 1;
// Set configuration for Tim_config and Tim_MatchConfig
TIM_Init(LPC_TIM0, TIM_TIMER_MODE,&TIM_ConfigStruct);
config.ChipSize = 256;
config.AddrBusWidth = 32;
config.AddrMap = EMC_ADD_MAP_ROW_BANK_COL;
config.CSn = 0;
config.DataWidth = 16;
config.TotalSize = SDRAM_SIZE;
config.CASLatency= 3;
config.RASLatency= 3;
config.Active2ActivePeriod =EMC_NS2CLK( SDRAM_TRC);
config.ActiveBankLatency =EMC_NS2CLK( SDRAM_TRRD);
config.AutoRefrehPeriod = EMC_NS2CLK( SDRAM_TRFC);
config.DataIn2ActiveTime = SDRAM_TDAL + EMC_NS2CLK( SDRAM_TRP);
config.DataOut2ActiveTime = SDRAM_TAPR;
config.WriteRecoveryTime = SDRAM_TWR;
config.ExitSelfRefreshTime = EMC_NS2CLK( SDRAM_TXSR);
config.LoadModeReg2Active = SDRAM_TMRD;
config.PrechargeCmdPeriod = EMC_NS2CLK( SDRAM_TRP);
config.ReadConfig = 1; // Command delayed strategy, using EMCCLKDELAY
config.RefreshTime = EMC_NS2CLK( SDRAM_REFRESH) >> 4;
config.Active2PreChargeTime = EMC_NS2CLK( SDRAM_TRAS);
config.SeftRefreshExitTime = EMC_NS2CLK( SDRAM_TXSR);
DynMem_Init(&config);
EMC_DynCtrlSDRAMInit(EMC_DYNAMIC_CTRL_SDRAM_NOP); // Issue NOP command
TIM_Waitms(100); // wait 200ms
EMC_DynCtrlSDRAMInit(EMC_DYNAMIC_CTRL_SDRAM_PALL); // Issue Pre-charge command
for(i = 0; i < 0x80; i++); // wait 128 AHB clock cycles
TIM_Waitms(100);
EMC_DynCtrlSDRAMInit(EMC_DYNAMIC_CTRL_SDRAM_MODE); // Issue MODE command
Dummy = *((volatile uint32_t *)(SDRAM_BASE_ADDR | (0x32<<13))); // Mode Register Setting
//Timing for 48/60/72MHZ Bus
EMC_DynCtrlSDRAMInit(EMC_DYNAMIC_CTRL_SDRAM_NORMAL); // Issue NORMAL command
//enable buffers
EMC_DynMemConfigB(0, EMC_DYNAMIC_CFG_BUFF_ENABLED);
for(i = 100000; i;i--);
TIM_DeInit(LPC_TIM0);
}
void open1788_sdram_initialize(void)
{
uint32_t regval;
int i;
/* Reconfigure delays:
*
* CMDDLY: Programmable delay value for EMC outputs in command delayed
* mode. The delay amount is roughly CMDDLY * 250 picoseconds.
* FBCLKDLY: Programmable delay value for the feedback clock that controls
* input data sampling. The delay amount is roughly (FBCLKDLY+1) * 250
* picoseconds.
* CLKOUT0DLY: Programmable delay value for the CLKOUT0 output. This would
* typically be used in clock delayed mode. The delay amount is roughly
* (CLKOUT0DLY+1) * 250 picoseconds.
* CLKOUT1DLY: Programmable delay value for the CLKOUT1 output. This would
* typically be used in clock delayed mode. The delay amount is roughly
* (CLKOUT1DLY+1) * 250 picoseconds.
*/
regval = SYSCON_EMCDLYCTL_CMDDLY(32) |
SYSCON_EMCDLYCTL_FBCLKDLY(32) |
SYSCON_EMCDLYCTL_CLKOUT0DLY(1) |
SYSCON_EMCDLYCTL_CLKOUT1DLY(1);
putreg32(regval, LPC17_SYSCON_EMCDLYCTL);
/* Configure the SDRAM */
putreg32( EMC_NS2CLK(20), LPC17_EMC_DYNAMICRP); /* TRP = 20 nS */
putreg32( 15, LPC17_EMC_DYNAMICRAS); /* RAS = 42ns to 100K ns, */
putreg32( 0, LPC17_EMC_DYNAMICSREX); /* TSREX = 1 clock */
putreg32( 1, LPC17_EMC_DYNAMICAPR); /* TAPR = 2 clocks? */
putreg32(EMC_NS2CLK(20) + 2, LPC17_EMC_DYNAMICDAL); /* TDAL = TRP + TDPL = 20ns + 2clk */
putreg32( 1, LPC17_EMC_DYNAMICWR); /* TWR = 2 clocks */
putreg32( EMC_NS2CLK(63), LPC17_EMC_DYNAMICRC); /* H57V2562GTR-75C TRC = 63ns(min)*/
putreg32( EMC_NS2CLK(63), LPC17_EMC_DYNAMICRFC); /* H57V2562GTR-75C TRFC = TRC */
putreg32( 15, LPC17_EMC_DYNAMICXSR); /* Exit self-refresh to active */
putreg32( EMC_NS2CLK(63), LPC17_EMC_DYNAMICRRD); /* 3 clock, TRRD = 15ns (min) */
putreg32( 1, LPC17_EMC_DYNAMICMRD); /* 2 clock, TMRD = 2 clocks (min) */
/* Command delayed strategy, using EMCCLKDELAY */
putreg32(EMC_DYNAMICREADCONFIG_RD_CMD, LPC17_EMC_DYNAMICREADCONFIG);
/* H57V2562GTR-75C: TCL=3CLK, TRCD = 20ns(min), 3 CLK = 24ns */
putreg32(MDKCFG_RASCAS0VAL, LPC17_EMC_DYNAMICRASCAS0);
#ifdef CONFIG_LPC17_SDRAM_16BIT
/* For Manley lpc1778 SDRAM: H57V2562GTR-75C, 256Mb, 16Mx16, 4 banks, row=13, column=9:
*
* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC
*/
putreg32(EMC_DYNAMICCONFIG_MD_SDRAM | EMC_DYNAMICCONFIG_AM0(13),
LPC17_EMC_DYNAMICCONFIG0);
#elif defined CONFIG_LPC17_SDRAM_32BIT
/* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */
putreg32(EMC_DYNAMICCONFIG_MD_SDRAM | EMC_DYNAMICCONFIG_AM0(13) | EMC_DYNAMICCONFIG_AM1,
LPC17_EMC_DYNAMICCONFIG0);
#endif
up_mdelay(100);
/* Issue NOP command */
putreg32(EMC_DYNAMICCONTROL_CE | EMC_DYNAMICCONTROL_CS | EMC_DYNAMICCONTROL_I_NOP,
LPC17_EMC_DYNAMICCONTROL);
/* Wait 200 Msec */
up_mdelay(200);
/* Issue PALL command */
putreg32(EMC_DYNAMICCONTROL_CE | EMC_DYNAMICCONTROL_CS | EMC_DYNAMICCONTROL_I_PALL,
LPC17_EMC_DYNAMICCONTROL);
putreg32(2, LPC17_EMC_DYNAMICREFRESH); /* ( n * 16 ) -> 32 clock cycles */
/* Wait 128 AHB clock cycles */
for (i = 0; i < 128; i++);
/* 64ms/8192 = 7.8125us, nx16x8.33ns < 7.8125us, n < 58.6*/
regval = 64000000 / (1 << 13);
regval -= 16;
regval >>= 4;
regval = regval * LPC17_EMCCLK_MHZ / 1000;
putreg32(regval, LPC17_EMC_DYNAMICREFRESH);
/* Issue MODE command */
putreg32(EMC_DYNAMICCONTROL_CE | EMC_DYNAMICCONTROL_CS | EMC_DYNAMICCONTROL_I_MODE,
LPC17_EMC_DYNAMICCONTROL);
#ifdef CONFIG_LPC17_SDRAM_16BIT
(void)getreg16(SDRAM_BASE | (0x33 << 12)); /* 8 burst, 3 CAS latency */
#elif defined CONFIG_LPC17_SDRAM_32BIT
(void)getreg32(SDRAM_BASE | (0x32 << 13)); /* 4 burst, 3 CAS latency */
#endif
/* Issue NORMAL command */
putreg32(EMC_DYNAMICCONTROL_I_NORMAL, LPC17_EMC_DYNAMICCONTROL);
/* Enable buffer */
regval = getreg32(LPC17_EMC_DYNAMICCONFIG0);
regval |= EMC_DYNAMICCONFIG_B;
putreg32(regval, LPC17_EMC_DYNAMICCONFIG0);
up_mdelay(12);
regval = getreg32(LPC17_SYSCON_EMCDLYCTL);
regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK;
regval |= SYSCON_EMCDLYCTL_CMDDLY(18);
putreg32(regval, LPC17_SYSCON_EMCDLYCTL);
}
/*********************************************************************//**
* @brief Initialize external SDRAM memory Micron sdram_h57v2562gtr
* 256Mbit(16M x 16)
* @param[in] None
* @return None
**********************************************************************/
void SDRAMInit( void )
{
volatile uint32_t i;
volatile unsigned long Dummy;
TIM_TIMERCFG_Type TIM_ConfigStruct;
TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL;
TIM_ConfigStruct.PrescaleValue = 1;
// Set configuration for Tim_config and Tim_MatchConfig
TIM_Init(LPC_TIM0, TIM_TIMER_MODE,&TIM_ConfigStruct);
/* Enable External Memory Controller power/clock */
LPC_SC->PCONP |= 0x00000800;
LPC_SC->EMCDLYCTL = 0x00001010;
LPC_EMC->Control = 0x00000001;
LPC_EMC->Config = 0x00000000;
SDRAM_GPIO_Config();
LPC_SC->EMCCLKSEL=1;
LPC_EMC->DynamicRP=EMC_NS2CLK(SDRAM_TRP); /* 20ns, */
LPC_EMC->DynamicRAS = EMC_NS2CLK(SDRAM_TRAS); /* 42ns to 100K ns, */
LPC_EMC->DynamicSREX = 1 - 1; /* tSRE, 1clk, */
LPC_EMC->DynamicAPR = SDRAM_TAPR - 1; /* Not found!!! Estimated as 2clk, */
LPC_EMC->DynamicDAL = EMC_NS2CLK(SDRAM_TRP) + 2; /* tDAL = tRP + tDPL = 20ns + 2clk */
LPC_EMC->DynamicWR = SDRAM_TWR - 1; /* 2CLK, */
LPC_EMC->DynamicRC = EMC_NS2CLK(63); /* H57V2562GTR-75C tRC=63ns(min)*/
LPC_EMC->DynamicRFC = EMC_NS2CLK(63); /* H57V2562GTR-75C tRFC=tRC */
LPC_EMC->DynamicXSR = SDRAM_TXSR-1; /* exit self-refresh to active*/
LPC_EMC->DynamicRRD = EMC_NS2CLK(63); /* 3clk, tRRD=15ns(min) */
LPC_EMC->DynamicMRD = SDRAM_TMRD - 1; /* 2clk, tMRD=2clk(min) */
LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
/* H57V2562GTR-75C: tCL=3CLK, tRCD=20ns(min), 3 CLK=24ns */
LPC_EMC->DynamicRasCas0 = 0x303;
LPC_EMC->DynamicConfig0 = 0x680;
TIM_Waitms(100);
LPC_EMC->DynamicControl = 0x00000183; /* Issue NOP command */
TIM_Waitms(200); /* wait 200ms */
LPC_EMC->DynamicControl = 0x00000103; /* Issue PALL command */
LPC_EMC->DynamicRefresh = 0x00000002; /* ( n * 16 ) -> 32 clock cycles */
for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */
/* 64ms/8192=7.8125us, nx16x8.33ns<7.8125us, n<58.6*/
LPC_EMC->DynamicRefresh = EMC_SDRAM_REFRESH(64);
LPC_EMC->DynamicControl = 0x00000083; /* Issue MODE command */
Dummy = *((volatile uint16_t *)(SDRAM_BASE_ADDR | (0x33<<12))); /* 8 burst, 3 CAS latency */
LPC_EMC->DynamicControl = 0x00000000; /* Issue NORMAL command */
LPC_EMC->DynamicConfig0 |= 0x80000; /* enable buffer */
TIM_Waitms(1);
TIM_DeInit(LPC_TIM0);
}
