static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev) { A_STATUS status; A_UINT8 error_int_status; A_UINT8 regBuffer[4]; AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error Interrupt\n")); error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F; AR_DEBUG_ASSERT(error_int_status); AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", error_int_status)); if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) { /* Wakeup */ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n")); } if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) { /* Rx Underflow */ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n")); if (pDev->TargetFailureCallback != NULL) { pDev->TargetFailureCallback(pDev->HTCContext, AR6K_TARGET_RX_ERROR); } } if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) { /* Tx Overflow */ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n")); if (pDev->TargetFailureCallback != NULL) { pDev->TargetFailureCallback(pDev->HTCContext, AR6K_TARGET_TX_ERROR); } } /* Clear the interrupt */ pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */ /* set up the register transfer buffer to hit the register 4 times , this is done * to make the access 4-byte aligned to mitigate issues with host bus interconnects that * restrict bus transfer lengths to be a multiple of 4-bytes */ /* set W1C value to clear the interrupt, this hits the register first */ regBuffer[0] = error_int_status; /* the remaining 4 values are set to zero which have no-effect */ regBuffer[1] = 0; regBuffer[2] = 0; regBuffer[3] = 0; status = HIFReadWrite(pDev->HIFDevice, ERROR_INT_STATUS_ADDRESS, regBuffer, 4, HIF_WR_SYNC_BYTE_FIX, NULL); AR_DEBUG_ASSERT(status == A_OK); return status; }
void htcServiceErrorInterrupt(HTC_TARGET *target) { A_STATUS status; A_UINT32 address; HIF_REQUEST request; A_UINT8 error_int_status; HTC_DEBUG_PRINTF(ATH_LOG_INF, "Error Interrupt\n"); error_int_status = target->table.error_int_status & target->table.error_status_enable; AR_DEBUG_ASSERT(error_int_status); HTC_DEBUG_PRINTF(ATH_LOG_INF, "Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", error_int_status); if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) { /* Wakeup */ HTC_DEBUG_PRINTF(ATH_LOG_INF, "Wakeup\n"); } if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) { /* Rx Underflow */ HTC_DEBUG_PRINTF(ATH_LOG_INF, "Rx Underflow\n"); } if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) { /* Tx Overflow */ HTC_DEBUG_PRINTF(ATH_LOG_INF, "Tx Overflow\n"); } /* Clear the interrupt */ target->table.error_int_status = error_int_status; /* W1C */ HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_SYNCHRONOUS, HIF_BYTE_BASIS, HIF_FIXED_ADDRESS); address = getRegAddr(ERROR_INT_STATUS_REG, ENDPOINT_UNUSED); status = HIFReadWrite(target->device, address, &target->table.error_int_status, 1, &request, NULL); AR_DEBUG_ASSERT(status == A_OK); }