uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance)
{
uint_fast8_t intStatus = UART_getInterruptStatus(moduleInstance,
EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG);
uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->IE;
if (!(intEnabled & EUSCI_A_UART_RECEIVE_INTERRUPT))
{
intStatus &= ~EUSCI_A_UART_RECEIVE_INTERRUPT;
}
if (!(intEnabled & EUSCI_A_UART_TRANSMIT_INTERRUPT))
{
intStatus &= ~EUSCI_A_UART_TRANSMIT_INTERRUPT;
}
intEnabled = EUSCI_A_CMSIS(moduleInstance)->CTLW0;
if (!(intEnabled & EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT))
{
intStatus &= ~EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT;
}
if (!(intEnabled & EUSCI_A_UART_BREAKCHAR_INTERRUPT))
{
intStatus &= ~EUSCI_A_UART_BREAKCHAR_INTERRUPT;
}
return intStatus;
}
void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
{
uint_fast8_t locMask;
ASSERT(
!(mask
& ~(EUSCI_A_UART_RECEIVE_INTERRUPT
| EUSCI_A_UART_TRANSMIT_INTERRUPT
| EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
| EUSCI_A_UART_BREAKCHAR_INTERRUPT
| EUSCI_A_UART_STARTBIT_INTERRUPT
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));
locMask = (mask
& (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
| EUSCI_A_UART_STARTBIT_INTERRUPT
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
EUSCI_A_CMSIS(moduleInstance)->IE |= locMask;
locMask = (mask
& (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
| EUSCI_A_UART_BREAKCHAR_INTERRUPT));
EUSCI_A_CMSIS(moduleInstance)->CTLW0 |= locMask;
}
//*****************************************************************************
//
//! \brief Initializes the SPI Slave block.
//!
//! Upon successful initialization of the SPI slave block, this function will
//! have initailized the slave block, but the SPI Slave block still remains
//! disabled and must be enabled with EUSCI_A_SPI_enable()
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI Slave module.
//! \param msbFirst controls the direction of the receive and transmit shift
//! register.
//! Valid values are:
//! - \b EUSCI_A_SPI_MSB_FIRST
//! - \b EUSCI_A_SPI_LSB_FIRST [Default]
//! \param clockPhase is clock phase select.
//! Valid values are:
//! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
//! [Default]
//! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
//! \param clockPolarity is clock polarity select
//! Valid values are:
//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
//! \param spiMode is SPI mode select
//! Valid values are:
//! - \b EUSCI_A_SPI_3PIN
//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
//!
//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b
//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return STATUS_SUCCESS
//
//*****************************************************************************
bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode)
{
ASSERT(
(EUSCI_A_SPI_MSB_FIRST == msbFirst)
|| (EUSCI_A_SPI_LSB_FIRST == msbFirst));
ASSERT(
(EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== clockPhase)
|| (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== clockPhase));
ASSERT(
(EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
|| (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== clockPolarity));
ASSERT(
(EUSCI_A_SPI_3PIN == spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
//Disable USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
//Reset OFS_UCAxCTLW0 register
EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
& ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
| (clockPhase + clockPolarity + msbFirst + UCSYNC + spiMode);
return true;
}
void UART_transmitAddress(uint32_t moduleInstance, uint_fast8_t transmitAddress)
{
/* Set UCTXADDR bit */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXADDR_OFS) = 1;
/* Place next byte to be sent into the transmit buffer */
EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitAddress;
}
uint8_t UART_receiveData(uint32_t moduleInstance)
{
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__RXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_RXIFG_OFS))
;
return EUSCI_A_CMSIS(moduleInstance)->RXBUF;
}
void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
{
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__TXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
;
EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitData;
}
//*****************************************************************************
//
//! \brief Selects 4Pin Functionality
//!
//! This function should be invoked only in 4-wire mode. Invoking this function
//! has no effect in 3-wire mode.
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI module.
//! \param select4PinFunctionality selects 4 pin functionality
//! Valid values are:
//! - \b EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
//! - \b EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
//!
//! Modified bits are \b UCSTEM of \b UCAxCTLW0 register.
//!
//! \return None
//
//*****************************************************************************
void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress,
uint8_t select4PinFunctionality)
{
ASSERT(
(EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
== select4PinFunctionality)
|| (EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
== select4PinFunctionality));
EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
& ~UCSTEM) | select4PinFunctionality;
}
//*****************************************************************************
//
//! \brief Initializes the SPI Master clock. At the end of this function call,
//! SPI module is left enabled.
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI module.
//! \param clockSourceFrequency is the frequency of the slected clock source
//! \param desiredSpiClock is the desired clock rate for SPI communication
//!
//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return None
//
//*****************************************************************************
void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,
uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
{
//Disable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
EUSCI_A_CMSIS(baseAddress)->rBRW = (uint16_t) (clockSourceFrequency
/ desiredSpiClock);
//Reset the UCSWRST bit to enable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
}
void UART_selectDeglitchTime(uint32_t moduleInstance, uint32_t deglitchTime)
{
ASSERT(
(EUSCI_A_UART_DEGLITCH_TIME_2ns == deglitchTime)
|| (EUSCI_A_UART_DEGLITCH_TIME_50ns == deglitchTime)
|| (EUSCI_A_UART_DEGLITCH_TIME_100ns == deglitchTime)
|| (EUSCI_A_UART_DEGLITCH_TIME_200ns == deglitchTime));
EUSCI_A_CMSIS(moduleInstance)->CTLW1 =
(EUSCI_A_CMSIS(moduleInstance)->CTLW1 & ~(EUSCI_A_CTLW1_GLIT_MASK))
| deglitchTime;
}
//*****************************************************************************
//
//! \brief Clears the selected SPI interrupt status flag.
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI module.
//! \param mask is the masked interrupt flag to be cleared.
//! Mask value is the logical OR of any of the following:
//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
//!
//! Modified bits of \b UCAxIFG register.
//!
//! \return None
//
//*****************************************************************************
void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
{
ASSERT(
!(mask
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
EUSCI_A_CMSIS(baseAddress)->rIFG.r &= ~mask;
}
//*****************************************************************************
//
//! \brief Gets the current SPI interrupt status.
//!
//! This returns the interrupt status for the SPI module based on which flag is
//! passed.
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI module.
//! \param mask is the masked interrupt flag status to be returned.
//! Mask value is the logical OR of any of the following:
//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
//!
//! \return Logical OR of any of the following:
//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
//! \n indicating the status of the masked interrupts
//
//*****************************************************************************
uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
{
ASSERT(
!(mask
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
return EUSCI_A_CMSIS(baseAddress)->rIFG.r & mask;
}
//*****************************************************************************
//
//! \brief Disables individual SPI interrupt sources.
//!
//! Disables the indicated SPI interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI module.
//! \param mask is the bit mask of the interrupt sources to be disabled.
//! Mask value is the logical OR of any of the following:
//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
//!
//! Modified bits of \b UCAxIE register.
//!
//! \return None
//
//*****************************************************************************
void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
{
ASSERT(
!(mask
& ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
| EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
EUSCI_A_CMSIS(baseAddress)->rIE.r &= ~mask;
}
uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, uint8_t mask)
{
ASSERT(
!(mask
& ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
| EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
| EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
return EUSCI_A_CMSIS(moduleInstance)->IFG & mask;
}
void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
{
ASSERT(
!(mask
& ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
| EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
| EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
//Clear the UART interrupt source.
EUSCI_A_CMSIS(moduleInstance)->IFG &= ~(mask);
}
uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance, uint_fast8_t mask)
{
ASSERT(
0x00 != mask
&& (EUSCI_A_UART_LISTEN_ENABLE + EUSCI_A_UART_FRAMING_ERROR
+ EUSCI_A_UART_OVERRUN_ERROR
+ EUSCI_A_UART_PARITY_ERROR
+ EUSCI_A_UART_BREAK_DETECT
+ EUSCI_A_UART_RECEIVE_ERROR
+ EUSCI_A_UART_ADDRESS_RECEIVED
+ EUSCI_A_UART_IDLELINE + EUSCI_A_UART_BUSY));
return EUSCI_A_CMSIS(moduleInstance)->STATW & mask;
}
//*****************************************************************************
//
//! \brief Changes the SPI colock phase and polarity. At the end of this
//! function call, SPI module is left enabled.
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI module.
//! \param clockPhase is clock phase select.
//! Valid values are:
//! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
//! [Default]
//! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
//! \param clockPolarity is clock polarity select
//! Valid values are:
//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
//!
//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0
//! register.
//!
//! \return None
//
//*****************************************************************************
void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress,
uint16_t clockPhase, uint16_t clockPolarity)
{
ASSERT(
(EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
|| (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== clockPolarity));
ASSERT(
(EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== clockPhase)
|| (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== clockPhase));
//Disable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
& ~(UCCKPH + UCCKPL)) | (clockPhase + clockPolarity);
//Reset the UCSWRST bit to enable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
}
uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance)
{
if (is_A_Module(moduleInstance))
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
& EUSCI_A_CMSIS(moduleInstance)->IE;
} else
{
return SPI_getInterruptStatus(moduleInstance,
EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
& EUSCI_B_CMSIS(moduleInstance)->IE;
}
}
void UART_transmitBreak(uint32_t moduleInstance)
{
/* Set UCTXADDR bit */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXBRK_OFS) = 1;
/* If current mode is automatic baud-rate detection */
if (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
== (EUSCI_A_CMSIS(moduleInstance)->CTLW0
& EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))
EUSCI_A_CMSIS(moduleInstance)->TXBUF =
EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC;
else
EUSCI_A_CMSIS(moduleInstance)->TXBUF = DEFAULT_SYNC;
/* If interrupts are not used, poll for flags */
if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A__TXIE_OFS))
while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
;
}
bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
{
bool retVal = true;
ASSERT(
(EUSCI_A_UART_MODE == config->uartMode)
|| (EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE
== config->uartMode)
|| (EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE
== config->uartMode)
|| (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
== config->uartMode));
ASSERT(
(EUSCI_A_UART_CLOCKSOURCE_ACLK == config->selectClockSource)
|| (EUSCI_A_UART_CLOCKSOURCE_SMCLK
== config->selectClockSource));
ASSERT(
(EUSCI_A_UART_MSB_FIRST == config->msborLsbFirst)
|| (EUSCI_A_UART_LSB_FIRST == config->msborLsbFirst));
ASSERT(
(EUSCI_A_UART_ONE_STOP_BIT == config->numberofStopBits)
|| (EUSCI_A_UART_TWO_STOP_BITS == config->numberofStopBits));
ASSERT(
(EUSCI_A_UART_NO_PARITY == config->parity)
|| (EUSCI_A_UART_ODD_PARITY == config->parity)
|| (EUSCI_A_UART_EVEN_PARITY == config->parity));
/* Disable the USCI Module */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/* Clock source select */
EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_A_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_A_CTLW0_SSEL_MASK)
| config->selectClockSource;
/* MSB, LSB select */
if (config->msborLsbFirst)
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 1;
else
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 0;
/* UCSPB = 0(1 stop bit) OR 1(2 stop bits) */
if (config->numberofStopBits)
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 1;
else
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 0;
/* Parity */
switch (config->parity)
{
case EUSCI_A_UART_NO_PARITY:
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 0;
break;
case EUSCI_A_UART_ODD_PARITY:
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 0;
break;
case EUSCI_A_UART_EVEN_PARITY:
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 1;
break;
}
/* BaudRate Control Register */
EUSCI_A_CMSIS(moduleInstance)->BRW = config->clockPrescalar;
EUSCI_A_CMSIS(moduleInstance)->MCTLW = ((config->secondModReg << 8)
+ (config->firstModReg << 4) + config->overSampling);
/* Asynchronous mode & 8 bit character select & clear mode */
EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_A_CMSIS(moduleInstance)->CTLW0
& ~(EUSCI_A_CTLW0_SYNC | EUSCI_A_CTLW0_SEVENBIT | EUSCI_A_CTLW0_MODE_3 | EUSCI_A_CTLW0_RXEIE | EUSCI_A_CTLW0_BRKIE | EUSCI_A_CTLW0_DORM
| EUSCI_A_CTLW0_TXADDR | EUSCI_A_CTLW0_TXBRK)) | config->uartMode;
return retVal;
}
//*****************************************************************************
//
//! \brief Transmits a byte from the SPI Module.
//!
//! This function will place the supplied data into SPI trasmit data register
//! to start transmission.
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI module.
//! \param transmitData data to be transmitted from the SPI module
//!
//! \return None
//
//*****************************************************************************
void EUSCI_A_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
{
EUSCI_A_CMSIS(baseAddress)->rTXBUF.r = transmitData;
}
//*****************************************************************************
//
//! \brief Receives a byte that has been sent to the SPI Module.
//!
//! This function reads a byte of data from the SPI receive data Register.
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI module.
//!
//! \return Returns the byte received from by the SPI module, cast as an
//! uint8_t.
//
//*****************************************************************************
uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress)
{
return EUSCI_A_CMSIS(baseAddress)->rRXBUF.r;
}
//*****************************************************************************
//
//! \brief Enables the SPI block.
//!
//! This will enable operation of the SPI block.
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI module.
//!
//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return None
//
//*****************************************************************************
void EUSCI_A_SPI_enable(uint32_t baseAddress)
{
//Reset the UCSWRST bit to enable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
}
//*****************************************************************************
//
//! \brief Disables the SPI block.
//!
//! This will disable operation of the SPI block.
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI module.
//!
//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
//!
//! \return None
//
//*****************************************************************************
void EUSCI_A_SPI_disable(uint32_t baseAddress)
{
//Set the UCSWRST bit to disable the USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
}
//*****************************************************************************
//
//! \brief Indicates whether or not the SPI bus is busy.
//!
//! This function returns an indication of whether or not the SPI bus is
//! busy.This function checks the status of the bus via UCBBUSY bit
//!
//! \param baseAddress is the base address of the EUSCI_A_SPI module.
//!
//! \return true if busy, false otherwise
//*****************************************************************************
bool EUSCI_A_SPI_isBusy(uint32_t baseAddress)
{
//Return the bus busy status.
return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rSTATW.r, UCBBUSY_OFS);
}
uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
{
return (uint32_t)&EUSCI_A_CMSIS(moduleInstance)->RXBUF;
}
bool SPI_initSlave(uint32_t moduleInstance, const eUSCI_SPI_SlaveConfig *config)
{
if (is_A_Module(moduleInstance))
{
ASSERT(
(EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
|| (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
ASSERT(
(EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== config->clockPhase)
|| (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== config->clockPhase));
ASSERT(
(EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
== config->clockPolarity)
|| (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== config->clockPolarity));
ASSERT(
(EUSCI_A_SPI_3PIN == config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
== config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable USCI Module
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
//Reset OFS_UCAxCTLW0 register
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
| (config->clockPhase + config->clockPolarity
+ config->msbFirst + UCSYNC + config->spiMode);
return true;
} else
{
ASSERT(
(EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
|| (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
ASSERT(
(EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== config->clockPhase)
|| (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== config->clockPhase));
ASSERT(
(EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
== config->clockPolarity)
|| (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== config->clockPolarity));
ASSERT(
(EUSCI_B_SPI_3PIN == config->spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
== config->spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
//Reset OFS_UCBxCTLW0 register
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
| (config->clockPhase + config->clockPolarity
+ config->msbFirst + UCSYNC + config->spiMode);
return true;
}
}
void UART_resetDormant(uint32_t moduleInstance)
{
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 0;
}
bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config)
{
if (is_A_Module(moduleInstance))
{
ASSERT(
(EUSCI_A_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
|| (EUSCI_A_SPI_CLOCKSOURCE_SMCLK
== config->selectClockSource));
ASSERT(
(EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
|| (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
ASSERT(
(EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== config->clockPhase)
|| (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== config->clockPhase));
ASSERT(
(EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
== config->clockPolarity)
|| (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== config->clockPolarity));
ASSERT(
(EUSCI_A_SPI_3PIN == config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
== config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
* UCMST = Master mode
* UCSYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
+ UCMODE_3 + UCSYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
+ UCMST + UCSYNC + config->spiMode);
EUSCI_A_CMSIS(moduleInstance)->rBRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
//No modulation
EUSCI_A_CMSIS(moduleInstance)->rMCTLW.r = 0;
return true;
} else
{
ASSERT(
(EUSCI_B_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
|| (EUSCI_B_SPI_CLOCKSOURCE_SMCLK
== config->selectClockSource));
ASSERT(
(EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
|| (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
ASSERT(
(EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== config->clockPhase)
|| (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== config->clockPhase));
ASSERT(
(EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
== config->clockPolarity)
|| (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== config->clockPolarity));
ASSERT(
(EUSCI_B_SPI_3PIN == config->spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
== config->spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
* UCMST = Master mode
* UCSYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
& ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
+ UCMODE_3 + UCSYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
+ UCMST + UCSYNC + config->spiMode);
EUSCI_B_CMSIS(moduleInstance)->rBRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
return true;
}
}
void UART_disableModule(uint32_t moduleInstance)
{
/* Set the UCSWRST bit to disable the USCI Module */
BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
}
bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config)
{
/* Returning false if we are not divisible */
if((config->clockSourceFrequency
% config->desiredSpiClock) != 0)
{
return false;
}
if (is_A_Module(moduleInstance))
{
ASSERT(
(EUSCI_A_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
|| (EUSCI_A_SPI_CLOCKSOURCE_SMCLK
== config->selectClockSource));
ASSERT(
(EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
|| (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
ASSERT(
(EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== config->clockPhase)
|| (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== config->clockPhase));
ASSERT(
(EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
== config->clockPolarity)
|| (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== config->clockPolarity));
ASSERT(
(EUSCI_A_SPI_3PIN == config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
== config->spiMode)
|| (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
* EUSCI_A_CTLW0_MST = Master mode
* EUSCI_A_CTLW0_SYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_A_CMSIS(moduleInstance)->CTLW0
& ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
+ EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
+ EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
EUSCI_A_CMSIS(moduleInstance)->BRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
//No modulation
EUSCI_A_CMSIS(moduleInstance)->MCTLW = 0;
return true;
} else
{
ASSERT(
(EUSCI_B_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
|| (EUSCI_B_SPI_CLOCKSOURCE_SMCLK
== config->selectClockSource));
ASSERT(
(EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
|| (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
ASSERT(
(EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
== config->clockPhase)
|| (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
== config->clockPhase));
ASSERT(
(EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
== config->clockPolarity)
|| (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
== config->clockPolarity));
ASSERT(
(EUSCI_B_SPI_3PIN == config->spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
== config->spiMode)
|| (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
== config->spiMode));
//Disable the USCI Module
BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
/*
* Configure as SPI master mode.
* Clock phase select, polarity, msb
* EUSCI_A_CTLW0_MST = Master mode
* EUSCI_A_CTLW0_SYNC = Synchronous mode
* UCMODE_0 = 3-pin SPI
*/
EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
(EUSCI_B_CMSIS(moduleInstance)->CTLW0
& ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
+ EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
| (config->selectClockSource + config->msbFirst
+ config->clockPhase + config->clockPolarity
+ EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
EUSCI_B_CMSIS(moduleInstance)->BRW =
(uint16_t) (config->clockSourceFrequency
/ config->desiredSpiClock);
return true;
}
}
