static void init_pa7_dsm2()
{
EXTERNAL_RF_ON();
// configure_pins( PIN_EXTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_3 | PIN_OS25 | PIN_PUSHPULL ) ;
// Timer8
setupPulsesDsm2(6) ;
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
#if defined(REV3)
configure_pins( PIN_INTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25 | PIN_PUSHPULL ) ;
#else
configure_pins( PIN_EXTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_3 | PIN_OS25 | PIN_PUSHPULL ) ;
#endif
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN ; // Enable clock
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN ; // Enable DMA2 clock
TIM8->CR1 &= ~TIM_CR1_CEN ;
TIM8->ARR = 44000 ; // 22mS
TIM8->CCR2 = 40000 ; // Update time
TIM8->PSC = (PeripheralSpeeds.Peri2_frequency * PeripheralSpeeds.Timer_mult2) / 2000000 - 1 ; // 0.5uS from 30MHz
#if defined(REV3)
TIM8->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P ;
#else
#ifdef PCB9XT
TIM8->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ;
#else
TIM8->CCER = TIM_CCER_CC1NE ;
#endif
#endif
TIM8->CR2 = TIM_CR2_OIS1 ; // O/P idle high
TIM8->BDTR = TIM_BDTR_MOE ; // Enable outputs
TIM8->CCR1 = dsm2Stream[0] ;
TIM8->CCMR1 = TIM_CCMR1_OC1M_2 ; // Force O/P low, hardware inverts it
TIM8->EGR = 1 ; // Restart
// TIM8->SR &= ~TIM_SR_UIF ; // Clear flag
// TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
TIM8->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match
TIM8->DCR = 13 ; // DMA to CC1
// TIM8->CR1 = TIM_CR1_OPM ; // Just run once
// Enable the DMA channel here, DMA2 stream 2, channel 7
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
DMA2_Stream2->PAR = CONVERT_PTR(&TIM8->DMAR);
DMA2_Stream2->M0AR = CONVERT_PTR(&dsm2Stream[1]);
// DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
// DMA2_Stream2->NDTR = 100 ;
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
TIM8->CR1 |= TIM_CR1_CEN ;
NVIC_SetPriority( TIM8_CC_IRQn, 3 ) ; // Lower priority interrupt
NVIC_EnableIRQ(TIM8_CC_IRQn) ;
}
static void init_pa7_assan()
{
x9dSPortInit( 115200, SPORT_MODE_HARDWARE, 0, 0 ) ;
EXTERNAL_RF_ON();
setupPulsesDsm2(6) ;
configure_pins( PIN_EXTPPM_OUT, PIN_INPUT | PIN_PORTA ) ;
// configure_pins( PIN_EXTPPM_OUT, PIN_OUTPUT | PIN_PUSHPULL | PIN_OS25 | PIN_PORTA ) ;
// GPIO_SetBits(GPIOA, PIN_EXTPPM_OUT) ; // Set high
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN ; // Enable clock
TIM8->CR1 &= ~TIM_CR1_CEN ;
TIM8->ARR = 22000 ; // 11mS
TIM8->CCR2 = 19000 ; // Update time
TIM8->CCR1 = 10000 ; // Tx back on time
TIM8->CCR3 = 1936*2 ; // Tx hold on until time
TIM8->PSC = (PeripheralSpeeds.Peri2_frequency * PeripheralSpeeds.Timer_mult2) / 2000000 - 1 ; // 0.5uS from 30MHz
#if defined(REV3)
TIM8->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P ;
#else
TIM8->CCER = TIM_CCER_CC1NE ;
#endif
TIM8->EGR = 0 ; // Restart
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
TIM8->DIER |= TIM_DIER_CC2IE | TIM_DIER_CC1IE | TIM_DIER_CC3IE ; // Enable these interrupts
TIM8->DIER |= TIM_DIER_UIE ;
TIM8->CR1 |= TIM_CR1_CEN ;
NVIC_SetPriority( TIM8_CC_IRQn, 3 ) ; // Lower priority interrupt
NVIC_SetPriority( TIM8_UP_TIM13_IRQn, 3 ) ; // Lower priority interrupt
NVIC_EnableIRQ(TIM8_CC_IRQn) ;
NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn) ;
}
// PPM output
// Timer 1, channel 1 on PA8 for prototype
// Pin is AF1 function for timer 1
static void init_pa7_ppm()
{
EXTERNAL_RF_ON();
// Timer1
// setupPulsesPpmx() ;
ppmStreamPtr[EXTERNAL_MODULE] = ppmStream[EXTERNAL_MODULE];
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
#if defined(REV3)
configure_pins( 0x0100, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25 | PIN_PUSHPULL ) ;
#else
configure_pins( PIN_EXTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_3 | PIN_OS25 | PIN_PUSHPULL ) ;
#endif
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN ; // Enable clock
TIM8->CR1 &= ~TIM_CR1_CEN ;
TIM8->ARR = *ppmStreamPtr[EXTERNAL_MODULE]++ ;
TIM8->PSC = (PeripheralSpeeds.Peri2_frequency * PeripheralSpeeds.Timer_mult2) / 2000000 - 1 ; // 0.5uS from 30MHz
#if defined(REV3)
TIM8->CCER = TIM_CCER_CC1E ;
#else
#ifdef PCB9XT
TIM8->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ;
#else
TIM8->CCER = TIM_CCER_CC1NE ;
#endif
if(!g_model.xpulsePol)
#ifdef PCB9XT
TIM8->CCER &= ~TIM_CCER_CC1NP ;
#else
TIM8->CCER |= TIM_CCER_CC1NP;
#endif
#endif
TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE ; // PWM mode 1
TIM8->CCR1 = (g_model.xppmDelay*50+300)*2 ;
TIM8->BDTR = TIM_BDTR_MOE ;
TIM8->EGR = 1 ;
TIM8->DIER = TIM_DIER_UDE ;
TIM8->SR &= ~TIM_SR_UIF ; // Clear flag
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
TIM8->DIER |= TIM_DIER_CC2IE ;
TIM8->DIER |= TIM_DIER_UIE ;
TIM8->CR1 = TIM_CR1_CEN ;
NVIC_SetPriority( TIM8_CC_IRQn, 3 ) ; // Lower priority interrupt
NVIC_SetPriority( TIM8_UP_TIM13_IRQn, 3 ) ; // Lower priority interrupt
NVIC_EnableIRQ(TIM8_CC_IRQn) ;
NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn) ;
}
// PPM output
// Timer 1, channel 1 on PA8 for prototype
// Pin is AF1 function for timer 1
static void init_pa7_ppm()
{
EXTERNAL_RF_ON();
// Timer1
setupPulsesPPM(EXTERNAL_MODULE) ;
ppmStreamPtr[EXTERNAL_MODULE] = ppmStream[EXTERNAL_MODULE];
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
#if defined(REV3)
configure_pins( 0x0100, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25 | PIN_PUSHPULL ) ;
#else
configure_pins( PIN_EXTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_3 | PIN_OS25 | PIN_PUSHPULL ) ;
#endif
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN ; // Enable clock
TIM8->CR1 &= ~TIM_CR1_CEN ;
TIM8->ARR = *ppmStreamPtr[EXTERNAL_MODULE]++ ;
TIM8->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
#if defined(REV3)
TIM8->CCER = TIM_CCER_CC1E ;
#else
TIM8->CCER = TIM_CCER_CC1NE;
if(!g_model.moduleData[EXTERNAL_MODULE].ppmPulsePol)
TIM8->CCER |= TIM_CCER_CC1NP;
#endif
TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE ; // PWM mode 1
TIM8->CCR1 = (g_model.moduleData[EXTERNAL_MODULE].ppmDelay*50+300)*2;
TIM8->BDTR = TIM_BDTR_MOE ;
TIM8->EGR = 1 ;
TIM8->DIER = TIM_DIER_UDE ;
TIM8->SR &= ~TIM_SR_UIF ; // Clear flag
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
TIM8->DIER |= TIM_DIER_CC2IE ;
TIM8->DIER |= TIM_DIER_UIE ;
TIM8->CR1 = TIM_CR1_CEN ;
NVIC_EnableIRQ(TIM8_CC_IRQn) ;
NVIC_SetPriority(TIM8_CC_IRQn, 7);
NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn) ;
NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 7);
}
static void init_pa7_dsm2()
{
EXTERNAL_RF_ON();
// Timer8
setupPulsesDSM2(EXTERNAL_MODULE);
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
#if defined(REV3)
configure_pins( PIN_INTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25 | PIN_PUSHPULL ) ;
#else
GPIO_InitTypeDef GPIO_InitStructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_EXTPPM, ENABLE);
GPIO_PinAFConfig(GPIO_EXTPPM, GPIO_PinSource_EXTPPM, GPIO_AF_TIM8);
GPIO_InitStructure.GPIO_Pin = PIN_EXTPPM_OUT;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIO_EXTPPM, &GPIO_InitStructure);
#endif
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN ; // Enable clock
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN ; // Enable DMA2 clock
TIM8->CR1 &= ~TIM_CR1_CEN ;
TIM8->ARR = 44000 ; // 22mS
TIM8->CCR2 = 40000 ; // Update time
TIM8->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
#if defined(REV3)
TIM8->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P ;
#else
TIM8->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ;
#endif
TIM8->CR2 = TIM_CR2_OIS1 ; // O/P idle high
TIM8->BDTR = TIM_BDTR_MOE ; // Enable outputs
TIM8->CCR1 = dsm2Stream[0] ;
TIM8->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high
TIM8->EGR = 1 ; // Restart
// TIM8->SR &= ~TIM_SR_UIF ; // Clear flag
// TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
TIM8->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match
TIM8->DCR = 13 ; // DMA to CC1
// TIM8->CR1 = TIM_CR1_OPM ; // Just run once
// Enable the DMA channel here, DMA2 stream 2, channel 7
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
DMA2_Stream2->PAR = CONVERT_PTR_UINT(&TIM8->DMAR);
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&dsm2Stream[1]);
// DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
// DMA2_Stream2->NDTR = 100 ;
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
TIM8->CR1 |= TIM_CR1_CEN ;
NVIC_EnableIRQ(TIM8_CC_IRQn) ;
NVIC_SetPriority(TIM8_CC_IRQn, 7);
}
