static unsigned int dec10_setclrf(DisasContext *dc)
{
uint32_t flags;
unsigned int set = ~dc->opcode & 1;
flags = EXTRACT_FIELD(dc->ir, 0, 3)
| (EXTRACT_FIELD(dc->ir, 12, 15) << 4);
LOG_DIS("%s set=%d flags=%x\n", __func__, set, flags);
if (flags & X_FLAG) {
dc->flagx_known = 1;
if (set)
dc->flags_x = X_FLAG;
else
dc->flags_x = 0;
}
cris_evaluate_flags (dc);
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
cris_update_cc_x(dc);
tcg_gen_movi_tl(cc_op, dc->cc_op);
if (set) {
tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
} else {
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS],
~(flags|F_FLAG_V10|P_FLAG_V10));
}
dc->flags_uptodate = 1;
dc->clear_x = 0;
cris_lock_irq(dc);
return 2;
}
void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
{
#if !defined(CONFIG_USER_ONLY)
CRISCPU *cpu = cris_env_get_cpu(env);
#endif
uint32_t srs;
srs = env->pregs[PR_SRS];
srs &= 3;
env->sregs[srs][sreg] = env->regs[reg];
#if !defined(CONFIG_USER_ONLY)
if (srs == 1 || srs == 2) {
if (sreg == 6) {
/* Writes to tlb-hi write to mm_cause as a side
effect. */
env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
}
else if (sreg == 5) {
uint32_t set;
uint32_t idx;
uint32_t lo, hi;
uint32_t vaddr;
int tlb_v;
idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
set >>= 4;
set &= 3;
idx &= 15;
/* We've just made a write to tlb_lo. */
lo = env->sregs[SFR_RW_MM_TLB_LO];
/* Writes are done via r_mm_cause. */
hi = env->sregs[SFR_R_MM_CAUSE];
vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
13, 31);
vaddr <<= TARGET_PAGE_BITS;
tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
3, 3);
env->tlbsets[srs - 1][set][idx].lo = lo;
env->tlbsets[srs - 1][set][idx].hi = hi;
D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
vaddr, tlb_v, env->pc);
if (tlb_v) {
tlb_flush_page(CPU(cpu), vaddr);
}
}
}
static inline void decode(DisasContext *dc, uint32_t ir)
{
dc->ir = ir;
LOG_DIS("%8.8x\t", dc->ir);
dc->opcode = EXTRACT_FIELD(ir, 26, 31);
dc->imm5 = EXTRACT_FIELD(ir, 0, 4);
dc->imm16 = EXTRACT_FIELD(ir, 0, 15);
dc->imm26 = EXTRACT_FIELD(ir, 0, 25);
dc->csr = EXTRACT_FIELD(ir, 21, 25);
dc->r0 = EXTRACT_FIELD(ir, 21, 25);
dc->r1 = EXTRACT_FIELD(ir, 16, 20);
dc->r2 = EXTRACT_FIELD(ir, 11, 15);
/* bit 31 seems to indicate insn type. */
if (ir & (1 << 31)) {
dc->format = OP_FMT_RR;
} else {
dc->format = OP_FMT_RI;
}
assert(ARRAY_SIZE(decinfo) == 64);
assert(dc->opcode < 64);
decinfo[dc->opcode](dc);
}
static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
CPUState *env, uint32_t vaddr,
int rw, int usermode)
{
unsigned int vpage;
unsigned int idx;
uint32_t lo, hi;
uint32_t vpn, pfn = 0, pid, fg, fv, fk, fw, fx;
int i, match = 0;
vpage = vaddr >> 13;
idx = vpage & 31;
vpage >>= 4;
/* We know the index which to check on each set.
Scan both I and D. */
for (i = 0; i < 4; i++)
{
lo = env->tlbsets[0][i][idx].lo;
hi = env->tlbsets[0][i][idx].hi;
vpn = EXTRACT_FIELD(hi, 13, 31);
pid = EXTRACT_FIELD(hi, 0, 7);
if (vpn == vpage
&& pid == env->pregs[SR_PID]) {
match = 1;
break;
}
}
if (match) {
pfn = EXTRACT_FIELD(lo, 13, 31);
fg = EXTRACT_FIELD(lo, 4, 4);
fv = EXTRACT_FIELD(lo, 3, 3);
fk = EXTRACT_FIELD(lo, 2, 2);
fw = EXTRACT_FIELD(lo, 1, 1);
fx = EXTRACT_FIELD(lo, 0, 0);
}
printf ("%s match=%d vaddr=%x vpage=%x vpn=%x pfn=%x pid=%x %x\n",
__func__, match,
vaddr, vpage,
vpn, pfn, pid, env->pregs[SR_PID]);
res->pfn = pfn;
return !match;
}
static unsigned int crisv10_decoder(DisasContext *dc)
{
unsigned int insn_len = 2;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
tcg_gen_debug_insn_start(dc->pc);
/* Load a halfword onto the instruction register. */
dc->ir = lduw_code(dc->pc);
/* Now decode it. */
dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
dc->mode = EXTRACT_FIELD(dc->ir, 10, 11);
dc->src = EXTRACT_FIELD(dc->ir, 0, 3);
dc->size = EXTRACT_FIELD(dc->ir, 4, 5);
dc->cond = dc->dst = EXTRACT_FIELD(dc->ir, 12, 15);
dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
dc->clear_prefix = 1;
/* FIXME: What if this insn insn't 2 in length?? */
if (dc->src == 15 || dc->dst == 15)
tcg_gen_movi_tl(cpu_R[15], dc->pc + 2);
switch (dc->mode) {
case CRISV10_MODE_QIMMEDIATE:
insn_len = dec10_quick_imm(dc);
break;
case CRISV10_MODE_REG:
insn_len = dec10_reg(dc);
break;
case CRISV10_MODE_AUTOINC:
case CRISV10_MODE_INDIRECT:
insn_len = dec10_ind(dc);
break;
}
if (dc->clear_prefix && dc->tb_flags & PFIX_FLAG) {
dc->tb_flags &= ~PFIX_FLAG;
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~PFIX_FLAG);
if (dc->tb_flags != dc->tb->flags) {
dc->cpustate_changed = 1;
}
}
/* CRISv10 locks out interrupts on dslots. */
if (dc->delayed_branch == 2) {
cris_lock_irq(dc);
}
return insn_len;
}
static void mstatus_init()
{
if (!supports_extension('S'))
panic("supervisor support is required");
uintptr_t ms = 0;
ms = INSERT_FIELD(ms, MSTATUS_PRV, PRV_M);
ms = INSERT_FIELD(ms, MSTATUS_PRV1, PRV_S);
ms = INSERT_FIELD(ms, MSTATUS_PRV2, PRV_U);
ms = INSERT_FIELD(ms, MSTATUS_IE2, 1);
ms = INSERT_FIELD(ms, MSTATUS_VM, VM_CHOICE);
ms = INSERT_FIELD(ms, MSTATUS_FS, 3);
ms = INSERT_FIELD(ms, MSTATUS_XS, 3);
write_csr(mstatus, ms);
ms = read_csr(mstatus);
if (EXTRACT_FIELD(ms, MSTATUS_VM) != VM_CHOICE)
have_vm = 0;
write_csr(mtimecmp, 0);
clear_csr(mip, MIP_MSIP);
set_csr(mie, MIP_MSIP);
}
