/** To Register the ISRs with the underlying OS, if required */
void registerEdma3Interrupts (unsigned int edma3Id)
{
static UInt32 cookie = 0;
Int eventId = 0; /* GEM event id */
unsigned int numTc = 0;
/* Disabling the global interrupts */
cookie = Hwi_disable();
/* Transfer completion ISR */
CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
lisrEdma3ComplHandler0,
edma3Id,
TRUE);
CpIntc_mapSysIntToHostInt(0, ccXferCompInt[edma3Id][dsp_num],
ccXferHostInt[edma3Id][dsp_num]);
CpIntc_enableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
ccXferHostInt[edma3Id][dsp_num], TRUE);
EventCombiner_enableEvent(eventId);
/* CC Error ISR */
CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
edma3Id, TRUE);
CpIntc_mapSysIntToHostInt(0, ccErrorInt[edma3Id],
edma3ErrHostInt[edma3Id][dsp_num]);
/* TC Error ISR */
while (numTc < numEdma3Tc[edma3Id])
{
CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
(CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
edma3Id, TRUE);
CpIntc_mapSysIntToHostInt(0, tcErrorInt[edma3Id][numTc],
edma3ErrHostInt[edma3Id][dsp_num]);
numTc++;
}
/* Enable the host interrupt which is common for both CC and TC error */
CpIntc_enableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
edma3ErrHostInt[edma3Id][dsp_num], TRUE);
EventCombiner_enableEvent(eventId);
Hwi_enableInterrupt(hwiInterrupt);
/* enable the 'global' switch */
CpIntc_enableAllHostInts(0);
/* Restore interrupts */
Hwi_restore(cookie);
}
/** To Register the ISRs with the underlying OS, if required. */
void registerEdma3Interrupts (unsigned int edma3Id)
{
static UInt32 cookie = 0;
unsigned int numTc = 0;
/* Disabling the global interrupts */
cookie = Hwi_disable();
/* Enable the Xfer Completion Event Interrupt */
EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
(EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
edma3Id, 1);
EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
/* Enable the CC Error Event Interrupt */
EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
(EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
edma3Id, 1);
EventCombiner_enableEvent(ccErrorInt[edma3Id]);
/* Enable the TC Error Event Interrupt, according to the number of TCs. */
while (numTc < numEdma3Tc[edma3Id])
{
EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
(EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
edma3Id, 1);
EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
numTc++;
}
/**
* Enabling the HWI_ID.
* EDMA3 interrupts (transfer completion, CC error etc.)
* correspond to different ECM events (SoC specific). These ECM events come
* under ECM block XXX (handling those specific ECM events). Normally, block
* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
* is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
* mapped HWI_INT YYY, one should use the corresponding bitmask in the
* API C64_enableIER(), in which the YYY bit is SET.
*/
Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
/* Restore interrupts */
Hwi_restore(cookie);
}
/*
* ======== EventCombiner_dispatchPlug ========
* This function will plug the ECM dispatch table with the specified fxn
* and attrs.
*/
Void EventCombiner_dispatchPlug(UInt eventId, EventCombiner_FuncPtr fxn,
UArg arg, Bool unmask)
{
Assert_isTrue(eventId < EventCombiner_NUM_EVENTS,
EventCombiner_A_invalidEventId);
if (eventId < EventCombiner_NUM_EVENTS) {
EventCombiner_module->dispatchTab[eventId].fxn = fxn;
EventCombiner_module->dispatchTab[eventId].arg = arg;
if (unmask) {
EventCombiner_enableEvent(eventId);
}
}
}
