void MNT_init(void)
{
// init state machine
STM_init(&MNT.stm, &init);
// set the door pins direction
CONE_DDR &= ~_BV(CONE_PIN);
// init the cone state with its opposite value to generate the first event
MNT.cone_state = ~(CONE & _BV(CONE_PIN));
// init fifoes
FIFO_init(&MNT.ev_fifo, MNT.ev_buf, NB_EVENTS, sizeof(mnt_event_t));
FIFO_init(&MNT.cmds_fifo, MNT.cmds_buf, NB_CMDS, sizeof(frame_t));
FIFO_init(&MNT.out_fifo, MNT.out_buf, NB_OUT_FR, sizeof(frame_t));
// register to dispatcher
MNT.interf.channel = 7;
MNT.interf.cmde_mask = _CM(FR_TAKE_OFF) | _CM(FR_MINUT_TIME_OUT) | _CM(FR_STATE) | _CM(FR_APPLI_START);
MNT.interf.queue = &MNT.cmds_fifo;
DPT_register(&MNT.interf);
// init threads
PT_INIT(&MNT.pt_chk_time_out);
PT_INIT(&MNT.pt_chk_cmds);
PT_INIT(&MNT.pt_out);
// prevent any time-out
MNT.time_out = TIME_MAX;
MNT.sampling_rate = SAMPLING_START;
// the application start signal shall be received
MNT.started = 0;
}
// basic module initialization
void BSC_init(void)
{
frame_t fr;
// fifoes init
FIFO_init(&BSC.in_fifo, &BSC.in_buf, NB_IN_FRAMES, sizeof(frame_t));
FIFO_init(&BSC.out_fifo, &BSC.out_buf, NB_OUT_FRAMES, sizeof(frame_t));
// thread init
PT_INIT(&BSC.in_pt);
PT_INIT(&BSC.out_pt);
// reset time-out
BSC.time_out = 0;
BSC.is_running = FALSE;
// register own call-back for specific commands
BSC.interf.channel = 0;
BSC.interf.cmde_mask = _CM(FR_NO_CMDE)
| _CM(FR_RAM_READ)
| _CM(FR_RAM_WRITE)
| _CM(FR_EEP_READ)
| _CM(FR_EEP_WRITE)
| _CM(FR_FLH_READ)
| _CM(FR_FLH_WRITE)
| _CM(FR_SPI_READ)
| _CM(FR_SPI_WRITE)
| _CM(FR_WAIT)
| _CM(FR_CONTAINER);
BSC.interf.queue = &BSC.in_fifo;
DPT_register(&BSC.interf);
// drivers init
SLP_init();
EEP_init();
SPI_init(SPI_MASTER, SPI_THREE, SPI_MSB, SPI_DIV_16);
// read reset frame
EEP_read(0x00, (u8*)&fr, sizeof(frame_t));
while ( ! EEP_is_fini() )
;
// check if the frame is valid
if ( fr.dest == 0xff || fr.orig == 0xff || fr.cmde == 0xff || fr.status == 0xff ) {
return;
}
// enqueue the reset frame
FIFO_put(&BSC.out_fifo, &fr);
// lock the dispatcher to be able to treat the frame
DPT_lock(&BSC.interf);
}
// Time Synchro module initialization
void TSN_init(void)
{
// thread context init
PT_INIT(&TSN.pt);
// variables init
TSN.time_correction = 0;
TSN.time_out = TIME_1_SEC;
TIME_set_incr(10 * TIME_1_MSEC);
FIFO_init(&TSN.queue, &TSN.buf, QUEUE_SIZE, sizeof(TSN.buf) / sizeof(TSN.buf[0]));
// register to dispatcher
TSN.interf.channel = 8;
TSN.interf.cmde_mask = _CM(FR_TIME_GET);
TSN.interf.queue = &TSN.queue;
DPT_register(&TSN.interf);
}
// log module initialization
void LOG_init(void)
{
u8 index;
// init context and fifo
PT_INIT(&LOG.log_pt);
FIFO_init(&LOG.in_fifo, &LOG.in_buf, NB_FRAMES, sizeof(LOG.in_buf[0]));
// reset scan start address and index
LOG.eeprom_addr = EEPROM_START_ADDR;
LOG.sdcard_addr = SDCARD_START_ADDR;
LOG.index = 0;
// origin filter blocks every node by default
memset(&LOG.orig_filter, 0xff, NB_ORIG_FILTER);
memset(&LOG.orig_filter, 0x00, NB_ORIG_FILTER); // for debug, no filtering
LOG.state = LOG_RAM;
#ifdef SAVE_IN_RAM_ENABLED
LOG.ram_index = 0;
#endif
// find the start address for this session
index = LOG_find_eeprom_start();
LOG_find_sdcard_start(index);
// register to dispatcher
LOG.interf.channel = 6;
LOG.interf.queue = &LOG.in_fifo;
#if 0 // for debug
LOG.interf.cmde_mask = _CM(FR_STATE)
| _CM(FR_MUX_RESET)
| _CM(FR_RECONF_MODE)
| _CM(FR_MINUT_TAKE_OFF)
| _CM(FR_MINUT_DOOR)
| _CM(FR_SWITCH_POWER)
| MINIMAL_FILTER;
#else
LOG.interf.cmde_mask = -1;
#endif
DPT_register(&LOG.interf);
}
//-----------------------------------------------
void USBIOinit(void)
{
FIFO_init(&RxQueue,RxBuff,RX_SIZE);
}
