__attribute__((section(".boot_hdr.conf"))) #elif defined(__ICCARM__) #pragma location = ".boot_hdr.conf" #endif const flexspi_nor_config_t qspiflash_config = { .memConfig = { .tag = FLEXSPI_CFG_BLK_TAG, .version = FLEXSPI_CFG_BLK_VERSION, .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, .csHoldTime = 3u, .csSetupTime = 3u, // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock .sflashPadType = kSerialFlash_4Pads, .serialClkFreq = kFlexSpiSerialClk_100MHz, .sflashA1Size = 8u * 1024u * 1024u, .lookupTable = { // Read LUTs FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), }, }, .pageSize = 256u, .sectorSize = 4u * 1024u, .blockSize = 256u * 1024u, .isUniformBlockSize = false, }; #endif /* XIP_BOOT_HEADER_ENABLE */
.version = FLEXSPI_CFG_BLK_VERSION, .read_sample_clksrc = FLASH_READ_SAMPLE_CLK_EXTERNALINPUT_FROM_DQSPAD, .cs_hold_time = 3u, .cs_setup_time = 3u, .column_address_width = 3u, /* Enable DDR mode, Wordaddassable, Safe configuration, Differential clock */ .controller_misc_option = (1u << FLEXSPIMISC_OFFSET_DDR_MODE_EN) | (1u << FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN) | (1u << FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN) | (1u << FLEXSPIMISC_OFFSET_DIFFCLKEN), .sflash_pad_type = SERIAL_FLASH_8PADS, .serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_133MHz, .sflash_a1size = 64u * 1024u * 1024u, .data_valid_time = {16u, 16u}, .lookup_table = { /* Read LUTs */ FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), }, }, .page_size = 512u, .sector_size = 256u * 1024u, .blocksize = 256u * 1024u, .is_uniform_blocksize = 1, };