/************************************************************************
* NAME: fnet_eth_io_init
*
* DESCRIPTION: Ethernet IO initialization.
*************************************************************************/
void fnet_eth_io_init()
{
#if FNET_CFG_CPU_MPC5668G /* FADO */
/*
PG[11] PCR[107] ALT2 RX_CLK FEC I
PH[6] PCR[118] ALT2 RXD[2] FEC I
PH[5] PCR[117] ALT2 RXD[1] FEC I
PH[4] PCR[116] ALT2 RXD[0] FEC I
PH[0] PCR[112] ALT2 COL FEC I
PH[3] PCR[115] ALT2 RX_ER FEC I
PG[9] PCR[105] ALT2 CRS FEC I
PH[7] PCR[119] ALT2 RXD[3] FEC I
PG[7] PCR[103] ALT2 MDIO FEC I/O
PH[1] PCR[113] ALT2 RX_DV FEC I
PG[6] PCR[102] ALT2 MDC FEC O
PG[8] PCR[104] ALT2 TX_CLK FEC I
PG[14] PCR[110] ALT2 TXD[2] FEC O
PG[15] PCR[111] ALT2 TXD[3] FEC O
PG[13] PCR[109] ALT2 TXD[1] FEC O
PG[12] PCR[108] ALT2 TXD[0] FEC O
PH[2] PCR[114] ALT2 TX_EN FEC O
PG[10] PCR[106] ALT2 TX_ER FEC O
*/
FNET_MPC_GPIO_PCR(103) = 0xB06; /* Set to FEC_MDIO */
FNET_MPC_GPIO_PCR(102) = 0xA04; /* Set to FEC_MDC */
FNET_MPC_GPIO_PCR(114) = 0xA04; /* Set to FEC_TX_EN */
FNET_MPC_GPIO_PCR(108) = 0xA04; /* Set to FEC_TXD(0) */
FNET_MPC_GPIO_PCR(109) = 0xA04; /* Set to FEC_TXD(1) */
FNET_MPC_GPIO_PCR(110) = 0xA04; /* Set to FEC_TXD(2) */
FNET_MPC_GPIO_PCR(111) = 0xA04; /* Set to FEC_TXD(3) */
FNET_MPC_GPIO_PCR(106) = 0xA04 ; /* Set to FEC_TX_ER */
FNET_MPC_GPIO_PCR(112) = 0x906; /* Set to FEC_COL */
FNET_MPC_GPIO_PCR(104) = 0x906; /* Set to FEC_TX_CLK */
FNET_MPC_GPIO_PCR(105) = 0x906; /* Set to FEC_CRS */
FNET_MPC_GPIO_PCR(107) = 0x906; /* Set to FEC_RX_CLK */
FNET_MPC_GPIO_PCR(113) = 0x906; /* Set to FEC_RX_DV */
FNET_MPC_GPIO_PCR(116) = 0x906; /* Set to FEC_RXD(0) */
FNET_MPC_GPIO_PCR(117) = 0x906; /* Set to FEC_RXD(1) */
FNET_MPC_GPIO_PCR(118) = 0x906; /* Set to FEC_RXD(2) */
FNET_MPC_GPIO_PCR(119) = 0x906; /* Set to FEC_RXD(3) */
FNET_MPC_GPIO_PCR(115) = 0x906; /* Set to FEC_RX_ER */
#endif
#if FNET_CFG_CPU_MPC564xBC /* Bolero3M */
/*
PA[3] PCR[3] RX_CLK FEC I
PA[7] PCR[7] RXD[2] FEC I
PA[8] PCR[8] RXD[1] FEC I
PA[9] PCR[9] RXD[0] FEC I
PA[10] PCR[10] COL FEC I
PA[11] PCR[11] RX_ER FEC I
PE[12] PCR[76] CRS FEC I
PE[13] PCR[77] RXD[3] FEC I
PF[14] PCR[94] ALT4 MDIO FEC I/O
PF[15] PCR[95] RX_DV FEC I
PG[0] PCR[96] ALT4 MDC FEC O
PG[1] PCR[97] TX_CLK FEC I
PG[12] PCR[108] ALT4 TXD[2] FEC O
PG[13] PCR[109] ALT4 TXD[3] FEC O
PH[0] PCR[112] ALT4 TXD[1] FEC O
PH[1] PCR[113] ALT4 TXD[0] FEC O
PH[2) PCR[114) ALT4 TX_EN FEC O
PH(3) PCR(115) ALT4 TX_ER FEC O
*/
FNET_MPC_GPIO_PCR(94) = 0x1306; /* Set to FEC_MDIO */
FNET_MPC_GPIO_PCR(96) = 0x1202; /* Set to FEC_MDC */
FNET_MPC_GPIO_PCR(114) = 0x1204; /* Set to FEC_TX_EN */
FNET_MPC_GPIO_PCR(113) = 0x1204; /* Set to FEC_TXD(0) */
FNET_MPC_GPIO_PCR(112) = 0x1204; /* Set to FEC_TXD(1) */
FNET_MPC_GPIO_PCR(108) = 0x1204; /* Set to FEC_TXD(2) */
FNET_MPC_GPIO_PCR(109) = 0x1204; /* Set to FEC_TXD(3) */
FNET_MPC_GPIO_PCR(115) = 0x1204; /* Set to FEC_TX_ER */
FNET_MPC_GPIO_PCR(10) = 0x106; /* Set to FEC_COL */
FNET_MPC_GPIO_PCR(97) = 0x102; /* Set to FEC_TX_CLK */
FNET_MPC_GPIO_PCR(76) = 0x106; /* Set to FEC_CRS */
FNET_MPC_GPIO_PCR(3) = 0x106; /* Set to FEC_RX_CLK */
FNET_MPC_GPIO_PCR(95) = 0x102; /* Set to FEC_RX_DV */
FNET_MPC_GPIO_PCR(9) = 0x106; /* Set to FEC_RXD(0) */
FNET_MPC_GPIO_PCR(8) = 0x106; /* Set to FEC_RXD(1) */
FNET_MPC_GPIO_PCR(7) = 0x106; /* Set to FEC_RXD(2) */
FNET_MPC_GPIO_PCR(77) = 0x106; /* Set to FEC_RXD(3) */
FNET_MPC_GPIO_PCR(11) = 0x106; /* Set to FEC_RX_ER */
#endif
}
static inline void fnet_cpu_serial_gpio_init(long port_number)
{
/* Enable the proper UART pins */
#if FNET_CFG_CPU_MPC5668G
switch (port_number)
{
case 1:
FNET_MPC_GPIO_PCR(62) = 0x600;
FNET_MPC_GPIO_PCR(63) = 0x600;
break;
case 0:
default:
FNET_MPC_GPIO_PCR(60) = 0x600;
FNET_MPC_GPIO_PCR(61) = 0x600;
break;
}
#endif
#if FNET_CFG_CPU_MPC5744P
switch (port_number)
{
case 1:
break;
case 0:
default:
/* LINFlex 0 is connected to the MPC5746M MB
PB[2] MSCR[18] TXD LIN0 O SRC[1:0]=00 OBE=1 ODE=0 SMC=0 APC=0 IBE=0 HYS=0 PUS=0 PUE=0 INV=0 SSS=0001
PB[3] MSCR[19] RXD LIN0 O SRC[1:0]=00 OBE=0 ODE=0 SMC=0 APC=0 IBE=1 HYS=0 PUS=0 PUE=0 INV=0 SSS=0000
*/
FNET_MPC5744_GPIO_MSCR(18) = 0x02000001; /* Set to LIN0_TXD */
FNET_MPC5744_GPIO_MSCR(19) = 0x00080000; /* Set to LIN0_RXD */
FNET_MPC5744_GPIO_IMCR(165) = 0x00000001;
break;
}
#endif
#if FNET_CFG_CPU_MPC564xBC
switch (port_number)
{
case 9:
FNET_MPC_GPIO_PCR(130) = 0xA00;
FNET_MPC_GPIO_PCR(131) = 0x100;
break;
case 8:
FNET_MPC_GPIO_PCR(128) = 0xA00;
FNET_MPC_GPIO_PCR(129) = 0x100;
break;
case 7:
FNET_MPC_GPIO_PCR(104) = 0xA00;
FNET_MPC_GPIO_PCR(105) = 0x100;
break;
case 6:
FNET_MPC_GPIO_PCR(102) = 0xA00;
FNET_MPC_GPIO_PCR(103) = 0x100;
break;
case 5:
FNET_MPC_GPIO_PCR(92) = 0xA00;
FNET_MPC_GPIO_PCR(93) = 0x100;
break;
case 4:
FNET_MPC_GPIO_PCR(90) = 0xA00;
FNET_MPC_GPIO_PCR(91) = 0x100;
break;
case 3:
FNET_MPC_GPIO_PCR(74) = 0x600;
FNET_MPC_GPIO_PCR(75) = 0x100;
break;
case 2:
FNET_MPC_GPIO_PCR(40) = 0x600;
FNET_MPC_GPIO_PCR(41) = 0x100;
break;
case 1:
FNET_MPC_GPIO_PCR(38) = 0x600;
FNET_MPC_GPIO_PCR(39) = 0x100;
break;
case 0:
default:
FNET_MPC_GPIO_PCR(18) = 0x600;
FNET_MPC_GPIO_PCR(19) = 0x100;
break;
}
#endif
}
