/*FUNCTION**********************************************************************
*
* Function Name : FTM_DRV_Init
* Description : Initializes the FTM driver.
*
*END**************************************************************************/
ftm_status_t FTM_DRV_Init(uint32_t instance, const ftm_user_config_t * info)
{
assert(instance < FTM_INSTANCE_COUNT);
assert(g_ftmBase[instance] != NULL);
FTM_Type *ftmBase = g_ftmBase[instance];
uint8_t chan = g_ftmChannelCount[instance];
/* clock setting initialization*/
CLOCK_SYS_EnableFtmClock(instance);
FTM_HAL_Reset(ftmBase);
/* Reset the channel registers */
for(int i = 0; i < chan; i++)
{
FTM_WR_CnSC(ftmBase, i, 0);
FTM_WR_CnV(ftmBase, i, 0);
}
FTM_HAL_Init(ftmBase);
FTM_HAL_SetSyncMode(ftmBase, info->syncMethod);
FTM_HAL_SetTofFreq(ftmBase, info->tofFrequency);
FTM_HAL_SetWriteProtectionCmd(ftmBase, info->isWriteProtection);
FTM_HAL_SetBdmMode(ftmBase,info->BDMMode);
NVIC_ClearPendingIRQ(g_ftmIrqId[instance]);
INT_SYS_EnableIRQ(g_ftmIrqId[instance]);
return kStatusFtmSuccess;
}
/*See fsl_ftm_driver.h for documentation of this function.*/
void FTM_DRV_Init(uint8_t instance, ftm_user_config_t * info)
{
assert(instance < HW_FTM_INSTANCE_COUNT);
uint32_t ftmBaseAddr = g_ftmBaseAddr[instance];
uint8_t chan = FSL_FEATURE_FTM_CHANNEL_COUNTn(instance);
/* clock setting initialization*/
CLOCK_SYS_EnableFtmClock(instance);
FTM_HAL_Reset(ftmBaseAddr);
/* Reset the channel registers */
for(int i = 0; i < chan; i++)
{
HW_FTM_CnSC_WR(ftmBaseAddr, i, 0);
HW_FTM_CnV_WR(ftmBaseAddr, i, 0);
}
FTM_HAL_Init(ftmBaseAddr);
FTM_HAL_SetSyncMode(ftmBaseAddr, info->syncMethod);
FTM_HAL_SetTofFreq(ftmBaseAddr, info->tofFrequency);
FTM_HAL_SetWriteProtectionCmd(ftmBaseAddr, info->isWriteProtection);
FTM_HAL_SetBdmMode(ftmBaseAddr,info->BDMMode);
NVIC_ClearPendingIRQ(g_ftmIrqId[instance]);
INT_SYS_EnableIRQ(g_ftmIrqId[instance]);
}
/*************************************************************************
* Function Name: FTM2_init
* Parameters: none
* Return: none
* Description: FlexTimer 2 initialization
*************************************************************************/
void FTM2_init(void)
{
FTM_HAL_SetWriteProtectionCmd(FTM2_BASE_PTR, false);//false: Write-protection is disabled
FTM_HAL_Enable(FTM2_BASE_PTR, true);//true: all registers including FTM-specific registers are available
FTM_HAL_SetMod(FTM2_BASE_PTR, (uint16_t)0xffff);// Free running timer
FTM_HAL_SetClockSource(FTM2_BASE_PTR, kClock_source_FTM_SystemClk);//clock The FTM peripheral clock selection\n
FTM_HAL_SetClockPs(FTM2_BASE_PTR, kFtmDividedBy2); // system clock, divide by 2
FTM_HAL_EnableChnInt(FTM2_BASE_PTR, 0);//Enables the FTM peripheral timer channel(n) interrupt.
FTM_HAL_SetChnMSnBAMode(FTM2_BASE_PTR, 0, 1);//Sets the FTM peripheral timer channel mode.
INT_SYS_EnableIRQ(FTM2_IRQn);
set_irq_priority(FTM2_IRQn, ISR_PRIORITY_SLOW_TIMER);
}
/*************************************************************************
* Function Name: FTM0_init
* Parameters: none
* Return: none
* Description: FlexTimer 0 initialization
*************************************************************************/
void FTM0_init(void)
{
FTM_HAL_SetWriteProtectionCmd(FTM0_BASE_PTR, false);//false: Write-protection is disabled
FTM_HAL_Enable(FTM0_BASE_PTR, true);//true: all registers including FTM-specific registers are available
FTM_HAL_SetCounterInitVal(FTM0_BASE_PTR, (uint16_t)(-PWM_MODULO/2));
FTM_HAL_SetMod(FTM0_BASE_PTR, (uint16_t)PWM_MODULO/2-1); // 20 kHz
FTM_HAL_SetChnEdgeLevel(FTM0_BASE_PTR, 0, 2);
FTM_HAL_SetChnEdgeLevel(FTM0_BASE_PTR, 1, 2);
FTM_HAL_SetChnEdgeLevel(FTM0_BASE_PTR, 2, 2);
FTM_HAL_SetChnEdgeLevel(FTM0_BASE_PTR, 3, 2);
FTM_HAL_SetChnEdgeLevel(FTM0_BASE_PTR, 4, 2);
FTM_HAL_SetChnEdgeLevel(FTM0_BASE_PTR, 5, 2);
// output mask updated on PWM synchronization (not on rising edge of clock)
FTM_HAL_SetMaxLoadingCmd(FTM0_BASE_PTR, true);//True to enable minimum loading point
FTM_HAL_SetOutmaskPwmSyncModeCmd(FTM0_BASE_PTR, 1);//true if OUTMASK register is updated only by PWM sync\n
FTM_HAL_SetDualChnPwmSyncCmd(FTM0_BASE_PTR, 0, true);//True to enable PWM synchronization
FTM_HAL_SetDualChnPwmSyncCmd(FTM0_BASE_PTR, 1, true);
FTM_HAL_SetDualChnPwmSyncCmd(FTM0_BASE_PTR, 2, true);
FTM_HAL_SetDualChnDeadtimeCmd(FTM0_BASE_PTR, 0, true);//True to enable deadtime insertion, false to disable
FTM_HAL_SetDualChnDeadtimeCmd(FTM0_BASE_PTR, 1, true);
FTM_HAL_SetDualChnDeadtimeCmd(FTM0_BASE_PTR, 2, true);
FTM_HAL_SetDualChnCompCmd(FTM0_BASE_PTR, 0, true);//True to enable complementary mode, false to disable
FTM_HAL_SetDualChnCompCmd(FTM0_BASE_PTR, 1, true);
FTM_HAL_SetDualChnCompCmd(FTM0_BASE_PTR, 2, true);
FTM_HAL_SetDualChnCombineCmd(FTM0_BASE_PTR, 0, true);// True to enable channel pair to combine, false to disable
FTM_HAL_SetDualChnCombineCmd(FTM0_BASE_PTR, 1, true);
FTM_HAL_SetDualChnCombineCmd(FTM0_BASE_PTR, 2, true);
// High transistors have negative polarity (MC33927/37)
FTM_HAL_SetDeadtimePrescale(FTM0_BASE_PTR, kFtmDivided1);
FTM_HAL_SetDeadtimeCount(FTM0_BASE_PTR, FTM_DEADTIME_DTVAL(63)); // DTVAL - deadtime value (0-63): deadtime period = DTPS x DTVAL
FTM_HAL_SetInitTriggerCmd(FTM0_BASE_PTR, true);//True to enable, false to disable
FTM_HAL_SetChnOutputPolarityCmd(FTM0_BASE_PTR, 0, 1);
FTM_HAL_SetChnOutputPolarityCmd(FTM0_BASE_PTR, 2, 1);
FTM_HAL_SetChnOutputPolarityCmd(FTM0_BASE_PTR, 4, 1);
/* Following line configures:
- enhanced PWM synchronization, FTM counter reset on SW sync
- output SW control / polarity registers updated on PWM synchronization (not on rising edge of clock)
- output SW control/inverting(swap)/mask registers updated from buffers on SW synchronization */
FTM_HAL_SetPwmSyncModeCmd(FTM0_BASE_PTR, true);// true means use Enhanced PWM synchronization\n
FTM_HAL_SetCounterSoftwareSyncModeCmd(FTM0_BASE_PTR, true);//true means software trigger activates register sync\n
FTM_HAL_SetSwoctrlPwmSyncModeCmd(FTM0_BASE_PTR, true);//true means SWOCTRL register is updated by PWM synch\n
FTM_HAL_SetInvctrlPwmSyncModeCmd(FTM0_BASE_PTR, true);//true means INVCTRL register is updated by PWM synch\n
FTM_HAL_SetSwoctrlSoftwareSyncModeCmd(FTM0_BASE_PTR, true);//true means software trigger activates register sync\n
FTM_HAL_SetInvctrlSoftwareSyncModeCmd(FTM0_BASE_PTR, true);//true means software trigger activates register sync\n
FTM_HAL_SetOutmaskSoftwareSyncModeCmd(FTM0_BASE_PTR, true);//true means software
FTM_HAL_SetChnOutputMask(FTM0_BASE_PTR, 0, 1);//Sets the FTM peripheral timer channel output mask.
FTM_HAL_SetChnOutputMask(FTM0_BASE_PTR, 1, 1);
FTM_HAL_SetChnOutputMask(FTM0_BASE_PTR, 2, 1);
FTM_HAL_SetChnOutputMask(FTM0_BASE_PTR, 3, 1);
FTM_HAL_SetChnOutputMask(FTM0_BASE_PTR, 4, 1);
FTM_HAL_SetChnOutputMask(FTM0_BASE_PTR, 5, 1);
FTM_HAL_SetCounter(FTM0_BASE_PTR, 1U); // update of FTM settings
// no ISR, counting up, system clock, divide by 1
FTM_HAL_SetClockSource(FTM0_BASE_PTR, kClock_source_FTM_SystemClk);
FTM_HAL_SetChnCountVal(FTM0_BASE_PTR, 0, (uint16_t)(-PWM_MODULO/4));
FTM_HAL_SetChnCountVal(FTM0_BASE_PTR, 1,(uint16_t) PWM_MODULO/4);
FTM_HAL_SetChnCountVal(FTM0_BASE_PTR, 2, (uint16_t)(-PWM_MODULO/4));
FTM_HAL_SetChnCountVal(FTM0_BASE_PTR, 3,(uint16_t) PWM_MODULO/4);
FTM_HAL_SetChnCountVal(FTM0_BASE_PTR, 4, (uint16_t)(-PWM_MODULO/4));
FTM_HAL_SetChnCountVal(FTM0_BASE_PTR, 5,(uint16_t) PWM_MODULO/4);
FTM_HAL_SetSoftwareTriggerCmd(FTM0_BASE_PTR, 1);
FTM_HAL_SetPwmLoadCmd(FTM0_BASE_PTR, 1);
// FTM0 PWM output pins
PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 1, kPortMuxAlt4);
PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 3, kPortMuxAlt4);
PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 4, kPortMuxAlt4);
PORT_HAL_SetMuxMode(PORTD_BASE_PTR, 4, kPortMuxAlt4);
PORT_HAL_SetMuxMode(PORTD_BASE_PTR, 5, kPortMuxAlt4);
#if defined(KV10Z7_SERIES)
PORT_HAL_SetMuxMode(PORTE_BASE_PTR, 25, kPortMuxAlt3);
#elif (defined(KV10Z1287_SERIES) || defined(KV11Z7_SERIES))
PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 2, kPortMuxAlt4);
#endif
GPIO_HAL_SetPinDir(GPIOC_BASE_PTR, 1, kGpioDigitalOutput);
GPIO_HAL_SetPinDir(GPIOC_BASE_PTR, 3, kGpioDigitalOutput);
GPIO_HAL_SetPinDir(GPIOC_BASE_PTR, 4, kGpioDigitalOutput);
GPIO_HAL_SetPinDir(GPIOD_BASE_PTR, 4, kGpioDigitalOutput);
GPIO_HAL_SetPinDir(GPIOD_BASE_PTR, 5, kGpioDigitalOutput);
#if defined(KV10Z7_SERIES)
GPIO_HAL_SetPinDir(GPIOE_BASE_PTR, 25, kGpioDigitalOutput);
#elif (defined(KV10Z1287_SERIES) || defined(KV11Z7_SERIES))
GPIO_HAL_SetPinDir(GPIOC_BASE_PTR, 2, kGpioDigitalOutput);
#endif
}