static void qube_raq_galileo_fixup(struct pci_dev *dev)
{
unsigned short galileo_id;
/* Fix PCI latency-timer and cache-line-size values in Galileo
* host bridge.
*/
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
/*
* On all machines prior to Q2, we had the STOP line disconnected
* from Galileo to VIA on PCI. The new Galileo does not function
* correctly unless we have it connected.
*
* Therefore we must set the disconnect/retry cycle values to
* something sensible when using the new Galileo.
*/
pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
galileo_id &= 0xff; /* mask off class info */
if (galileo_id >= 0x10) {
/* New Galileo, assumes PCI stop line to VIA is connected. */
GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);
} else if (galileo_id == 0x1 || galileo_id == 0x2) {
signed int timeo;
/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
timeo = GALILEO_INL(GT_PCI0_TOR_OFS);
/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS);
}
}
static inline void galileo_irq(struct pt_regs *regs)
{
unsigned int mask, pending, devfn;
mask = GALILEO_INL(GT_INTRMASK_OFS);
pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask;
if (pending & GALILEO_INTR_T0EXP) {
GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
do_IRQ(COBALT_GALILEO_IRQ, regs);
} else if (pending & GALILEO_INTR_RETRY_CTR) {
devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8;
GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS);
printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n",
PCI_SLOT(devfn), PCI_FUNC(devfn));
} else {
void __init plat_timer_setup(struct irqaction *irq)
{
/* Load timer value for 1KHz (TCLK is 50MHz) */
GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS);
/* Enable timer */
GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS);
/* Register interrupt */
setup_irq(COBALT_GALILEO_IRQ, irq);
/* Enable interrupt */
GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
}
void __init plat_mem_setup(void)
{
static struct uart_port uart;
unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
int i;
_machine_restart = cobalt_machine_restart;
_machine_halt = cobalt_machine_halt;
pm_power_off = cobalt_machine_power_off;
set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));
/* I/O port resource must include UART and LCD/buttons */
ioport_resource.end = 0x0fffffff;
/* request I/O space for devices used on all i[345]86 PCs */
for (i = 0; i < COBALT_IO_RESOURCES; i++)
request_resource(&ioport_resource, cobalt_io_resources + i);
/* Read the cobalt id register out of the PCI config space */
PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
printk("Cobalt board ID: %d\n", cobalt_board_id);
#ifdef CONFIG_PCI
register_pci_controller(&cobalt_pci_controller);
#endif
#ifdef CONFIG_SERIAL_8250
if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
#ifdef CONFIG_EARLY_PRINTK
cobalt_early_console();
#endif
uart.line = 0;
uart.type = PORT_UNKNOWN;
uart.uartclk = 18432000;
uart.irq = COBALT_SERIAL_IRQ;
uart.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
uart.iobase = 0xc800000;
uart.iotype = UPIO_PORT;
early_serial_setup(&uart);
}
#endif
}
asmlinkage void galileo_irq(struct pt_regs *regs)
{
unsigned long irq_src;
irq_src = GALILEO_INL(GT_INTRCAUSE_OFS);
/* Check for timer irq ... */
if (irq_src & GALILEO_T0EXP) {
/* Clear the int line */
GALILEO_OUTL(0, GT_INTRCAUSE_OFS);
do_IRQ(COBALT_TIMER_IRQ, regs);
} else
printk("Spurious Galileo interrupt...\n");
}
asmlinkage void cobalt_irq(struct pt_regs *regs)
{
unsigned int pending = read_c0_status() & read_c0_cause();
if (pending & CAUSEF_IP2) { /* int 18 */
unsigned long irq_src = GALILEO_INL(GT_INTRCAUSE_OFS);
/* Check for timer irq ... */
if (irq_src & GALILEO_T0EXP) {
/* Clear the int line */
GALILEO_OUTL(0, GT_INTRCAUSE_OFS);
do_IRQ(COBALT_TIMER_IRQ, regs);
}
return;
}
if (pending & CAUSEF_IP6) { /* int 22 */
int irq = i8259_irq();
if (irq >= 0)
do_IRQ(irq, regs);
return;
}
if (pending & CAUSEF_IP3) { /* int 19 */
do_IRQ(COBALT_ETH0_IRQ, regs);
return;
}
if (pending & CAUSEF_IP4) { /* int 20 */
do_IRQ(COBALT_ETH1_IRQ, regs);
return;
}
if (pending & CAUSEF_IP5) { /* int 21 */
do_IRQ(COBALT_SERIAL_IRQ, regs);
return;
}
if (pending & CAUSEF_IP7) { /* int 23 */
do_IRQ(COBALT_QUBE_SLOT_IRQ, regs);
return;
}
}
