static void qube_raq_galileo_fixup(struct pci_dev *dev) { unsigned short galileo_id; /* Fix PCI latency-timer and cache-line-size values in Galileo * host bridge. */ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); /* * On all machines prior to Q2, we had the STOP line disconnected * from Galileo to VIA on PCI. The new Galileo does not function * correctly unless we have it connected. * * Therefore we must set the disconnect/retry cycle values to * something sensible when using the new Galileo. */ pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id); galileo_id &= 0xff; /* mask off class info */ if (galileo_id >= 0x10) { /* New Galileo, assumes PCI stop line to VIA is connected. */ GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS); } else if (galileo_id == 0x1 || galileo_id == 0x2) { signed int timeo; /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ timeo = GALILEO_INL(GT_PCI0_TOR_OFS); /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS); } }
void __init plat_timer_setup(struct irqaction *irq) { /* Load timer value for 1KHz (TCLK is 50MHz) */ GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS); /* Enable timer */ GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS); /* Register interrupt */ setup_irq(COBALT_GALILEO_IRQ, irq); /* Enable interrupt */ GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); }
static inline void galileo_irq(struct pt_regs *regs) { unsigned int mask, pending, devfn; mask = GALILEO_INL(GT_INTRMASK_OFS); pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask; if (pending & GALILEO_INTR_T0EXP) { GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS); do_IRQ(COBALT_GALILEO_IRQ, regs); } else if (pending & GALILEO_INTR_RETRY_CTR) { devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8; GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS); printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n", PCI_SLOT(devfn), PCI_FUNC(devfn)); } else {
asmlinkage void galileo_irq(struct pt_regs *regs) { unsigned long irq_src; irq_src = GALILEO_INL(GT_INTRCAUSE_OFS); /* Check for timer irq ... */ if (irq_src & GALILEO_T0EXP) { /* Clear the int line */ GALILEO_OUTL(0, GT_INTRCAUSE_OFS); do_IRQ(COBALT_TIMER_IRQ, regs); } else printk("Spurious Galileo interrupt...\n"); }
asmlinkage void cobalt_irq(struct pt_regs *regs) { unsigned int pending = read_c0_status() & read_c0_cause(); if (pending & CAUSEF_IP2) { /* int 18 */ unsigned long irq_src = GALILEO_INL(GT_INTRCAUSE_OFS); /* Check for timer irq ... */ if (irq_src & GALILEO_T0EXP) { /* Clear the int line */ GALILEO_OUTL(0, GT_INTRCAUSE_OFS); do_IRQ(COBALT_TIMER_IRQ, regs); } return; } if (pending & CAUSEF_IP6) { /* int 22 */ int irq = i8259_irq(); if (irq >= 0) do_IRQ(irq, regs); return; } if (pending & CAUSEF_IP3) { /* int 19 */ do_IRQ(COBALT_ETH0_IRQ, regs); return; } if (pending & CAUSEF_IP4) { /* int 20 */ do_IRQ(COBALT_ETH1_IRQ, regs); return; } if (pending & CAUSEF_IP5) { /* int 21 */ do_IRQ(COBALT_SERIAL_IRQ, regs); return; } if (pending & CAUSEF_IP7) { /* int 23 */ do_IRQ(COBALT_QUBE_SLOT_IRQ, regs); return; } }