/* Handle a break interrupt. */ void frv_break_interrupt ( SIM_CPU *current_cpu, struct frv_interrupt *interrupt, IADDR current_pc ) { IADDR new_pc; /* BPCSR=PC BPSR.BS=PSR.S BPSR.BET=PSR.ET PSR.S=1 PSR.ET=0 TBR.TT=0xff PC=TBR */ /* Must set PSR.S first to allow access to supervisor-only spr registers. */ SET_H_BPSR_BS (GET_H_PSR_S ()); SET_H_BPSR_BET (GET_H_PSR_ET ()); SET_H_PSR_S (1); SET_H_PSR_ET (0); /* Must set PSR.S first to allow access to supervisor-only spr registers. */ SET_H_SPR (H_SPR_BPCSR, current_pc); /* Set the new PC in the TBR. */ SET_H_TBR_TT (interrupt->handler_offset); new_pc = GET_H_SPR (H_SPR_TBR); SET_H_PC (new_pc); CPU_DEBUG_STATE (current_cpu) = 1; }
/* Check for interrupts caused by illegal insn access. These conditions are checked in the order specified by the fr400 and fr500 LSI specs. */ void frv_detect_insn_access_interrupts (SIM_CPU *current_cpu, SCACHE *sc) { const CGEN_INSN *insn = sc->argbuf.idesc->idata; SIM_DESC sd = CPU_STATE (current_cpu); FRV_VLIW *vliw = CPU_VLIW (current_cpu); /* Check for vliw constraints. */ if (vliw->constraint_violation) frv_queue_illegal_instruction_interrupt (current_cpu, insn); /* Check for non-excepting insns. */ else if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NON_EXCEPTING) && ! GET_H_PSR_NEM ()) frv_queue_non_implemented_instruction_interrupt (current_cpu, insn); /* Check for conditional insns. */ else if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONDITIONAL) && ! GET_H_PSR_CM ()) frv_queue_non_implemented_instruction_interrupt (current_cpu, insn); /* Make sure floating point support is enabled. */ else if (! GET_H_PSR_EF ()) { /* Generate fp_disabled if it is a floating point insn or if PSR.EM is off and the insns accesses a fp register. */ if (frv_is_float_insn (insn) || (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR_ACCESS) && ! GET_H_PSR_EM ())) frv_queue_float_disabled_interrupt (current_cpu); } /* Make sure media support is enabled. */ else if (! GET_H_PSR_EM ()) { /* Generate mp_disabled if it is a media insn. */ if (frv_is_media_insn (insn) || CGEN_INSN_NUM (insn) == FRV_INSN_MTRAP) frv_queue_media_disabled_interrupt (current_cpu); } /* Check for privileged insns. */ else if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRIVILEGED) && ! GET_H_PSR_S ()) frv_queue_privileged_instruction_interrupt (current_cpu, insn); #if 0 /* disable for now until we find out how FSR0.QNE gets reset. */ else { /* Enter the halt state if FSR0.QNE is set and we are executing a floating point insn, a media insn or an insn which access a FR register. */ SI fsr0 = GET_FSR (0); if (GET_FSR_QNE (fsr0) && (frv_is_float_insn (insn) || frv_is_media_insn (insn) || CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR_ACCESS))) { sim_engine_halt (sd, current_cpu, NULL, GET_H_PC (), sim_stopped, SIM_SIGINT); } } #endif }
/* Handle a program interrupt or a software interrupt. */ void frv_program_or_software_interrupt ( SIM_CPU *current_cpu, struct frv_interrupt *interrupt, IADDR current_pc ) { USI new_pc; int original_psr_et; /* PCSR=PC PSR.PS=PSR.S PSR.ET=0 PSR.S=1 if PSR.ESR==1 SR0 through SR3=GR4 through GR7 TBR.TT=interrupt handler offset PC=TBR */ original_psr_et = GET_H_PSR_ET (); SET_H_PSR_PS (GET_H_PSR_S ()); SET_H_PSR_ET (0); SET_H_PSR_S (1); /* Must set PSR.S first to allow access to supervisor-only spr registers. */ /* The PCSR depends on the precision of the interrupt. */ if (interrupt->precise) SET_H_SPR (H_SPR_PCSR, previous_vliw_pc); else SET_H_SPR (H_SPR_PCSR, current_pc); /* Set the new PC in the TBR. */ SET_H_TBR_TT (interrupt->handler_offset); new_pc = GET_H_SPR (H_SPR_TBR); SET_H_PC (new_pc); /* If PSR.ET was not originally set, then enter the stopped state. */ if (! original_psr_et) { SIM_DESC sd = CPU_STATE (current_cpu); frv_non_operating_interrupt (current_cpu, interrupt->kind, current_pc); sim_engine_halt (sd, current_cpu, NULL, new_pc, sim_stopped, SIM_SIGINT); } }
/* Handle a program interrupt or a software interrupt. */ void frv_external_interrupt ( SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item, IADDR pc ) { USI new_pc; struct frv_interrupt *interrupt = & frv_interrupt_table[item->kind]; /* Don't process the interrupt if PSR.ET is not set or if it is masked. Interrupt 15 is processed even if it appears to be masked. */ if (! GET_H_PSR_ET () || (interrupt->kind != FRV_INTERRUPT_LEVEL_15 && interrupt->kind < GET_H_PSR_PIL ())) return; /* Leave it for later. */ /* Remove the interrupt from the queue. */ --frv_interrupt_state.queue_index; /* PCSR=PC PSR.PS=PSR.S PSR.ET=0 PSR.S=1 if PSR.ESR==1 SR0 through SR3=GR4 through GR7 TBR.TT=interrupt handler offset PC=TBR */ SET_H_PSR_PS (GET_H_PSR_S ()); SET_H_PSR_ET (0); SET_H_PSR_S (1); /* Must set PSR.S first to allow access to supervisor-only spr registers. */ SET_H_SPR (H_SPR_PCSR, GET_H_PC ()); /* Set the new PC in the TBR. */ SET_H_TBR_TT (interrupt->handler_offset); new_pc = GET_H_SPR (H_SPR_TBR); SET_H_PC (new_pc); }
/* Return from trap. */ USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field) { USI new_pc; /* if (normal running mode and debug_field==0 PC=PCSR PSR.ET=1 PSR.S=PSR.PS else if (debug running mode and debug_field==1) PC=(BPCSR) PSR.ET=BPSR.BET PSR.S=BPSR.BS change to normal running mode */ int psr_s = GET_H_PSR_S (); int psr_et = GET_H_PSR_ET (); /* Check for exceptions in the priority order listed in the FRV Architecture Volume 2. */ if (! psr_s) { /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */ if (! psr_et) { SIM_DESC sd = CPU_STATE (current_cpu); sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); } /* privileged_instruction interrupt will have already been queued by frv_detect_insn_access_interrupts. */ new_pc = pc + 4; } else if (psr_et) { /* Halt if PSR.S is set. See chapter 6 of the LSI. */ if (psr_s) { SIM_DESC sd = CPU_STATE (current_cpu); sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); } frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); new_pc = pc + 4; } else if (! CPU_DEBUG_STATE (current_cpu) && debug_field == 0) { USI psr = GET_PSR (); /* Return from normal running state. */ new_pc = GET_H_SPR (H_SPR_PCSR); SET_PSR_ET (psr, 1); SET_PSR_S (psr, GET_PSR_PS (psr)); sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); } else if (CPU_DEBUG_STATE (current_cpu) && debug_field == 1) { USI psr = GET_PSR (); /* Return from debug state. */ new_pc = GET_H_SPR (H_SPR_BPCSR); SET_PSR_ET (psr, GET_H_BPSR_BET ()); SET_PSR_S (psr, GET_H_BPSR_BS ()); sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); CPU_DEBUG_STATE (current_cpu) = 0; } else new_pc = pc + 4; return new_pc; }