void rtw_hal_sreset_reset(_adapter *padapter) { padapter = GET_PRIMARY_ADAPTER(padapter); if(padapter->HalFunc.silentreset) padapter->HalFunc.silentreset(padapter); }
void rtw_sreset_reset(struct rtw_adapter *active_adapter) { struct rtw_adapter *padapter = GET_PRIMARY_ADAPTER(active_adapter); struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter); struct sreset_priv *psrtpriv = &pHalData->srestpriv; struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; unsigned long start = jiffies; DBG_8723A("%s\n", __func__); mutex_lock(&psrtpriv->silentreset_mutex); psrtpriv->silent_reset_inprogress = true; pwrpriv->change_rfpwrstate = rf_off; sreset_stop_adapter(padapter); ips_enter23a(padapter); ips_leave23a(padapter); sreset_start_adapter(padapter); psrtpriv->silent_reset_inprogress = false; mutex_unlock(&psrtpriv->silentreset_mutex); DBG_8723A("%s done in %d ms\n", __func__, jiffies_to_msecs(jiffies - start)); }
bool rtw_sreset_inprogress(struct rtw_adapter *padapter) { struct rtw_adapter *primary_adapter = GET_PRIMARY_ADAPTER(padapter); struct hal_data_8723a *pHalData = GET_HAL_DATA(primary_adapter); return pHalData->srestpriv.silent_reset_inprogress; }
void LeaveAllPowerSaveModeDirect(struct adapter *Adapter) { struct adapter *pri_padapter = GET_PRIMARY_ADAPTER(Adapter); struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter); DBG_871X("%s.....\n", __func__); if (true == Adapter->bSurpriseRemoved) { DBG_871X(FUNC_ADPT_FMT ": bSurpriseRemoved =%d Skip!\n", FUNC_ADPT_ARG(Adapter), Adapter->bSurpriseRemoved); return; } if ((check_fwstate(pmlmepriv, _FW_LINKED) == true)) { /* connect */ if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) { DBG_871X("%s: Driver Already Leave LPS\n", __func__); return; } down(&pwrpriv->lock); rtw_set_rpwm(Adapter, PS_STATE_S4); up(&pwrpriv->lock); rtw_lps_ctrl_wk_cmd(pri_padapter, LPS_CTRL_LEAVE, 0); } else{ if (pwrpriv->rf_pwrstate == rf_off) if (false == ips_leave(pri_padapter)) DBG_871X("======> ips_leave fail.............\n"); } }
bool rtw_hal_sreset_inprogress(_adapter *padapter) { bool inprogress = _FALSE; padapter = GET_PRIMARY_ADAPTER(padapter); if(padapter->HalFunc.sreset_inprogress) inprogress = padapter->HalFunc.sreset_inprogress(padapter); return inprogress; }
bool rtw_hal_sreset_inprogress(struct rtw_adapter *padapter) { bool inprogress = false; padapter = GET_PRIMARY_ADAPTER(padapter); if (padapter->HalFunc.sreset_inprogress) inprogress = padapter->HalFunc.sreset_inprogress(padapter); return inprogress; }
s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer) { _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter); if (pri_adapter->bFWReady == _TRUE) return padapter->HalFunc.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer); else if (padapter->registrypriv.mp_mode == 0) DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n" , FUNC_ADPT_ARG(padapter), ElementID); return _FAIL; }
void rtw_os_xmit_schedule(_adapter *padapter) { #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter); if (!padapter) return; if (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE) _rtw_up_sema(&pri_adapter->xmitpriv.xmit_sema); #else _irqL irqL; struct xmit_priv *pxmitpriv; if (!padapter) return; pxmitpriv = &padapter->xmitpriv; _enter_critical_bh(&pxmitpriv->lock, &irqL); if (rtw_txframes_pending(padapter)) tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); _exit_critical_bh(&pxmitpriv->lock, &irqL); #if defined(CONFIG_PCI_HCI) && defined(CONFIG_XMIT_THREAD_MODE) if (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE) _rtw_up_sema(&padapter->xmitpriv.xmit_sema); #endif #endif }
/***************************************** * H2C Msg format : *| 31 - 8 |7 | 6 - 0 | *| h2c_msg |Ext_bit |CMD_ID | * ******************************************/ static void _FillH2CCmd92D(_adapter* padapter, u8 ElementID, u32 CmdLen, u8* pCmdBuffer) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); u8 BoxNum; u16 BOXReg=0, BOXExtReg=0; u8 BoxContent[4], BoxExtContent[2]; u8 BufIndex=0; u8 U1btmp; //Read 0x1bf u8 bWriteSucess = _FALSE; u8 IsFwRead = _FALSE; u8 WaitH2cLimmit = 100; u8 WaitWriteH2cLimmit = 100; u8 idx=0; _func_enter_; padapter = GET_PRIMARY_ADAPTER(padapter); pHalData = GET_HAL_DATA(padapter); _enter_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL); //DBG_8192C("FillH2CCmd : ElementID=%d \n",ElementID); while(!bWriteSucess) { WaitWriteH2cLimmit--; if(WaitWriteH2cLimmit == 0) { DBG_8192C("FillH2CCmd92C():Write H2C fail because no trigger for FW INT!!!!!!!!\n"); break; } // 2. Find the last BOX number which has been writen. BoxNum = pHalData->LastHMEBoxNum; switch(BoxNum) { case 0: BOXReg = REG_HMEBOX_0; BOXExtReg = REG_HMEBOX_EXT_0; break; case 1: BOXReg = REG_HMEBOX_1; BOXExtReg = REG_HMEBOX_EXT_1; break; case 2: BOXReg = REG_HMEBOX_2; BOXExtReg = REG_HMEBOX_EXT_2; break; case 3: BOXReg = REG_HMEBOX_3; BOXExtReg = REG_HMEBOX_EXT_3; break; default: break; } // 3. Check if the box content is empty. IsFwRead = CheckFwReadLastH2C(padapter, BoxNum); while(!IsFwRead) { //wait until Fw read WaitH2cLimmit--; if(WaitH2cLimmit == 0) { DBG_8192C("FillH2CCmd92C(): Wating too long for FW read clear HMEBox(%d)!!!\n", BoxNum); break; } rtw_udelay_os(10); //us IsFwRead = CheckFwReadLastH2C(padapter, BoxNum); U1btmp = rtw_read8(padapter, 0x1BF); //DBG_8192C("FillH2CCmd92C(): Wating for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n", BoxNum, U1btmp); } // If Fw has not read the last H2C cmd, break and give up this H2C. if(!IsFwRead) { DBG_8192C("FillH2CCmd92C(): Write H2C register BOX[%d] fail!!!!! Fw do not read. \n", BoxNum); break; } // 4. Fill the H2C cmd into box _rtw_memset(BoxContent, 0, sizeof(BoxContent)); _rtw_memset(BoxExtContent, 0, sizeof(BoxExtContent)); BoxContent[0] = ElementID; // Fill element ID //DBG_8192C("FillH2CCmd92C():Write ElementID BOXReg(%4x) = %2x \n", BOXReg, ElementID); switch(CmdLen) { case 1: { BoxContent[0] &= ~(BIT7); _rtw_memcpy((u8 *)(BoxContent)+1, pCmdBuffer+BufIndex, 1); //PlatformEFIOWrite4Byte(Adapter, BOXReg, *((pu4Byte)BoxContent)); //For Endian Free. for(idx= 0; idx < 4; idx++) { rtw_write8(padapter, BOXReg+idx, BoxContent[idx]); } break; } case 2: { BoxContent[0] &= ~(BIT7); _rtw_memcpy((u8 *)(BoxContent)+1, pCmdBuffer+BufIndex, 2); //PlatformEFIOWrite4Byte(Adapter, BOXReg, *((pu4Byte)BoxContent)); for(idx=0; idx < 4; idx++) { rtw_write8(padapter, BOXReg+idx, BoxContent[idx]); } break; } case 3: { BoxContent[0] &= ~(BIT7); _rtw_memcpy((u8 *)(BoxContent)+1, pCmdBuffer+BufIndex, 3); //PlatformEFIOWrite4Byte(Adapter, BOXReg, *((pu4Byte)BoxContent)); for(idx = 0; idx < 4 ; idx++) { rtw_write8(padapter, BOXReg+idx, BoxContent[idx]); } break; } case 4: { BoxContent[0] |= (BIT7); _rtw_memcpy((u8 *)(BoxExtContent), pCmdBuffer+BufIndex, 2); _rtw_memcpy((u8 *)(BoxContent)+1, pCmdBuffer+BufIndex+2, 2); //PlatformEFIOWrite2Byte(Adapter, BOXExtReg, *((pu2Byte)BoxExtContent)); //PlatformEFIOWrite4Byte(Adapter, BOXReg, *((pu4Byte)BoxContent)); for(idx = 0 ; idx < 2 ; idx ++) { rtw_write8(padapter, BOXExtReg+idx, BoxExtContent[idx]); } for(idx = 0 ; idx < 4 ; idx ++) { rtw_write8(padapter, BOXReg+idx, BoxContent[idx]); } break; } case 5: { BoxContent[0] |= (BIT7); _rtw_memcpy((u8 *)(BoxExtContent), pCmdBuffer+BufIndex, 2); _rtw_memcpy((u8 *)(BoxContent)+1, pCmdBuffer+BufIndex+2, 3); //PlatformEFIOWrite2Byte(Adapter, BOXExtReg, *((pu2Byte)BoxExtContent)); //PlatformEFIOWrite4Byte(Adapter, BOXReg, *((pu4Byte)BoxContent)); for(idx = 0 ; idx < 2 ; idx ++) { rtw_write8(padapter, BOXExtReg+idx, BoxExtContent[idx]); } for(idx = 0 ; idx < 4 ; idx ++) { rtw_write8(padapter, BOXReg+idx, BoxContent[idx]); } break; } default: break; } //DBG_8192C("FillH2CCmd(): BoxExtContent=0x%04x\n", *(u16*)BoxExtContent); //DBG_8192C("FillH2CCmd(): BoxContent=0x%08x\n", *(u32*)BoxContent); // 5. Normal chip does not need to check if the H2C cmd has be written successfully. // 92D test chip does not need to check, bWriteSucess = _TRUE; // Record the next BoxNum pHalData->LastHMEBoxNum = BoxNum+1; if(pHalData->LastHMEBoxNum == 4) // loop to 0 pHalData->LastHMEBoxNum = 0; //DBG_8192C("FillH2CCmd92C():pHalData->LastHMEBoxNum = %d\n", pHalData->LastHMEBoxNum); } _exit_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL); _func_exit_; }
int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); struct mlme_priv *pmlmepriv; int ret = _SUCCESS; unsigned long start = jiffies; unsigned long deny_time = jiffies + msecs_to_jiffies(ips_deffer_ms); /* for LPS */ LeaveAllPowerSaveMode(padapter); /* IPS still bound with primary adapter */ padapter = GET_PRIMARY_ADAPTER(padapter); pmlmepriv = &padapter->mlmepriv; if (time_before(pwrpriv->ips_deny_time, deny_time)) pwrpriv->ips_deny_time = deny_time; if (pwrpriv->ps_processing) { DBG_871X("%s wait ps_processing...\n", __func__); while (pwrpriv->ps_processing && jiffies_to_msecs(jiffies - start) <= 3000) msleep(10); if (pwrpriv->ps_processing) DBG_871X("%s wait ps_processing timeout\n", __func__); else DBG_871X("%s wait ps_processing done\n", __func__); } if (pwrpriv->bInternalAutoSuspend == false && pwrpriv->bInSuspend) { DBG_871X("%s wait bInSuspend...\n", __func__); while (pwrpriv->bInSuspend && jiffies_to_msecs(jiffies - start) <= 3000 ) { msleep(10); } if (pwrpriv->bInSuspend) DBG_871X("%s wait bInSuspend timeout\n", __func__); else DBG_871X("%s wait bInSuspend done\n", __func__); } /* System suspend is not allowed to wakeup */ if ((pwrpriv->bInternalAutoSuspend == false) && (true == pwrpriv->bInSuspend)){ ret = _FAIL; goto exit; } /* block??? */ if ((pwrpriv->bInternalAutoSuspend == true) && (padapter->net_closed == true)) { ret = _FAIL; goto exit; } /* I think this should be check in IPS, LPS, autosuspend functions... */ if (check_fwstate(pmlmepriv, _FW_LINKED) == true) { ret = _SUCCESS; goto exit; } if (rf_off == pwrpriv->rf_pwrstate) { { DBG_8192C("%s call ips_leave....\n", __FUNCTION__); if (_FAIL == ips_leave(padapter)) { DBG_8192C("======> ips_leave fail.............\n"); ret = _FAIL; goto exit; } } } /* TODO: the following checking need to be merged... */ if (padapter->bDriverStopped || !padapter->bup || !padapter->hw_init_completed ){ DBG_8192C("%s: bDriverStopped =%d, bup =%d, hw_init_completed =%u\n" , caller , padapter->bDriverStopped , padapter->bup , padapter->hw_init_completed); ret = false; goto exit; } exit: deny_time = jiffies + msecs_to_jiffies(ips_deffer_ms); if (time_before(pwrpriv->ips_deny_time, deny_time)) pwrpriv->ips_deny_time = deny_time; return ret; }
bool rtw_hal_sreset_inprogress(_adapter *padapter) { padapter = GET_PRIMARY_ADAPTER(padapter); return padapter->HalFunc.sreset_inprogress(padapter); }
/***************************************** * H2C Msg format : * 0x1DF - 0x1D0 *| 31 - 8 | 7-5 4 - 0 | *| h2c_msg |Class_ID CMD_ID | * * Extend 0x1FF - 0x1F0 *|31 - 0 | *|ext_msg| ******************************************/ static s32 FillH2CCmd_88E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); u8 h2c_box_num; u32 msgbox_addr; u32 msgbox_ex_addr; u8 cmd_idx,ext_cmd_len; u32 h2c_cmd = 0; u32 h2c_cmd_ex = 0; s32 ret = _FAIL; _func_enter_; padapter = GET_PRIMARY_ADAPTER(padapter); pHalData = GET_HAL_DATA(padapter); if(padapter->bFWReady == _FALSE) { DBG_8192C("FillH2CCmd_88E(): return H2C cmd because fw is not ready\n"); return ret; } _enter_critical_mutex(&(dvobj->h2c_fwcmd_mutex), NULL); if (!pCmdBuffer) { goto exit; } if (CmdLen > RTL88E_MAX_CMD_LEN) { goto exit; } if (padapter->bSurpriseRemoved == _TRUE) goto exit; //pay attention to if race condition happened in H2C cmd setting. do{ h2c_box_num = pHalData->LastHMEBoxNum; if(!_is_fw_read_cmd_down(padapter, h2c_box_num)){ DBG_8192C(" fw read cmd failed...\n"); goto exit; } *(u8*)(&h2c_cmd) = ElementID; if(CmdLen<=3) { _rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer, CmdLen ); } else{ _rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer,3); ext_cmd_len = CmdLen-3; _rtw_memcpy((u8*)(&h2c_cmd_ex), pCmdBuffer+3,ext_cmd_len ); //Write Ext command msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num *RTL88E_EX_MESSAGE_BOX_SIZE); #ifdef CONFIG_H2C_EF for(cmd_idx=0;cmd_idx<ext_cmd_len;cmd_idx++ ){ rtw_write8(padapter,msgbox_ex_addr+cmd_idx,*((u8*)(&h2c_cmd_ex)+cmd_idx)); } #else h2c_cmd_ex = le32_to_cpu( h2c_cmd_ex ); rtw_write32(padapter, msgbox_ex_addr, h2c_cmd_ex); #endif } // Write command msgbox_addr =REG_HMEBOX_0 + (h2c_box_num *RTL88E_MESSAGE_BOX_SIZE); #ifdef CONFIG_H2C_EF for(cmd_idx=0;cmd_idx<RTL88E_MESSAGE_BOX_SIZE;cmd_idx++ ){ rtw_write8(padapter,msgbox_addr+cmd_idx,*((u8*)(&h2c_cmd)+cmd_idx)); } #else h2c_cmd = le32_to_cpu( h2c_cmd ); rtw_write32(padapter,msgbox_addr, h2c_cmd); #endif // DBG_8192C("MSG_BOX:%d,CmdLen(%d), reg:0x%x =>h2c_cmd:0x%x, reg:0x%x =>h2c_cmd_ex:0x%x ..\n" // ,pHalData->LastHMEBoxNum ,CmdLen,msgbox_addr,h2c_cmd,msgbox_ex_addr,h2c_cmd_ex); pHalData->LastHMEBoxNum = (h2c_box_num+1) % RTL88E_MAX_H2C_BOX_NUMS; }while(0); ret = _SUCCESS; exit: _exit_critical_mutex(&(dvobj->h2c_fwcmd_mutex), NULL); _func_exit_; return ret; }
/***************************************** * H2C Msg format : *| 31 - 8 |7 | 6 - 0 | *| h2c_msg |Ext_bit |CMD_ID | * ******************************************/ int FillH2CCmd(struct rtw_adapter *padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer) { u8 bcmd_down = false; s32 retry_cnts = 100; u8 h2c_box_num; u32 msgbox_addr; u32 msgbox_ex_addr; struct hal_data_8723a *pHalData; u32 h2c_cmd = 0; u16 h2c_cmd_ex = 0; int ret = _FAIL; padapter = GET_PRIMARY_ADAPTER(padapter); pHalData = GET_HAL_DATA(padapter); mutex_lock(&adapter_to_dvobj(padapter)->h2c_fwcmd_mutex); if (!pCmdBuffer) goto exit; if (CmdLen > RTL92C_MAX_CMD_LEN) goto exit; if (padapter->bSurpriseRemoved == true) goto exit; /* pay attention to if race condition happened in H2C cmd setting. */ do { h2c_box_num = pHalData->LastHMEBoxNum; if (!_is_fw_read_cmd_down(padapter, h2c_box_num)) { DBG_8723A(" fw read cmd failed...\n"); goto exit; } if (CmdLen <= 3) { memcpy((u8 *)(&h2c_cmd)+1, pCmdBuffer, CmdLen); } else { memcpy((u8 *)(&h2c_cmd_ex), pCmdBuffer, EX_MESSAGE_BOX_SIZE); memcpy((u8 *)(&h2c_cmd)+1, pCmdBuffer+2, (CmdLen-EX_MESSAGE_BOX_SIZE)); *(u8 *)(&h2c_cmd) |= BIT(7); } *(u8 *)(&h2c_cmd) |= ElementID; if (h2c_cmd & BIT(7)) { msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE); h2c_cmd_ex = le16_to_cpu(h2c_cmd_ex); rtl8723au_write16(padapter, msgbox_ex_addr, h2c_cmd_ex); } msgbox_addr = REG_HMEBOX_0 + (h2c_box_num * MESSAGE_BOX_SIZE); h2c_cmd = le32_to_cpu(h2c_cmd); rtl8723au_write32(padapter, msgbox_addr, h2c_cmd); bcmd_down = true; pHalData->LastHMEBoxNum = (h2c_box_num+1) % RTL92C_MAX_H2C_BOX_NUMS; } while ((!bcmd_down) && (retry_cnts--)); ret = _SUCCESS; exit: mutex_unlock(&adapter_to_dvobj(padapter)->h2c_fwcmd_mutex); return ret; }