コード例 #1
0
ファイル: pwrseqcmd.c プロジェクト: 020gzh/linux
/* This routine deals with the Power Configuration CMDs parsing
 * for RTL8723/RTL8188E Series IC.
 */
u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers,
			    struct wl_pwr_cfg pwrseqcmd[])
{
	struct wl_pwr_cfg pwrcfgcmd = {0};
	u8 poll_bit = false;
	u32 aryidx = 0;
	u8 value = 0;
	u32 offset = 0;
	u32 poll_count = 0; /*  polling autoload done. */
	u32 max_poll_count = 5000;

	do {
		pwrcfgcmd = pwrseqcmd[aryidx];

		RT_TRACE(_module_hal_init_c_, _drv_info_,
			 ("rtl88eu_pwrseqcmdparsing: offset(%#x) cut_msk(%#x)"
			  " cmd(%#x)"
			  "msk(%#x) value(%#x)\n",
			 GET_PWR_CFG_OFFSET(pwrcfgcmd),
			 GET_PWR_CFG_CUT_MASK(pwrcfgcmd),
			 GET_PWR_CFG_CMD(pwrcfgcmd),
			 GET_PWR_CFG_MASK(pwrcfgcmd),
			 GET_PWR_CFG_VALUE(pwrcfgcmd)));

		/* Only Handle the command whose CUT is matched */
		if (GET_PWR_CFG_CUT_MASK(pwrcfgcmd) & cut_vers) {
			switch (GET_PWR_CFG_CMD(pwrcfgcmd)) {
			case PWR_CMD_READ:
				RT_TRACE(_module_hal_init_c_, _drv_info_,
					 ("rtl88eu_pwrseqcmdparsing: PWR_CMD_READ\n"));
				break;
			case PWR_CMD_WRITE:
				RT_TRACE(_module_hal_init_c_, _drv_info_,
					 ("rtl88eu_pwrseqcmdparsing: PWR_CMD_WRITE\n"));
				offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);

				/*  Read the value from system register */
				value = usb_read8(padapter, offset);

				value &= ~(GET_PWR_CFG_MASK(pwrcfgcmd));
				value |= (GET_PWR_CFG_VALUE(pwrcfgcmd) &
					  GET_PWR_CFG_MASK(pwrcfgcmd));

				/*  Write the value back to system register */
				usb_write8(padapter, offset, value);
				break;
			case PWR_CMD_POLLING:
				RT_TRACE(_module_hal_init_c_, _drv_info_,
					 ("rtl88eu_pwrseqcmdparsing: PWR_CMD_POLLING\n"));

				poll_bit = false;
				offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);
				do {
					value = usb_read8(padapter, offset);
					value &= GET_PWR_CFG_MASK(pwrcfgcmd);

					if (value == (GET_PWR_CFG_VALUE(pwrcfgcmd) &
						      GET_PWR_CFG_MASK(pwrcfgcmd)))
						poll_bit = true;
					else
						udelay(10);

					if (poll_count++ > max_poll_count) {
						DBG_88E("Fail to polling Offset[%#x]\n", offset);
						return false;
					}
				} while (!poll_bit);
				break;
			case PWR_CMD_DELAY:
				RT_TRACE(_module_hal_init_c_, _drv_info_,
					 ("rtl88eu_pwrseqcmdparsing: PWR_CMD_DELAY\n"));
				if (GET_PWR_CFG_VALUE(pwrcfgcmd) == PWRSEQ_DELAY_US)
					udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd));
				else
					udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd)*1000);
				break;
			case PWR_CMD_END:
				/* When this command is parsed, end the process */
				RT_TRACE(_module_hal_init_c_, _drv_info_,
					 ("rtl88eu_pwrseqcmdparsing: PWR_CMD_END\n"));
				return true;
			default:
				RT_TRACE(_module_hal_init_c_, _drv_err_,
					 ("rtl88eu_pwrseqcmdparsing: Unknown CMD!!\n"));
				break;
			}
		}

		aryidx++;/* Add Array Index */
	} while (1);
	return true;
}
コード例 #2
0
//
//	Description:
//		This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
//
//	Assumption:
//		We should follow specific format which was released from HW SD.
//
//	2011.07.07, added by Roger.
//
u8 HalPwrSeqCmdParsing(
	PADAPTER		padapter,
	u8				CutVersion,
	u8				FabVersion,
	u8				InterfaceType,
	WLAN_PWR_CFG	PwrSeqCmd[])
{
	WLAN_PWR_CFG 	PwrCfgCmd = {0};
	u8				bPollingBit = _FALSE;
	u32				AryIdx = 0;
	u8				value = 0;
	u32				offset = 0;
	u32				pollingCount = 0; // polling autoload done.
	u32				maxPollingCnt = 5000;

	do {
		PwrCfgCmd = PwrSeqCmd[AryIdx];

		RT_TRACE(_module_hal_init_c_ , _drv_info_,
				 ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
					GET_PWR_CFG_OFFSET(PwrCfgCmd),
					GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
					GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
					GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
					GET_PWR_CFG_BASE(PwrCfgCmd),
					GET_PWR_CFG_CMD(PwrCfgCmd),
					GET_PWR_CFG_MASK(PwrCfgCmd),
					GET_PWR_CFG_VALUE(PwrCfgCmd)));

		//2 Only Handle the command whose FAB, CUT, and Interface are matched
		if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
			(GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
			(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType))
		{
			switch (GET_PWR_CFG_CMD(PwrCfgCmd))
			{
				case PWR_CMD_READ:
					RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
					break;

				case PWR_CMD_WRITE:
					RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
					offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);

#ifdef CONFIG_SDIO_HCI
					//
					// <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
					// 2011.07.07.
					//
					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
					{
						// Read Back SDIO Local value
						value = SdioLocalCmd52Read1Byte(padapter, offset);

						value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
						value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));

						// Write Back SDIO Local value
						SdioLocalCmd52Write1Byte(padapter, offset, value);
					}
					else
#endif
					{
#ifdef CONFIG_GSPI_HCI
						if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
							offset = SPI_LOCAL_OFFSET | offset;
#endif
						// Read the value from system register
						value = rtw_read8(padapter, offset);

						value=value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));
						value=value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));

						// Write the value back to sytem register
						rtw_write8(padapter, offset, value);
					}
					break;

				case PWR_CMD_POLLING:
					RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));

					bPollingBit = _FALSE;
					offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_GSPI_HCI
					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
						offset = SPI_LOCAL_OFFSET | offset;
#endif
					do {
#ifdef CONFIG_SDIO_HCI
						if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
							value = SdioLocalCmd52Read1Byte(padapter, offset);
						else
#endif
							value = rtw_read8(padapter, offset);

						value=value&GET_PWR_CFG_MASK(PwrCfgCmd);
						if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
							bPollingBit = _TRUE;
						else
							rtw_udelay_os(10);

						if (pollingCount++ > maxPollingCnt) {
							DBG_871X("Fail to polling Offset[%#x]=%02x\n", offset, value);
							return _FALSE;
						}
					} while (!bPollingBit);

					break;

				case PWR_CMD_DELAY:
					RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
					if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
						rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
					else
						rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
					break;

				case PWR_CMD_END:
					// When this command is parsed, end the process
					RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
					return _TRUE;
					break;

				default:
					RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
					break;
			}
		}

		AryIdx++;//Add Array Index
	}while(1);

	return _TRUE;
}
コード例 #3
0
ファイル: pwrseqcmd.c プロジェクト: 4T-Shirt/rtlwifi_new
/*
*	Description:
*		This routine deal with the Power Configuration CMDs
*		 parsing for RTL8723/RTL8188E Series IC.
*	Assumption:
*		We should follow specific format which was released from HW SD.
*
*	2011.07.07, added by Roger.
*/
bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
			u8 fab_version, u8 interface_type,
			struct wlan_pwr_cfg	pwrcfgcmd[])

{
	struct wlan_pwr_cfg pwr_cfg_cmd = {0};
	bool b_polling_bit = false;
	u32 ary_idx = 0;
	u8 value = 0;
	u32 offset = 0;
	u32 polling_count = 0;
	u32 max_polling_cnt = 5000;

	do {
		pwr_cfg_cmd = pwrcfgcmd[ary_idx];
		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
			"rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), fab_msk(%#x), interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
			GET_PWR_CFG_OFFSET(pwr_cfg_cmd),
				GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd),
			GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd),
				GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd),
			GET_PWR_CFG_BASE(pwr_cfg_cmd),
				GET_PWR_CFG_CMD(pwr_cfg_cmd),
			GET_PWR_CFG_MASK(pwr_cfg_cmd),
				GET_PWR_CFG_VALUE(pwr_cfg_cmd));

		if ((GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd)&fab_version)
			&& (GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd)&cut_version)
			&& (GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd)&interface_type)) {
			switch (GET_PWR_CFG_CMD(pwr_cfg_cmd)) {
			case PWR_CMD_READ:
				RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
					"rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n");
				break;

			case PWR_CMD_WRITE: {
				RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
					"rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
				offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);

					/*Read the value from system register*/
					value = rtl_read_byte(rtlpriv, offset);
					value = value & (~(GET_PWR_CFG_MASK(pwr_cfg_cmd)));
					value = value | (GET_PWR_CFG_VALUE(pwr_cfg_cmd)
							& GET_PWR_CFG_MASK(pwr_cfg_cmd));

					/*Write the value back to sytem register*/
					rtl_write_byte(rtlpriv, offset, value);
				}
				break;

			case PWR_CMD_POLLING:
				RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
					"rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
				b_polling_bit = false;
				offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);

				do {
					value = rtl_read_byte(rtlpriv, offset);

					value = value & GET_PWR_CFG_MASK(pwr_cfg_cmd);
					if (value == (GET_PWR_CFG_VALUE(pwr_cfg_cmd)
							& GET_PWR_CFG_MASK(pwr_cfg_cmd)))
						b_polling_bit = true;
					else
						udelay(10);

					if (polling_count++ > max_polling_cnt) {
						RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
							 "polling fail in pwrseqcmd\n");
						return false;
					}
				} while (!b_polling_bit);

				break;

			case PWR_CMD_DELAY:
				RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
					"rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
				if (GET_PWR_CFG_VALUE(pwr_cfg_cmd) == PWRSEQ_DELAY_US)
					udelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
				else
					mdelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
				break;

			case PWR_CMD_END:
				RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
					"rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n");
				return true;
				break;

			default:
				RT_ASSERT(false,
					"rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n");
				break;
			}

		}

		ary_idx++;
	} while (1);

	return true;
}
コード例 #4
0
ファイル: HalPwrSeqCmd.c プロジェクト: MingxuZhang/rtl8821cu
/*
 *	Description:
 *		This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
 *
 *	Assumption:
 *		We should follow specific format which was released from HW SD.
 *
 *	2011.07.07, added by Roger.
 *   */
u8 HalPwrSeqCmdParsing(
	PADAPTER		padapter,
	u8				CutVersion,
	u8				FabVersion,
	u8				InterfaceType,
	WLAN_PWR_CFG	PwrSeqCmd[])
{
	WLAN_PWR_CFG	PwrCfgCmd = {0};
	u8				bPollingBit = _FALSE;
	u32				AryIdx = 0;
	u8				value = 0;
	u32				offset = 0;
	u32				pollingCount = 0; /* polling autoload done. */
	u32				maxPollingCnt = 5000;

	do {
		PwrCfgCmd = PwrSeqCmd[AryIdx];


		/* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
		if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
		    (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
		    (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
			switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
			case PWR_CMD_READ:
				break;

			case PWR_CMD_WRITE:
				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);

#ifdef CONFIG_SDIO_HCI
				/*  */
				/* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
				/* 2011.07.07. */
				/*  */
				if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
					/* Read Back SDIO Local value */
					value = SdioLocalCmd52Read1Byte(padapter, offset);

					value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
					value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));

					/* Write Back SDIO Local value */
					SdioLocalCmd52Write1Byte(padapter, offset, value);
				} else
#endif
				{
#ifdef CONFIG_GSPI_HCI
					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
						offset = SPI_LOCAL_OFFSET | offset;
#endif
					/* Read the value from system register */
					value = rtw_read8(padapter, offset);

					value = value & (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
					value = value | (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));

					/* Write the value back to sytem register */
					rtw_write8(padapter, offset, value);
				}
				break;

			case PWR_CMD_POLLING:

				bPollingBit = _FALSE;
				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_GSPI_HCI
				if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
					offset = SPI_LOCAL_OFFSET | offset;
#endif
				do {
#ifdef CONFIG_SDIO_HCI
					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
						value = SdioLocalCmd52Read1Byte(padapter, offset);
					else
#endif
						value = rtw_read8(padapter, offset);

					value = value & GET_PWR_CFG_MASK(PwrCfgCmd);
					if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
						bPollingBit = _TRUE;
					else
						rtw_udelay_os(10);

					if (pollingCount++ > maxPollingCnt) {
						RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
						return _FALSE;
					}
				} while (!bPollingBit);

				break;

			case PWR_CMD_DELAY:
				if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
					rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
				else
					rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000);
				break;

			case PWR_CMD_END:
				/* When this command is parsed, end the process */
				return _TRUE;
				break;

			default:
				break;
			}
		}

		AryIdx++;/* Add Array Index */
	} while (1);

	return _TRUE;
}
コード例 #5
0
ファイル: HalPwrSeqCmd.c プロジェクト: LXiong/openwrt-rtk
//
//	Description: 
//		This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
//
//	Assumption:
//		We should follow specific format which was released from HW SD. 
//
//	2011.07.07, added by Roger.
//
unsigned int HalPwrSeqCmdParsing(struct rtl8192cd_priv *priv, unsigned char CutVersion, unsigned char FabVersion, 
							 unsigned char InterfaceType, WLAN_PWR_CFG PwrSeqCmd[])
{
		
	WLAN_PWR_CFG 	PwrCfgCmd = {0};
	unsigned int 		bPollingBit = FALSE;
	unsigned int		AryIdx=0;
	unsigned char		value = 0;
	unsigned int		offset = 0;
	unsigned int 		pollingCount = 0; // polling autoload done.
	unsigned int		maxPollingCnt = 5000;
	
	do {
		PwrCfgCmd=PwrSeqCmd[AryIdx];

		DEBUG_INFO("%s %d, ENTRY, offset:0x%x, cut_msk:0x%x, fab_msk:0x%x, if_msk:0x%x, base:0x%x, cmd:0x%x, msk:0x%x, value:0x%x\n", 
			__FUNCTION__, __LINE__, GET_PWR_CFG_OFFSET(PwrCfgCmd), GET_PWR_CFG_CUT_MASK(PwrCfgCmd), 
			GET_PWR_CFG_FAB_MASK(PwrCfgCmd), GET_PWR_CFG_INTF_MASK(PwrCfgCmd), GET_PWR_CFG_BASE(PwrCfgCmd), 
			GET_PWR_CFG_CMD(PwrCfgCmd), GET_PWR_CFG_MASK(PwrCfgCmd), GET_PWR_CFG_VALUE(PwrCfgCmd));

		//2 Only Handle the command whose FAB, CUT, and Interface are matched
		if((GET_PWR_CFG_FAB_MASK(PwrCfgCmd)&FabVersion)&&
			(GET_PWR_CFG_CUT_MASK(PwrCfgCmd)&CutVersion)&&
			(GET_PWR_CFG_INTF_MASK(PwrCfgCmd)&InterfaceType)) {
			switch(GET_PWR_CFG_CMD(PwrCfgCmd))
			{
			case PWR_CMD_READ:
				DEBUG_INFO("%s %d, PWR_CMD_READ\n", __FUNCTION__, __LINE__);
				break;

			case PWR_CMD_WRITE:
				DEBUG_INFO("%s %d, PWR_CMD_WRITE\n", __FUNCTION__, __LINE__);
				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);

#ifdef CONFIG_SDIO_HCI
				//
				// <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
				// 2011.07.07.
				//
				if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
				{
					// Read Back SDIO Local value
					value = SdioLocalCmd52Read1Byte(priv, offset);

					value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
					value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));

					// Write Back SDIO Local value
					SdioLocalCmd52Write1Byte(priv, offset, value);
				}
				else
#endif
				{
					//Read the value from system register		
					value = RTL_R8(offset);
					value = value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));
					value = value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));

					//Write the value back to sytem register
					RTL_W8(offset, value);
				}
				break;

			case PWR_CMD_POLLING:
				DEBUG_INFO("%s %d, PWR_CMD_POLLING\n", __FUNCTION__, __LINE__);
				bPollingBit = FALSE;					
				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);				

				do {
#ifdef CONFIG_SDIO_HCI
					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
						value = SdioLocalCmd52Read1Byte(priv, offset);
					else
#endif
					value = RTL_R8(offset);
					value=value&GET_PWR_CFG_MASK(PwrCfgCmd);
					if(value==(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd)))
						bPollingBit=TRUE;
					else	
						delay_us(10);
					
					if(pollingCount++ > maxPollingCnt){
						DEBUG_WARN("%s %d, PWR_CMD_POLLING, Fail to polling Offset[0x%x]\n", __FUNCTION__, __LINE__, offset);
						return FALSE;
					}
				}while(!bPollingBit);

				break;

			case PWR_CMD_DELAY:
				DEBUG_INFO("%s %d, PWR_CMD_DELAY\n", __FUNCTION__, __LINE__);
				if(GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
					delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd));
				else
					delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
				break; 

			case PWR_CMD_END:
				// When this command is parsed, end the process
				DEBUG_INFO("%s %d, PWR_CMD_END\n", __FUNCTION__, __LINE__);
				return TRUE;
				break;

			default:
				DEBUG_ERR("%s %d, Unknown CMD!!\n", __FUNCTION__, __LINE__);
				break;
			}

		}
		
		AryIdx++;//Add Array Index
	}while(1);

	return TRUE;
}
コード例 #6
0
ファイル: HalPwrSeqCmd.c プロジェクト: 09sea98/rtl8188eu
/*		This routine deals with the Power Configuration CMDs parsing
 *		for RTL8723/RTL8188E Series IC.
 *	Assumption:
 *		We should follow specific format which was released from HW SD.
 */
u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers,
		       u8 ifacetype, struct wl_pwr_cfg pwrseqcmd[])
{
	struct wl_pwr_cfg pwrcfgcmd = {0};
	u8 poll_bit = false;
	u32 aryidx = 0;
	u8 value = 0;
	u32 offset = 0;
	u32 poll_count = 0; /*  polling autoload done. */
	u32 max_poll_count = 5000;

	do {
		pwrcfgcmd = pwrseqcmd[aryidx];

		RT_TRACE(_module_hal_init_c_ , _drv_info_,
			 ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
			 GET_PWR_CFG_OFFSET(pwrcfgcmd),
			 GET_PWR_CFG_CUT_MASK(pwrcfgcmd),
			 GET_PWR_CFG_FAB_MASK(pwrcfgcmd),
			 GET_PWR_CFG_INTF_MASK(pwrcfgcmd),
			 GET_PWR_CFG_BASE(pwrcfgcmd),
			 GET_PWR_CFG_CMD(pwrcfgcmd),
			 GET_PWR_CFG_MASK(pwrcfgcmd),
			 GET_PWR_CFG_VALUE(pwrcfgcmd)));

		/* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
		if ((GET_PWR_CFG_FAB_MASK(pwrcfgcmd) & fab_vers) &&
		    (GET_PWR_CFG_CUT_MASK(pwrcfgcmd) & cut_vers) &&
		    (GET_PWR_CFG_INTF_MASK(pwrcfgcmd) & ifacetype)) {
			switch (GET_PWR_CFG_CMD(pwrcfgcmd)) {
			case PWR_CMD_READ:
				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
				break;
			case PWR_CMD_WRITE:
				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
				offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);

				/*  Read the value from system register */
				value = rtw_read8(padapter, offset);

				value &= ~(GET_PWR_CFG_MASK(pwrcfgcmd));
				value |= (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd));

				/*  Write the value back to system register */
				rtw_write8(padapter, offset, value);
				break;
			case PWR_CMD_POLLING:
				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));

				poll_bit = false;
				offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);
				do {
						value = rtw_read8(padapter, offset);

					value &= GET_PWR_CFG_MASK(pwrcfgcmd);
					if (value == (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd)))
						poll_bit = true;
					else
						rtw_udelay_os(10);

					if (poll_count++ > max_poll_count) {
						DBG_88E("Fail to polling Offset[%#x]\n", offset);
						return false;
					}
				} while (!poll_bit);
				break;
			case PWR_CMD_DELAY:
				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
				if (GET_PWR_CFG_VALUE(pwrcfgcmd) == PWRSEQ_DELAY_US)
					rtw_udelay_os(GET_PWR_CFG_OFFSET(pwrcfgcmd));
				else
					rtw_udelay_os(GET_PWR_CFG_OFFSET(pwrcfgcmd)*1000);
				break;
			case PWR_CMD_END:
				/*  When this command is parsed, end the process */
				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
				return true;
				break;
			default:
				RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
				break;
			}
		}

		aryidx++;/* Add Array Index */
	} while (1);
	return true;
}
コード例 #7
0
ファイル: HalPwrSeqCmd.c プロジェクト: morphis/rtl8188eu
u8 HalPwrSeqCmdParsing(
	PADAPTER		padapter,
	u8				CutVersion,
	u8				FabVersion,
	u8				InterfaceType,
	WLAN_PWR_CFG	PwrSeqCmd[])
{
	WLAN_PWR_CFG	PwrCfgCmd = {0};
	u8				bPollingBit = false;
	u32				AryIdx = 0;
	u8				value = 0;
	u32				offset = 0;
	u32				pollingCount = 0; /*  polling autoload done. */
	u32				maxPollingCnt = 5000;

	do {
		PwrCfgCmd = PwrSeqCmd[AryIdx];

		RT_TRACE(_module_hal_init_c_ , _drv_info_,
				 ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
					GET_PWR_CFG_OFFSET(PwrCfgCmd),
					GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
					GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
					GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
					GET_PWR_CFG_BASE(PwrCfgCmd),
					GET_PWR_CFG_CMD(PwrCfgCmd),
					GET_PWR_CFG_MASK(PwrCfgCmd),
					GET_PWR_CFG_VALUE(PwrCfgCmd)));

		/* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
		if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
		    (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
		    (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
			switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
			case PWR_CMD_READ:
				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
				break;
			case PWR_CMD_WRITE:
				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);

				/*  Read the value from system register */
				value = rtw_read8(padapter, offset);

				value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
				value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));

				/*  Write the value back to sytem register */
				rtw_write8(padapter, offset, value);
				break;
			case PWR_CMD_POLLING:
				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));

				bPollingBit = false;
				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
				do {
						value = rtw_read8(padapter, offset);

					value &= GET_PWR_CFG_MASK(PwrCfgCmd);
					if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
						bPollingBit = true;
					else
						rtw_udelay_os(10);

					if (pollingCount++ > maxPollingCnt) {
						DBG_88E("Fail to polling Offset[%#x]\n", offset);
						return false;
					}
				} while (!bPollingBit);

				break;
			case PWR_CMD_DELAY:
				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
				if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
					rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
				else
					rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
				break;
			case PWR_CMD_END:
				/*  When this command is parsed, end the process */
				RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
				return true;
				break;
			default:
				RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
				break;
			}
		}

		AryIdx++;/* Add Array Index */
	}while (1);

	return true;
}
コード例 #8
0
ファイル: HalPwrSeqCmd.c プロジェクト: RainMark/rtl8723bs
u8 HalPwrSeqCmdParsing(
	struct adapter *padapter,
	u8 CutVersion,
	u8 FabVersion,
	u8 InterfaceType,
	WLAN_PWR_CFG PwrSeqCmd[]
)
{
	WLAN_PWR_CFG PwrCfgCmd = {0};
	u8 bPollingBit = false;
	u32 AryIdx = 0;
	u8 value = 0;
	u32 offset = 0;
	u32 pollingCount = 0; /*  polling autoload done. */
	u32 maxPollingCnt = 5000;

	do {
		PwrCfgCmd = PwrSeqCmd[AryIdx];

		RT_TRACE(
			_module_hal_init_c_,
			_drv_info_,
			(
				"HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
				GET_PWR_CFG_OFFSET(PwrCfgCmd),
				GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
				GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
				GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
				GET_PWR_CFG_BASE(PwrCfgCmd),
				GET_PWR_CFG_CMD(PwrCfgCmd),
				GET_PWR_CFG_MASK(PwrCfgCmd),
				GET_PWR_CFG_VALUE(PwrCfgCmd)
			)
		);

		/* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
		if (
			(GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
			(GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
			(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)
		) {
			switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
			case PWR_CMD_READ:
				RT_TRACE(
					_module_hal_init_c_,
					_drv_info_,
					("HalPwrSeqCmdParsing: PWR_CMD_READ\n")
				);
				break;

			case PWR_CMD_WRITE:
				RT_TRACE(
					_module_hal_init_c_,
					_drv_info_,
					("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n")
				);
				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);

				/*  */
				/*  <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
				/*  2011.07.07. */
				/*  */
				if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
					/*  Read Back SDIO Local value */
					value = SdioLocalCmd52Read1Byte(padapter, offset);

					value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
					value |= (
						GET_PWR_CFG_VALUE(PwrCfgCmd) &
						GET_PWR_CFG_MASK(PwrCfgCmd)
					);

					/*  Write Back SDIO Local value */
					SdioLocalCmd52Write1Byte(padapter, offset, value);
				} else {
					/*  Read the value from system register */
					value = rtw_read8(padapter, offset);

					value &= (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
					value |= (
						GET_PWR_CFG_VALUE(PwrCfgCmd)
						&GET_PWR_CFG_MASK(PwrCfgCmd)
					);

					/*  Write the value back to sytem register */
					rtw_write8(padapter, offset, value);
				}
				break;

			case PWR_CMD_POLLING:
				RT_TRACE(
					_module_hal_init_c_,
					_drv_info_,
					("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n")
				);

				bPollingBit = false;
				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
				do {
					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
						value = SdioLocalCmd52Read1Byte(padapter, offset);
					else
						value = rtw_read8(padapter, offset);

					value = value&GET_PWR_CFG_MASK(PwrCfgCmd);
					if (
						value == (GET_PWR_CFG_VALUE(PwrCfgCmd) &
						GET_PWR_CFG_MASK(PwrCfgCmd))
					)
						bPollingBit = true;
					else
						udelay(10);

					if (pollingCount++ > maxPollingCnt) {
						DBG_871X(
							"Fail to polling Offset[%#x]=%02x\n",
							offset,
							value
						);
						return false;
					}
				} while (!bPollingBit);

				break;

			case PWR_CMD_DELAY:
				RT_TRACE(
					_module_hal_init_c_,
					_drv_info_,
					("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n")
				);
				if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
					udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd));
				else
					udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
				break;

			case PWR_CMD_END:
				/*  When this command is parsed, end the process */
				RT_TRACE(
					_module_hal_init_c_,
					_drv_info_,
					("HalPwrSeqCmdParsing: PWR_CMD_END\n")
				);
				return true;

			default:
				RT_TRACE(
					_module_hal_init_c_,
					_drv_err_,
					("HalPwrSeqCmdParsing: Unknown CMD!!\n")
				);
				break;
			}
		}

		AryIdx++;/* Add Array Index */
	} while (1);

	return true;
}