static int puv3_gpio_type(struct irq_data *d, unsigned int type)
{
unsigned int mask;
if (d->irq < IRQ_GPIOHIGH)
mask = 1 << d->irq;
else
mask = GPIO_MASK(d->irq);
if (type == IRQ_TYPE_PROBE) {
if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
return 0;
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
if (type & IRQ_TYPE_EDGE_RISING)
GPIO_IRQ_rising_edge |= mask;
else
GPIO_IRQ_rising_edge &= ~mask;
if (type & IRQ_TYPE_EDGE_FALLING)
GPIO_IRQ_falling_edge |= mask;
else
GPIO_IRQ_falling_edge &= ~mask;
writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
return 0;
}
static int puv3_gpio_type(unsigned int irq, unsigned int type)
{
unsigned int mask;
if (irq < IRQ_GPIOHIGH)
mask = 1 << irq;
else
mask = GPIO_MASK(irq);
if (type == IRQ_TYPE_PROBE) {
if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
return 0;
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
if (type & IRQ_TYPE_EDGE_RISING) {
GPIO_IRQ_rising_edge |= mask;
} else
GPIO_IRQ_rising_edge &= ~mask;
if (type & IRQ_TYPE_EDGE_FALLING) {
GPIO_IRQ_falling_edge |= mask;
} else
GPIO_IRQ_falling_edge &= ~mask;
GPIO_GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
GPIO_GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
return 0;
}
unsigned int
gpio_get (unsigned int pin)
{
gpio_init_inpin(pin);
volatile unsigned int *Reg = (GPIO_BANK(pin) + 0x10);
return (((*Reg) & GPIO_MASK(pin)) != 0);
}
static void puv3_high_gpio_unmask(unsigned int irq)
{
unsigned int mask = GPIO_MASK(irq);
GPIO_IRQ_mask |= mask;
GPIO_GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
GPIO_GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
}
static void puv3_high_gpio_mask(unsigned int irq)
{
unsigned int mask = GPIO_MASK(irq);
GPIO_IRQ_mask &= ~mask;
GPIO_GRER &= ~mask;
GPIO_GFER &= ~mask;
}
static void puv3_high_gpio_mask(struct irq_data *d)
{
unsigned int mask = GPIO_MASK(d->irq);
GPIO_IRQ_mask &= ~mask;
writel(readl(GPIO_GRER) & ~mask, GPIO_GRER);
writel(readl(GPIO_GFER) & ~mask, GPIO_GFER);
}
static void puv3_high_gpio_unmask(struct irq_data *d)
{
unsigned int mask = GPIO_MASK(d->irq);
GPIO_IRQ_mask |= mask;
writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
}
/**
* gpio read
*
* Reads the specified pin.
*
* @param pin Pin number to read
*
* @return int 0: low, 1: high
*/
int gpio_read(int pin)
{
int port;
uint32_t mcu_pin_mask;
port = GPIO_PORT(pin);
mcu_pin_mask = GPIO_MASK(pin);
return HAL_GPIO_ReadPin(portmap[port], mcu_pin_mask);
}
/**
* gpio clear
*
* Sets specified pin to 0 (low).
*
* @param pin
*/
void gpio_clear(int pin)
{
int port;
uint32_t mcu_pin_mask;
port = GPIO_PORT(pin);
mcu_pin_mask = GPIO_MASK(pin);
HAL_GPIO_WritePin(portmap[port], mcu_pin_mask, GPIO_PIN_RESET);
}
/**
* gpio read
*
* Reads the specified pin.
*
* @param pin Pin number to read
*
* @return int 0: low, 1: high
*/
int
gpio_read(int pin)
{
int port;
uint32_t mcu_pin_mask;
port = GPIO_PORT(pin);
mcu_pin_mask = GPIO_MASK(pin);
return GPIO_ReadInputDataBit(portmap[port], mcu_pin_mask);
}
/**
* gpio write
*
* Write a value (either high or low) to the specified pin.
*
* @param pin Pin to set
* @param val Value to set pin (0:low 1:high)
*/
void
gpio_write(int pin, int val)
{
int port;
uint32_t mcu_pin_mask;
port = GPIO_PORT(pin);
mcu_pin_mask = GPIO_MASK(pin);
GPIO_WriteBit(portmap[port], mcu_pin_mask, val);
}
/**
* gpio irq disable
*
*
* @param pin
*/
void
gpio_irq_disable(int pin)
{
uint32_t ctx;
uint32_t mask;
mask = GPIO_MASK(pin);
__HAL_DISABLE_INTERRUPTS(ctx);
EXTI->IMR &= ~mask;
__HAL_ENABLE_INTERRUPTS(ctx);
}
static void xgene_gpio_set_bit(struct gpio_chip *gc,
void __iomem *reg, u32 gpio, int val)
{
u32 data;
data = gc->read_reg(reg);
if (val)
data |= GPIO_MASK(gpio);
else
data &= ~GPIO_MASK(gpio);
gc->write_reg(reg, data);
}
void
gpio_init_inpin (unsigned int pin)
{
SYSCFG_UNLOCK;
gpio_init_pin(pin);
// set direction
GPIO_DIR(pin) |= GPIO_MASK(pin);
SYSCFG_LOCK;
}
void
gpio_init_outpin (unsigned int pin)
{
SYSCFG_UNLOCK;
gpio_init_pin(pin);
// clear pin data and set direction
GPIO_CLR(pin) = GPIO_MASK(pin);
GPIO_DIR(pin) &= ~GPIO_MASK(pin);
SYSCFG_LOCK;
}
adc_init (void)
{
// init adc power pins
gpio_init_pin(GPIO_PIN(6, 14)); // 5VONIGEN
gpio_init_pin(GPIO_PIN(0, 6)); // ADCBATEN
// enable battery power on adc
GPIO_SET(GPIO_PIN(0, 6)) = GPIO_MASK(GPIO_PIN(0, 6));
GPIO_DIR(GPIO_PIN(0, 6)) &= ~GPIO_MASK(GPIO_PIN(0, 6));
spi_update(0x400F);
spi_update(0x400F);
spi_update(0x400F);
spi_update(0x400F);
spi_update(0x400F);
spi_update(0x400F);
}
/**
* gpio irq release
*
* No longer interrupt when something occurs on the pin. NOTE: this function
* does not change the GPIO push/pull setting nor does it change the
* SYSCFG EXTICR registers. It also does not disable the NVIC interrupt enable
* setting for the irq.
*
* @param pin
*/
void
gpio_irq_release(int pin)
{
int index;
uint32_t pin_mask;
/* Disable the interrupt */
gpio_irq_disable(pin);
/* Clear any pending interrupts */
pin_mask = GPIO_MASK(pin);
EXTI_ClearFlag(pin_mask);
/* Clear out the irq handler */
index = GPIO_INDEX(pin);
gpio_irq_handlers[index].arg = NULL;
gpio_irq_handlers[index].isr = NULL;
}
/**
* hal gpio init
*
* Called to initialize a gpio.
*
* @param pin
* @param cfg
*
* @return int
*/
static int
hal_gpio_init(int pin, GPIO_InitTypeDef *cfg)
{
int port;
uint32_t mcu_pin_mask;
/* Is this a valid pin? */
port = GPIO_PORT(pin);
if (port >= HAL_GPIO_NUM_PORTS) {
return -1;
}
mcu_pin_mask = GPIO_MASK(pin);
cfg->GPIO_Pin = mcu_pin_mask;
/* Enable the GPIO clockl */
hal_gpio_clk_enable(port);
/* Initialize pin as an input, setting proper mode */
GPIO_Init(portmap[port], cfg);
return 0;
}
/**
* gpio irq init
*
* Initialize an external interrupt on a gpio pin
*
* @param pin Pin number to enable gpio.
* @param handler Interrupt handler
* @param arg Argument to pass to interrupt handler
* @param trig Trigger mode of interrupt
* @param pull Push/pull mode of input.
*
* @return int
*/
int
gpio_irq_init(int pin, gpio_irq_handler_t handler, void *arg,
gpio_irq_trig_t trig, enum gpio_pull pull)
{
int rc;
int irqn;
int index;
uint32_t pin_mask;
EXTI_InitTypeDef exti_cfg;
/* Configure the gpio for an external interrupt */
rc = 0;
pin_mask = GPIO_MASK(pin);
index = GPIO_INDEX(pin);
exti_cfg.EXTI_Line = index;
exti_cfg.EXTI_Mode = EXTI_Mode_Interrupt;
switch (trig) {
case GPIO_TRIG_NONE:
rc = -1;
break;
case GPIO_TRIG_RISING:
exti_cfg.EXTI_Trigger = EXTI_Trigger_Rising;
break;
case GPIO_TRIG_FALLING:
exti_cfg.EXTI_Trigger = EXTI_Trigger_Falling;
break;
case GPIO_TRIG_BOTH:
exti_cfg.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
break;
case GPIO_TRIG_LOW:
rc = -1;
break;
case GPIO_TRIG_HIGH:
rc = -1;
break;
default:
rc = -1;
break;
}
exti_cfg.EXTI_LineCmd = ENABLE;
/* Check to make sure no error has occurred */
if (!rc) {
/* Disable interrupt and clear any pending */
gpio_irq_disable(pin);
EXTI_ClearFlag(pin_mask);
gpio_init_in(pin, pull);
/* Configure SYSCFG */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
/* Configure EXTI */
SYSCFG_EXTILineConfig(GPIO_PORT(pin), index);
EXTI_Init(&exti_cfg);
/* Set the gpio irq handler */
gpio_irq_handlers[index].isr = handler;
gpio_irq_handlers[index].arg = arg;
/* Configure the GPIO */
if (!rc) {
/* Enable interrupt vector in NVIC */
irqn = hal_gpio_pin_to_irq(pin);
hal_gpio_set_nvic(irqn);
}
}
return rc;
}
/**
* gpio irq init
*
* Initialize an external interrupt on a gpio pin
*
* @param pin Pin number to enable gpio.
* @param handler Interrupt handler
* @param arg Argument to pass to interrupt handler
* @param trig Trigger mode of interrupt
* @param pull Push/pull mode of input.
*
* @return int
*/
int
gpio_irq_init(int pin, gpio_irq_handler_t handler, void *arg,
gpio_irq_trig_t trig, gpio_pull_t pull)
{
int rc;
int irqn;
int index;
uint32_t pin_mask;
uint32_t mode;
GPIO_InitTypeDef init_cfg;
/* Configure the gpio for an external interrupt */
rc = 0;
switch (trig) {
case GPIO_TRIG_NONE:
rc = -1;
break;
case GPIO_TRIG_RISING:
mode = GPIO_MODE_IT_RISING;
break;
case GPIO_TRIG_FALLING:
mode = GPIO_MODE_IT_FALLING;
break;
case GPIO_TRIG_BOTH:
mode = GPIO_MODE_IT_RISING_FALLING;
break;
case GPIO_TRIG_LOW:
rc = -1;
break;
case GPIO_TRIG_HIGH:
rc = -1;
break;
default:
rc = -1;
break;
}
/* Check to make sure no error has occurred */
if (!rc) {
/* Disable interrupt and clear any pending */
gpio_irq_disable(pin);
pin_mask = GPIO_MASK(pin);
__HAL_GPIO_EXTI_CLEAR_FLAG(pin_mask);
/* Set the gpio irq handler */
index = GPIO_INDEX(pin);
gpio_irq_handlers[index].isr = handler;
gpio_irq_handlers[index].arg = arg;
/* Configure the GPIO */
init_cfg.Mode = mode;
init_cfg.Pull = pull;
rc = hal_gpio_init(pin, &init_cfg);
if (!rc) {
/* Enable interrupt vector in NVIC */
irqn = hal_gpio_pin_to_irq(pin);
hal_gpio_set_nvic(irqn);
}
}
return rc;
}
void
gpio_set (unsigned int pin, unsigned int value)
{
gpio_init_outpin(pin);
*((volatile unsigned int*)(GPIO_BANK(pin) + 8 + (!value) * 4)) = GPIO_MASK(pin);
}
#include <linux/tty.h>
#include <asm/hardware.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/serial_sa1100.h>
#include "generic.h"
static spinlock_t egpio_lock = SPIN_LOCK_UNLOCKED;
static unsigned long yopy_egpio =
GPIO_MASK(GPIO_CF_RESET) |
GPIO_MASK(GPIO_CLKDIV_CLR1) | GPIO_MASK(GPIO_CLKDIV_CLR2) |
GPIO_MASK(GPIO_SPEAKER_MUTE) | GPIO_MASK(GPIO_AUDIO_OPAMP_POWER);
int yopy_gpio_test(unsigned int gpio)
{
return ((yopy_egpio & (1 << gpio)) != 0);
}
void yopy_gpio_set(unsigned int gpio, int level)
{
unsigned long flags, mask;
mask = 1 << gpio;
spin_lock_irqsave(&egpio_lock, flags);
/*
* GPIO0-27 edge IRQs need to be handled specially.
* In addition, the IRQs are all collected up into one bit in the
* interrupt controller registers.
*/
static void puv3_high_gpio_ack(unsigned int irq)
{
unsigned int mask = GPIO_MASK(irq);
GPIO_GEDR = mask;
}
/*
* GPIO0-27 edge IRQs need to be handled specially.
* In addition, the IRQs are all collected up into one bit in the
* interrupt controller registers.
*/
static void puv3_high_gpio_ack(struct irq_data *d)
{
unsigned int mask = GPIO_MASK(d->irq);
writel(mask, GPIO_GEDR);
}
