void psxRcntUpdate()
{
u32 cycle;
cycle = psxRegs.cycle;
// rcnt 0.
if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
psxRcntReset( 0 );
// rcnt 1.
if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
psxRcntReset( 1 );
// rcnt 2.
if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
psxRcntReset( 2 );
// rcnt base.
if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
{
u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
u32 next_vsync;
hSyncCount += hsync_steps;
// VSync irq.
if( hSyncCount == VBlankStart )
{
HW_GPU_STATUS &= ~PSXGPU_LCF;
GPU_vBlank( 1, 0 );
setIrq( 0x01 );
EmuUpdate();
GPU_updateLace();
if( SPU_async )
{
SPU_async( cycle, 1 );
}
}
// Update lace. (with InuYasha fix)
if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
{
hSyncCount = 0;
frame_counter++;
gpuSyncPluginSR();
if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
HW_GPU_STATUS |= frame_counter << 31;
GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
}
void psxRcntUpdate()
{
u32 cycle;
cycle = psxRegs.cycle;
// rcnt 0.
if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
{
psxRcntReset( 0 );
}
// rcnt 1.
if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
{
psxRcntReset( 1 );
}
// rcnt 2.
if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
{
psxRcntReset( 2 );
}
// rcnt base.
if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
{
psxRcntReset( 3 );
spuSyncCount++;
hSyncCount++;
// Update spu.
if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
{
spuSyncCount = 0;
if( SPU_async )
{
SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
}
}
// VSync irq.
if( hSyncCount == VBlankStart[Config.PsxType] )
{
GPU_vBlank( 1 );
// For the best times. :D
//setIrq( 0x01 );
}
// Update lace. (with InuYasha fix)
if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
{
hSyncCount = 0;
GPU_vBlank( 0 );
setIrq( 0x01 );
GPU_updateLace();
EmuUpdate();
}
}
#ifndef LIBXENON
DebugVSync();
#endif
}
void psxRcntUpdate()
{
u32 cycle;
cycle = psxRegs.cycle;
// rcnt 0.
if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
{
psxRcntReset( 0 );
}
// rcnt 1.
if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
{
psxRcntReset( 1 );
}
// rcnt 2.
if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
{
psxRcntReset( 2 );
}
// rcnt base.
if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
{
psxRcntReset( 3 );
GPU_hSync(hSyncCount);
spuSyncCount++;
hSyncCount++;
// Update spu.
if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
{
spuSyncCount = 0;
if( SPU_async )
{
SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
}
}
#ifdef ENABLE_SIO1API
if( SIO1_update )
{
SIO1_update( 0 );
}
#endif
// VSync irq.
if( hSyncCount == VBlankStart[Config.PsxType] )
{
GPU_vBlank( 1 );
// For the best times. :D
//setIrq( 0x01 );
}
// Update lace. (calculated at psxHsyncCalculate() on init/defreeze)
if( hSyncCount >= HSyncTotal[Config.PsxType] )
{
hSyncCount = 0;
GPU_vBlank( 0 );
setIrq( 0x01 );
GPU_updateLace();
EmuUpdate();
}
}
DebugVSync();
}
void psxRcntUpdate()
{
#ifdef DEBUG_ANALYSIS
dbg_anacnt_psxRcntUpdate++;
#endif
pcsx4all_prof_start_with_pause(PCSX4ALL_PROF_COUNTERS,PCSX4ALL_PROF_CPU);
u32 cycle;
cycle = psxRegs.cycle;
#ifdef USE_EXTRA_IO_CYCLES
// CHUI: Añado ResetIoCycle para permite que en el proximo salto entre en psxBranchTest
ResetIoCycle();
#endif
// rcnt 0.
if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
{
psxRcntReset( 0 );
}
// rcnt 1.
if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
{
psxRcntReset( 1 );
}
// rcnt 2.
if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
{
psxRcntReset( 2 );
}
// rcnt base.
if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
{
psxRcntReset( 3 );
spuSyncCount++;
hSyncCount++;
// Update spu.
if( spuSyncCount >= SPU_UPD_INTERVAL )
{
spuSyncCount = 0;
SPU_async();
}
/*
// For the best times. :D
// VSync irq.
if( hSyncCount == VBlankStart[Config.PsxType] )
{
setIrq( 0x01 );
}
*/
// Update lace. (with InuYasha fix)
if( hSyncCount >= (Config.VSyncWA ? UDIV(HSyncTotal[Config.PsxType],BIAS) : HSyncTotal[Config.PsxType]) )
{
#ifdef DEBUG_BIOS
dbg("UpdateLace");
#endif
hSyncCount = 0;
setIrq( 0x01 );
GPU_updateLace();
pad_update();
#ifdef DEBUG_END_FRAME
{
static unsigned _endframe_=0;
static unsigned _frametime_[DEBUG_END_FRAME+1];
_frametime_[_endframe_]=(get_ticks()
#ifndef TIME_IN_MSEC
/1000
#endif
);
_endframe_++;
if (_endframe_>DEBUG_END_FRAME) {
unsigned i;
for(i=1;i<_endframe_;i++)
printf("FRAME %u = %u msec\n",i,_frametime_[i]-_frametime_[i-1]);
pcsx4all_exit();
}
}
#endif
if ((toSaveState)&&(SaveState_filename)) {
toSaveState=0;
SaveState(SaveState_filename);
if (toExit)
pcsx4all_exit();
}
if ((toLoadState)&&(SaveState_filename))
{
toLoadState=0;
LoadState(SaveState_filename);
pcsx4all_prof_reset();
#ifdef PROFILER_PCSX4ALL
_pcsx4all_prof_end(PCSX4ALL_PROF_CPU,0);
#endif
pcsx4all_prof_start(PCSX4ALL_PROF_CPU);
psxCpu->Execute();
pcsx4all_prof_end(PCSX4ALL_PROF_CPU);
pcsx4all_exit();
}
}
}
pcsx4all_prof_end_with_resume(PCSX4ALL_PROF_COUNTERS,PCSX4ALL_PROF_CPU);
}
