void gsc_pixelasync_sw_reset(struct gsc_dev *dev) { u32 cfg = readl(SYSREG_GSCBLK_CFG0); /* GSCBLK Pixel asyncy FIFO S/W reset sequence set PXLASYNC_SW_RESET as 0 then, set PXLASYNC_SW_RESET as 1 again */ cfg &= ~GSC_PXLASYNC_RST(dev->id); writel(cfg, SYSREG_GSCBLK_CFG0); cfg |= GSC_PXLASYNC_RST(dev->id); writel(cfg, SYSREG_GSCBLK_CFG0); }
void gsc_hw_set_pixelasync_reset_output(struct gsc_dev *dev) { u32 cfg = readl(SYSREG_GSCBLK_CFG0); cfg |= GSC_PXLASYNC_MASK_ALL; cfg &= ~GSC_PXLASYNC_MASK(dev->id); writel(cfg, SYSREG_GSCBLK_CFG0); /* GSCBLK Pixel asyncy FIFO S/W reset sequence set PXLASYNC_SW_RESET as 0 then, set PXLASYNC_SW_RESET as 1 again */ cfg &= ~GSC_PXLASYNC_RST(dev->id); writel(cfg, SYSREG_GSCBLK_CFG0); cfg |= GSC_PXLASYNC_RST(dev->id); writel(cfg, SYSREG_GSCBLK_CFG0); /* This is for prohibit of reset signal DISP0 */ cfg |= GSC_PXLASYNC_MASK_ALL; writel(cfg, SYSREG_GSCBLK_CFG0); }