/** * * A sub-function extracts WL and HW RxEn seeds from PSCFG tables * from a input table * * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK * * @return NBPtr->PsPtr->WLSeedVal * @return NBPtr->PsPtr->HWRxENSeedVal * */ BOOLEAN MemPGetTrainingSeeds ( IN OUT MEM_NB_BLOCK *NBPtr, IN MEM_PSC_TABLE_BLOCK *EntryOfTables ) { UINT8 i; UINT8 MaxDimmPerCh; UINT8 NOD; UINT8 TableSize; DIMM_TYPE DimmType; CPU_LOGICAL_ID LogicalCpuid; UINT8 PackageType; UINT8 Seedloop; UINT8 CH; PSC_TBL_ENTRY **TblEntryPtr; PSCFG_SEED_ENTRY *TblPtr; CH_DEF_STRUCT *CurrentChannel; CurrentChannel = NBPtr->ChannelPtr; TblEntryPtr = NULL; TblPtr = NULL; TableSize = 0; PackageType = 0; LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); NOD = (UINT8) 1 << (MaxDimmPerCh - 1); CH = 1 << (CurrentChannel->ChannelID); if (CurrentChannel->RegDimmPresent != 0) { DimmType = RDIMM_TYPE; } else if (CurrentChannel->SODimmPresent != 0) { DimmType = SODIMM_TYPE; if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { DimmType = SODWN_SODIMM_TYPE; } } else if (CurrentChannel->LrDimmPresent != 0) { DimmType = LRDIMM_TYPE; } else { DimmType = UDIMM_TYPE; } // Get seed value of WL, then HW RxEn for (Seedloop = 0; Seedloop < 2; Seedloop++) { TblEntryPtr = (Seedloop == 0) ? EntryOfTables->TblEntryOfWLSeed : EntryOfTables->TblEntryOfHWRxENSeed; i = 0; // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. while (TblEntryPtr[i] != NULL) { if (((TblEntryPtr[i])->Header.DimmType & DimmType) != 0) { // // Determine if this is the expected NB Type // LogicalCpuid = (TblEntryPtr[i])->Header.LogicalCpuid; PackageType = (TblEntryPtr[i])->Header.PackageType; if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { TblPtr = (PSCFG_SEED_ENTRY *) ((TblEntryPtr[i])->TBLPtr); TableSize = (TblEntryPtr[i])->TableSize; break; } } i++; } // Check whether no table entry is found. if (TblEntryPtr[i] == NULL) { IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s training seeds Config table\n", (Seedloop == 0) ? "WL" : "HW RxEn"); return FALSE; } for (i = 0; i < TableSize; i++) { if ((TblPtr->DimmPerCh & NOD) != 0) { if ((TblPtr->Channel & CH) != 0) { if (Seedloop == 0) { NBPtr->PsPtr->WLSeedVal = (UINT8) TblPtr->SeedVal; } else { NBPtr->PsPtr->HWRxENSeedVal = TblPtr->SeedVal; } break; } } TblPtr++; } if (i == TableSize) { IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s seed entries\n\n", (Seedloop == 0) ? "WL" : "HW RxEn"); PutEventLog (AGESA_ERROR, MEM_ERROR_TRAINING_SEED_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); SetMemError (AGESA_ERROR, NBPtr->MCTPtr); if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { ASSERT (FALSE); } return FALSE; } } return TRUE; }
/** * * A sub-function which extracts Slow mode, Address timing and Output driver compensation value * from a input table and store those value to a specific address. * * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK * * @return TRUE - Table values can be extracted per dimm population and ranks type. * @return FALSE - Table values cannot be extracted per dimm population and ranks type. * */ BOOLEAN MemPGetSAO ( IN OUT MEM_NB_BLOCK *NBPtr, IN MEM_PSC_TABLE_BLOCK *EntryOfTables ) { UINT8 i; UINT8 MaxDimmPerCh; UINT8 NOD; UINT8 TableSize; UINT32 CurDDRrate; UINT8 DDR3Voltage; UINT16 RankTypeOfPopulatedDimm; UINT16 RankTypeInTable; UINT8 PsoMaskSAO; DIMM_TYPE DimmType; CPU_LOGICAL_ID LogicalCpuid; UINT8 PackageType; PSCFG_SAO_ENTRY *TblPtr; CH_DEF_STRUCT *CurrentChannel; CurrentChannel = NBPtr->ChannelPtr; TblPtr = NULL; TableSize = 0; PackageType = 0; LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); NOD = (UINT8) 1 << (MaxDimmPerCh - 1); if (CurrentChannel->RegDimmPresent != 0) { DimmType = RDIMM_TYPE; } else if (CurrentChannel->SODimmPresent != 0) { DimmType = SODIMM_TYPE; if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { DimmType = SODWN_SODIMM_TYPE; } } else if (CurrentChannel->LrDimmPresent != 0) { DimmType = LRDIMM_TYPE; } else { DimmType = UDIMM_TYPE; } i = 0; // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. while (EntryOfTables->TblEntryOfSAO[i] != NULL) { if (((EntryOfTables->TblEntryOfSAO[i])->Header.DimmType & DimmType) != 0) { if (((EntryOfTables->TblEntryOfSAO[i])->Header.NumOfDimm & NOD) != 0) { // // Determine if this is the expected NB Type // LogicalCpuid = (EntryOfTables->TblEntryOfSAO[i])->Header.LogicalCpuid; PackageType = (EntryOfTables->TblEntryOfSAO[i])->Header.PackageType; if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { TblPtr = (PSCFG_SAO_ENTRY *) ((EntryOfTables->TblEntryOfSAO[i])->TBLPtr); TableSize = (EntryOfTables->TblEntryOfSAO[i])->TableSize; break; } } } i++; } // Check whether no table entry is found. if (EntryOfTables->TblEntryOfSAO[i] == NULL) { IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowAccMode, AddrTmg and ODCCtrl table\n"); return FALSE; } CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); for (i = 0; i < TableSize; i++) { MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); if (TblPtr->DimmPerCh == MaxDimmPerCh) { if ((TblPtr->DDRrate & CurDDRrate) != 0) { if ((TblPtr->VDDIO & DDR3Voltage) != 0) { if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { CurrentChannel->DctAddrTmg = TblPtr->AddTmgCtl; CurrentChannel->DctOdcCtl = TblPtr->ODC; CurrentChannel->SlowMode = (TblPtr->SlowMode == 1) ? TRUE : FALSE; break; } } } } TblPtr++; } // // If there is no entry, check if overriding values (SlowAccMode, AddrTmg and ODCCtrl) existed. If not, show no entry found. // PsoMaskSAO = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_SLOWACCMODE); PsoMaskSAO &= (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ODCCTRL); PsoMaskSAO &= (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ADDRTMG); if ((PsoMaskSAO == 0) && (i == TableSize)) { IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowAccMode, AddrTmg and ODCCtrl entries\n"); } else { return TRUE; } if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) { return TRUE; } PutEventLog (AGESA_ERROR, MEM_ERROR_SAO_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); SetMemError (AGESA_ERROR, NBPtr->MCTPtr); if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { ASSERT (FALSE); } return FALSE; }
/** * * A sub-function which extracts the value of max frequency supported from a input table and * compares it with DCTPtr->Timings.TargetSpeed * * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK * * @return TRUE - Succeed in extracting the table value * @return FALSE - Fail to extract the table value * */ BOOLEAN MemPGetMaxFreqSupported ( IN OUT MEM_NB_BLOCK *NBPtr, IN MEM_PSC_TABLE_BLOCK *EntryOfTables ) { UINT8 i; UINT8 MaxDimmSlotPerCh; UINT8 MaxDimmPerCh; UINT8 NOD; UINT8 TableSize; PSCFG_TYPE Type; UINT16 CDN; UINT16 MaxFreqSupported; UINT16 *SpeedArray; UINT8 DDR3Voltage; UINT8 CurrentVoltage; DIMM_TYPE DimmType; CPU_LOGICAL_ID LogicalCpuid; UINT8 PackageType; BOOLEAN DisDct; UINT8 PsoMaskMaxFreq; UINT16 PsoMaskMaxFreq16; UINT8 NumDimmSlotInTable; UINT16 DimmPopInTable; PSCFG_MAXFREQ_ENTRY *TblPtr; CH_DEF_STRUCT *CurrentChannel; PSC_TBL_ENTRY **TblEntryOfMaxFreq; CurrentChannel = NBPtr->ChannelPtr; DisDct = FALSE; Type = PSCFG_MAXFREQ; TblPtr = NULL; TableSize = 0; PackageType = 0; NumDimmSlotInTable = 0; DimmPopInTable = 0; LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; SpeedArray = NULL; MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); MaxDimmSlotPerCh = MaxDimmPerCh - GetMaxSolderedDownDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); if (CurrentChannel->RegDimmPresent != 0) { DimmType = RDIMM_TYPE; } else if (CurrentChannel->SODimmPresent != 0) { DimmType = SODIMM_TYPE; } else if (CurrentChannel->LrDimmPresent != 0) { DimmType = LRDIMM_TYPE; } else { DimmType = UDIMM_TYPE; } // Check if it is "SODIMM plus soldered-down DRAM" or "Soldered-down DRAM only" configuration, // DimmType is changed to 'SODWN_SODIMM_TYPE' if soldered-down DRAM exist if (MaxDimmSlotPerCh != MaxDimmPerCh) { // SODIMM plus soldered-down DRAM DimmType = SODWN_SODIMM_TYPE; } else if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { // Soldered-down DRAM only DimmType = SODWN_SODIMM_TYPE; MaxDimmSlotPerCh = 0; } NOD = (UINT8) (MaxDimmSlotPerCh != 0) ? (1 << (MaxDimmSlotPerCh - 1)) : _DIMM_NONE; TblEntryOfMaxFreq = EntryOfTables->TblEntryOfMaxFreq; IDS_OPTION_HOOK (IDS_GET_STRETCH_FREQUENCY_LIMIT, &TblEntryOfMaxFreq, &NBPtr->MemPtr->StdHeader); i = 0; // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. while (TblEntryOfMaxFreq[i] != NULL) { if (((TblEntryOfMaxFreq[i])->Header.DimmType & DimmType) != 0) { if (((TblEntryOfMaxFreq[i])->Header.NumOfDimm & NOD) != 0) { // // Determine if this is the expected NB Type // LogicalCpuid = (TblEntryOfMaxFreq[i])->Header.LogicalCpuid; PackageType = (TblEntryOfMaxFreq[i])->Header.PackageType; if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { TblPtr = (PSCFG_MAXFREQ_ENTRY *) ((TblEntryOfMaxFreq[i])->TBLPtr); TableSize = (TblEntryOfMaxFreq[i])->TableSize; Type = (TblEntryOfMaxFreq[i])->Header.PSCType; break; } } } i++; } // Check whether no table entry is found. if (TblEntryOfMaxFreq[i] == NULL) { IDS_HDT_CONSOLE (MEM_FLOW, "\nDCT %d: No MaxFreq table. This channel will be disabled.\n", NBPtr->Dct); return FALSE; } MaxFreqSupported = UNSUPPORTED_DDR_FREQUENCY; CDN = 0; DDR3Voltage = (UINT8) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage); // Construct the condition value ((CDNMaxFreq *)&CDN)->Dimms = CurrentChannel->Dimms; if (Type == PSCFG_MAXFREQ) { for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { if ((CurrentChannel->DimmSRPresent & (UINT8) (1 << i)) != 0) { ((CDNMaxFreq *)&CDN)->SR += 1; } if ((CurrentChannel->DimmDrPresent & (UINT16) (1 << i)) != 0) { ((CDNMaxFreq *)&CDN)->DR += 1; } if ((CurrentChannel->DimmQrPresent & (UINT16) (1 << i)) != 0) { if (i < 2) { ((CDNMaxFreq *)&CDN)->QR += 1; } } } } else { ((CDNLMaxFreq *)&CDN)->LR = CurrentChannel->Dimms; } for (i = 0; i < TableSize; i++) { NumDimmSlotInTable = TblPtr->MAXFREQ_ENTRY.DimmSlotPerCh; DimmPopInTable = (Type == PSCFG_MAXFREQ) ? TblPtr->MAXFREQ_ENTRY.CDN : ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.CDN; if (((NumDimmSlotInTable & NOD) != 0) && (CDN == DimmPopInTable)) { if (Type == PSCFG_MAXFREQ) { SpeedArray = TblPtr->MAXFREQ_ENTRY.Speed; } else { SpeedArray = ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.Speed; } break; } TblPtr++; } PsoMaskMaxFreq16 = MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_SPEEDLIMIT); if ((PsoMaskMaxFreq16 & INVALID_CONFIG_FLAG) == 0) { PsoMaskMaxFreq = (UINT8) PsoMaskMaxFreq16; if (PsoMaskMaxFreq != 0) { SpeedArray = NBPtr->PsPtr->SpeedLimit; } } else { SpeedArray = NULL; } if (SpeedArray != NULL) { if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) { IDS_HDT_CONSOLE (MEM_FLOW, "\nCheck speed supported for each VDDIO for Node%d DCT%d: ", NBPtr->Node, NBPtr->Dct); for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { if (NBPtr->SharedPtr->VoltageMap & (1 << CurrentVoltage)) { IDS_HDT_CONSOLE (MEM_FLOW, "%s -> %dMHz ", (CurrentVoltage == VOLT1_5_ENCODED_VAL) ? "1.5V" : ((CurrentVoltage == VOLT1_35_ENCODED_VAL) ? "1.35V" : "1.25V"), SpeedArray[CurrentVoltage]); if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedArray[CurrentVoltage]) { MaxFreqSupported = SpeedArray[CurrentVoltage]; } else { MaxFreqSupported = NBPtr->DCTPtr->Timings.TargetSpeed; } if (NBPtr->MaxFreqVDDIO[CurrentVoltage] > MaxFreqSupported) { NBPtr->MaxFreqVDDIO[CurrentVoltage] = MaxFreqSupported; } } else { NBPtr->MaxFreqVDDIO[CurrentVoltage] = 0; } } IDS_HDT_CONSOLE (MEM_FLOW, "\n"); } ASSERT (DDR3Voltage <= VOLT1_25_ENCODED_VAL); MaxFreqSupported = SpeedArray[DDR3Voltage]; } if (MaxFreqSupported == UNSUPPORTED_DDR_FREQUENCY) { // No entry in the table for current dimm population is found IDS_HDT_CONSOLE (MEM_FLOW, "\nDCT %d: No entry is found in the Max Frequency table\n", NBPtr->Dct); DisDct = TRUE; } else if (MaxFreqSupported != 0) { if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxFreqSupported) { NBPtr->DCTPtr->Timings.TargetSpeed = MaxFreqSupported; } } else if (NBPtr->SharedPtr->VoltageMap == VDDIO_DETERMINED) { // Dimm population is not supported at current voltage // Also if there is no performance optimization, disable the DCT DisDct = TRUE; } if (DisDct) { NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid; PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); SetMemError (AGESA_ERROR, NBPtr->MCTPtr); // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; } return TRUE; }
/** * * A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input * table and stores extracted value to a specific address. * * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK * * @return TRUE - Succeed in extracting the table value * @return FALSE - Fail to extract the table value * */ BOOLEAN MemPGetLRIBT ( IN OUT MEM_NB_BLOCK *NBPtr, IN MEM_PSC_TABLE_BLOCK *EntryOfTables ) { UINT8 i; UINT8 MaxDimmPerCh; UINT8 NOD; UINT8 TableSize; UINT32 CurDDRrate; UINT8 DDR3Voltage; UINT16 RankTypeOfPopulatedDimm; UINT16 RankTypeInTable; UINT8 PsoMaskLRIBT; CPU_LOGICAL_ID LogicalCpuid; UINT8 PackageType; PSCFG_L_IBT_ENTRY *TblPtr; CH_DEF_STRUCT *CurrentChannel; CurrentChannel = NBPtr->ChannelPtr; if (CurrentChannel->LrDimmPresent == 0) { return TRUE; } TblPtr = NULL; TableSize = 0; PackageType = 0; LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); NOD = (UINT8) 1 << (MaxDimmPerCh - 1); i = 0; // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type. while (EntryOfTables->TblEntryOfLRIBT[i] != NULL) { if (((EntryOfTables->TblEntryOfLRIBT[i])->Header.NumOfDimm & NOD) != 0) { LogicalCpuid = (EntryOfTables->TblEntryOfLRIBT[i])->Header.LogicalCpuid; PackageType = (EntryOfTables->TblEntryOfLRIBT[i])->Header.PackageType; // // Determine if this is the expected NB Type // if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { TblPtr = (PSCFG_L_IBT_ENTRY *) ((EntryOfTables->TblEntryOfLRIBT[i])->TBLPtr); TableSize = (EntryOfTables->TblEntryOfLRIBT[i])->TableSize; break; } } i++; } // Check whether no table entry is found. if (EntryOfTables->TblEntryOfLRIBT[i] == NULL) { IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT table\n"); return FALSE; } CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); for (i = 0; i < TableSize; i++) { MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); if ((TblPtr->DimmPerCh & NOD) != 0) { if ((TblPtr->DDRrate & CurDDRrate) != 0) { if ((TblPtr->VDDIO & DDR3Voltage) != 0) { if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { NBPtr->PsPtr->F0RC8 = (UINT8) TblPtr->F0RC8; NBPtr->PsPtr->F1RC0 = (UINT8) TblPtr->F1RC0; NBPtr->PsPtr->F1RC1 = (UINT8) TblPtr->F1RC1; NBPtr->PsPtr->F1RC2 = (UINT8) TblPtr->F1RC2; break; } } } } TblPtr++; } // // If there is no entry, check if overriding value existed. If not, return FALSE // PsoMaskLRIBT = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_LRDIMM_IBT); if ((PsoMaskLRIBT == 0) && (i == TableSize)) { IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT entries\n"); PutEventLog (AGESA_ERROR, MEM_ERROR_LR_IBT_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); SetMemError (AGESA_ERROR, NBPtr->MCTPtr); if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { ASSERT (FALSE); } return FALSE; } return TRUE; }
VOID STATIC MemSPDDataProcess ( IN OUT MEM_DATA_STRUCT *MemPtr ) { UINT8 Socket; UINT8 Channel; UINT8 Dimm; UINT8 DimmIndex; UINT32 AgesaStatus; UINT8 MaxSockets; UINT8 MaxChannelsPerSocket; UINT8 MaxDimmsPerChannel; SPD_DEF_STRUCT *DimmSPDPtr; PSO_TABLE *PsoTable; ALLOCATE_HEAP_PARAMS AllocHeapParams; AGESA_READ_SPD_PARAMS SpdParam; ASSERT (MemPtr != NULL); MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ()); PsoTable = MemPtr->ParameterListPtr->PlatformMemoryConfiguration; // // Allocate heap for the table // AllocHeapParams.RequestedBufferSize = (GetSpdSocketIndex (PsoTable, MaxSockets, &MemPtr->StdHeader) * sizeof (SPD_DEF_STRUCT)); AllocHeapParams.BufferHandle = AMD_MEM_SPD_HANDLE; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) { MemPtr->SpdDataStructure = (SPD_DEF_STRUCT *) AllocHeapParams.BufferPtr; // // Initialize SpdParam Structure // LibAmdMemCopy ((VOID *)&SpdParam, (VOID *)MemPtr, (UINTN)sizeof (SpdParam.StdHeader), &MemPtr->StdHeader); // // Populate SPDDataBuffer // SpdParam.MemData = MemPtr; DimmIndex = 0; for (Socket = 0; Socket < (UINT16)MaxSockets; Socket++) { MaxChannelsPerSocket = GetMaxChannelsPerSocket (PsoTable, Socket, &MemPtr->StdHeader); SpdParam.SocketId = Socket; for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { SpdParam.MemChannelId = Channel; MaxDimmsPerChannel = GetMaxDimmsPerChannel (PsoTable, Socket, Channel); for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++) { SpdParam.DimmId = Dimm; DimmSPDPtr = &(MemPtr->SpdDataStructure[DimmIndex++]); SpdParam.Buffer = DimmSPDPtr->Data; AGESA_TESTPOINT (TpProcMemBeforeAgesaReadSpd, &MemPtr->StdHeader); AgesaStatus = AgesaReadSpd (0, &SpdParam); AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader); if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, (intptr_t)SpdParam.Buffer); } else { DimmSPDPtr->DimmPresent = FALSE; } } } } } else { PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, 0, 0, 0, 0, &MemPtr->StdHeader); // // Assert here if unable to allocate heap for SPDs // IDS_ERROR_TRAP; } }
/** * * A sub-function which extracts ODT Pattern value from a input table and stores extracted * value to a specific address. * * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK * * @return TRUE - Table values can be extracted per dimm population and ranks type. * @return FALSE - Table values cannot be extracted per dimm population and ranks type. * */ BOOLEAN MemPGetODTPattern ( IN OUT MEM_NB_BLOCK *NBPtr, IN MEM_PSC_TABLE_BLOCK *EntryOfTables ) { UINT8 i; UINT16 RankTypeInTable; UINT16 RankTypeOfPopulatedDimm; UINT8 MaxDimmPerCh; UINT8 NOD; UINT8 TableSize; DIMM_TYPE DimmType; CPU_LOGICAL_ID LogicalCpuid; UINT8 PackageType; PSCFG_3D_ODTPAT_ENTRY *TblPtr; CH_DEF_STRUCT *CurrentChannel; CurrentChannel = NBPtr->ChannelPtr; TblPtr = NULL; TableSize = 0; PackageType = 0; LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); NOD = (UINT8) 1 << (MaxDimmPerCh - 1); if (CurrentChannel->RegDimmPresent != 0) { DimmType = RDIMM_TYPE; } else if (CurrentChannel->SODimmPresent != 0) { DimmType = SODIMM_TYPE; //@todo LRDIMM //} else if (CurrentChannel->LrDimmPresent) { // DimmType = LRDIMM_TYPE; } else { DimmType = UDIMM_TYPE; } i = 0; // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. while (EntryOfTables->TblEntryOfODTPattern[i] != NULL) { if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.DimmType & DimmType) != 0) { if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.NumOfDimm & NOD) != 0) { // // Determine if this is the expected NB Type // LogicalCpuid = (EntryOfTables->TblEntryOfODTPattern[i])->Header.LogicalCpuid; PackageType = (EntryOfTables->TblEntryOfODTPattern[i])->Header.PackageType; if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { TblPtr = (PSCFG_3D_ODTPAT_ENTRY *) ((EntryOfTables->TblEntryOfODTPattern[i])->TBLPtr); TableSize = (EntryOfTables->TblEntryOfODTPattern[i])->TableSize; break; } } } i++; } // Check whether no table entry is found. if (EntryOfTables->TblEntryOfODTPattern[i] == NULL) { IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT table\n"); return FALSE; } RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); //@todo - LRDIMM ? for (i = 0; i < TableSize; i++) { MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { CurrentChannel->PhyRODTCSHigh = TblPtr->RdODTCSHigh; CurrentChannel->PhyRODTCSLow = TblPtr->RdODTCSLow; CurrentChannel->PhyWODTCSHigh = TblPtr->WrODTCSHigh; CurrentChannel->PhyWODTCSLow = TblPtr->WrODTCSLow; //WL ODT NBPtr->FamilySpecificHook[ExtractWLODT] (NBPtr, NBPtr); return TRUE; } TblPtr++; } IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT entries\n"); return FALSE; }
/** * * A sub-function which determine if 2D should be run * from a input table * * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK * * @return TRUE - Table values can be extracted per dimm population and ranks type. * @return FALSE - Table values cannot be extracted per dimm population and ranks type. * */ BOOLEAN MemPGetS2D ( IN OUT MEM_NB_BLOCK *NBPtr, IN MEM_PSC_TABLE_BLOCK *EntryOfTables ) { UINT8 i; UINT8 MaxDimmPerCh; UINT8 MaxDimmSlotPerCh; UINT8 NOD; UINT8 TableSize; UINT32 CurDDRrate; UINT8 DDR3Voltage; UINT16 RankTypeOfPopulatedDimm; UINT16 RankTypeInTable; BOOLEAN FoundValue; DIMM_TYPE DimmType; CPU_LOGICAL_ID LogicalCpuid; UINT8 PackageType; PSCFG_S2D_ENTRY *TblPtr; CH_DEF_STRUCT *CurrentChannel; UINT16 P2dTraingOveride; CurrentChannel = NBPtr->ChannelPtr; TblPtr = NULL; TableSize = 0; PackageType = 0; LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); MaxDimmSlotPerCh = MaxDimmPerCh - GetMaxSolderedDownDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); if (CurrentChannel->RegDimmPresent != 0) { DimmType = RDIMM_TYPE; } else if (CurrentChannel->SODimmPresent != 0) { DimmType = SODIMM_TYPE; } else if (CurrentChannel->LrDimmPresent != 0) { DimmType = LRDIMM_TYPE; } else { DimmType = UDIMM_TYPE; } // Check if it is "SODIMM plus soldered-down DRAM" or "Soldered-down DRAM only" configuration, // DimmType is changed to 'SODWN_SODIMM_TYPE' if soldered-down DRAM exist if (MaxDimmSlotPerCh != MaxDimmPerCh) { // SODIMM plus soldered-down DRAM DimmType = SODWN_SODIMM_TYPE; } else if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { // Soldered-down DRAM only DimmType = SODWN_SODIMM_TYPE; MaxDimmSlotPerCh = 0; } NOD = (UINT8) (MaxDimmSlotPerCh != 0) ? (1 << (MaxDimmSlotPerCh - 1)) : _DIMM_NONE; i = 0; // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. while (EntryOfTables->TblEntryOfS2D[i] != NULL) { if (((EntryOfTables->TblEntryOfS2D[i])->Header.DimmType & DimmType) != 0) { if (((EntryOfTables->TblEntryOfS2D[i])->Header.NumOfDimm & NOD) != 0) { // // Determine if this is the expected NB Type // LogicalCpuid = (EntryOfTables->TblEntryOfS2D[i])->Header.LogicalCpuid; PackageType = (EntryOfTables->TblEntryOfS2D[i])->Header.PackageType; if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { TblPtr = (PSCFG_S2D_ENTRY *) ((EntryOfTables->TblEntryOfS2D[i])->TBLPtr); TableSize = (EntryOfTables->TblEntryOfS2D[i])->TableSize; break; } } } i++; } // Check whether no table entry is found. if (EntryOfTables->TblEntryOfS2D[i] == NULL) { IDS_HDT_CONSOLE (MEM_FLOW, "\nNo 2D training Config table\n"); return FALSE; } CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); FoundValue = FALSE; for (i = 0; i < TableSize; i++) { MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); if ((TblPtr->DimmPerCh & NOD) != 0) { if ((TblPtr->DDRrate & CurDDRrate) != 0) { if ((TblPtr->VDDIO & DDR3Voltage) != 0) { if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { if (TblPtr->Enable2D == 1) { FoundValue = TRUE; break; } } } } } TblPtr++; } P2dTraingOveride = MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_2D_TRAINING); if (P2dTraingOveride != 0) { if (NBPtr->Override2DTraining) { FoundValue = TRUE; } else { FoundValue = FALSE; } } // // If there is no entry, check if overriding 2D training existed. If not, show no entry found. // if (FoundValue == FALSE || ((P2dTraingOveride & INVALID_CONFIG_FLAG) != 0)) { IDS_HDT_CONSOLE (MEM_FLOW, "\nNo 2D training config entries\n"); return FALSE; } else { return TRUE; } }