void HAL_USBDeInit(uint8_t corenum, uint8_t mode)
{
HAL_DisableUSBInterrupt(corenum);
if (mode == USB_MODE_Device) {
#if defined(USB_CAN_BE_HOST)
USB_REG(corenum)->USBSTS_H = 0xFFFFFFFF; /* clear all current interrupts */
USB_REG(corenum)->PORTSC1_H &= ~(1 << 12); /* clear port power */
USB_REG(corenum)->USBMODE_H = (1 << 0); /* set USB mode reserve */
#endif
}
else if (mode == USB_MODE_Host) {
#if defined(USB_CAN_BE_DEVICE)
/* Clear all pending interrupts */
USB_REG(corenum)->USBSTS_D = 0xFFFFFFFF;
USB_REG(corenum)->ENDPTNAK = 0xFFFFFFFF;
USB_REG(corenum)->ENDPTNAKEN = 0;
USB_REG(corenum)->ENDPTSETUPSTAT = USB_REG(corenum)->ENDPTSETUPSTAT;
USB_REG(corenum)->ENDPTCOMPLETE = USB_REG(corenum)->ENDPTCOMPLETE;
while (USB_REG(corenum)->ENDPTPRIME) ; /* Wait until all bits are 0 */
USB_REG(corenum)->ENDPTFLUSH = 0xFFFFFFFF;
while (USB_REG(corenum)->ENDPTFLUSH) ; /* Wait until all bits are 0 */
#endif
}
/* Disable USB PHY if both USB cores are disabled */
if (coreEnabled[1 - corenum]) {
/* Turn off the phy (prior to PLL disabled) */
Chip_CREG_EnableUSB0Phy(false);
}
/* Power down USB clocking */
if (corenum == 0) {
Chip_Clock_Disable(CLK_MX_USB0);
Chip_Clock_DisableBaseClock(CLK_BASE_USB0);
}
else {
Chip_Clock_Disable(CLK_MX_USB1);
Chip_Clock_DisableBaseClock(CLK_BASE_USB1);
}
/* Disable USB PLL if both USB cores are disabled */
if (coreEnabled[1 - corenum]) {
/* Disable USB PLL */
Chip_Clock_DisablePLL(CGU_USB_PLL);
}
coreEnabled[corenum] = false;
}
uint32_t MassStorage_Cache_Flush(bool appcall)
{
SPIFIopers opers;
int res;
if(cache_update_flag)
{
if(appcall) HAL_DisableUSBInterrupt();
opers.length = CACHE_SIZE;
opers.scratch = (char*)0;
opers.protect = 0;
opers.options = 0;
/* Write */
opers.dest = (char *)((disk_block*CACHE_SIZE) + Spifi_obj.base);
if (res = pSpifi->spifi_program (&Spifi_obj, (char *)disk_cache, &opers)) {
/*TODO: Program fail */
while(res);
}
cache_update_flag = 0;
if(appcall) HAL_EnableUSBInterrupt();
}
return 0;
}
