void hal_interrupt_unmask(int vector) { unsigned val; if (vector < CYGNUM_HAL_ISR_MIN || CYGNUM_HAL_ISR_MAX < vector) return; #if CYGNUM_HAL_ISR_MAX > CYGNUM_HAL_VAR_ISR_MAX if (vector > CYGNUM_HAL_VAR_ISR_MAX) { HAL_PLF_INTERRUPT_UNMASK(vector); return; } #endif val = *IXP425_INTR_EN | (1 << vector); // If all NPE interrupts are masked, also mask QM1 which is // shared by all NPE ports. if (vector == CYGNUM_HAL_INTERRUPT_NPEB || vector == CYGNUM_HAL_INTERRUPT_NPEC) { val |= (1 << CYGNUM_HAL_INTERRUPT_QM1); } *IXP425_INTR_EN = val; }
externC void hal_ppc40x_interrupt_unmask(int vector) { cyg_uint32 exier, tcr; switch (vector) { case CYGNUM_HAL_INTERRUPT_first...CYGNUM_HAL_INTERRUPT_last: #ifndef HAL_PLF_INTERRUPT_UNMASK CYGARC_MFDCR(DCR_UIC0_ER, exier); exier |= (1<<(31-(vector-CYGNUM_HAL_INTERRUPT_405_BASE))); CYGARC_MTDCR(DCR_UIC0_ER, exier); #else HAL_PLF_INTERRUPT_UNMASK(vector); #endif break; case CYGNUM_HAL_INTERRUPT_VAR_TIMER: CYGARC_MFSPR(SPR_TCR, tcr); tcr = _hold_tcr; tcr |= TCR_PIE; CYGARC_MTSPR(SPR_TCR, tcr); _hold_tcr = tcr; break; case CYGNUM_HAL_INTERRUPT_FIXED_TIMER: CYGARC_MFSPR(SPR_TCR, tcr); tcr = _hold_tcr; tcr |= TCR_FIE; CYGARC_MTSPR(SPR_TCR, tcr); _hold_tcr = tcr; break; case CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER: CYGARC_MFSPR(SPR_TCR, tcr); tcr = _hold_tcr; tcr |= TCR_WIE; CYGARC_MTSPR(SPR_TCR, tcr); _hold_tcr = tcr; break; default: break; } }