externC cyg_uint32
_csb281_pci_cfg_read_uint32(int bus, int devfn, int offset)
{
cyg_uint32 addr;
cyg_uint32 cfg_val = (cyg_uint32)0xFFFFFFFF;
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
#endif // CYGPKG_IO_PCI_DEBUG
addr = _cfg_sel(bus, devfn, offset);
HAL_READ_UINT32LE(addr, cfg_val);
#if 0
HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
if (status & _CSB281_PCI_STAT_ERROR_MASK) {
// Cycle failed - clean up and get out
cfg_val = (cyg_uint32)0xFFFFFFFF;
HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
}
#endif
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%x\n", cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
return cfg_val;
}
void
hal_interrupt_configure(int vector, int level, int up)
{
cyg_uint32 pvr;
CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
// Can't do much with non-external interrupts
return;
}
// diag_printf("%s(%d, %d, %d)\n", __FUNCTION__, vector, level, up);
HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
pvr &= _CSB281_EPIC_PVR_M; // Preserve mask
pvr |= vector;
if (level) {
pvr |= _CSB281_EPIC_PVR_S;
} else {
pvr &= ~_CSB281_EPIC_PVR_S;
}
if (up) {
pvr |= _CSB281_EPIC_PVR_P;
} else {
pvr &= ~_CSB281_EPIC_PVR_P;
}
HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
}
//--------------------------------------------------------------------------
// Platform init code.
void
hal_platform_init(void)
{
cyg_uint32 bcsr, gcr, frr, eicr, iack;
int vec;
// Initialize I/O interfaces
hal_if_init();
// Reset interrupt controller/state
HAL_READ_UINT32LE(_CSB281_EPIC_GCR, gcr);
HAL_READ_UINT32LE(_CSB281_EPIC_FRR, frr);
HAL_WRITE_UINT32LE(_CSB281_EPIC_GCR, gcr | _CSB281_EPIC_GCR_R);
do {
HAL_READ_UINT32LE(_CSB281_EPIC_GCR, gcr);
} while ((gcr & _CSB281_EPIC_GCR_R) != 0);
HAL_WRITE_UINT32LE(_CSB281_EPIC_GCR, gcr | _CSB281_EPIC_GCR_M);
HAL_READ_UINT32LE(_CSB281_EPIC_EICR, eicr); // Force direct interrupts
eicr &= ~_CSB281_EPIC_EICR_SIE;
HAL_WRITE_UINT32LE(_CSB281_EPIC_EICR, eicr);
for (vec = CYGNUM_HAL_INTERRUPT_IRQ0; vec <= CYGNUM_HAL_ISR_MAX; vec++) {
HAL_INTERRUPT_CONFIGURE(vec, 0, 0); // Default to low-edge
HAL_INTERRUPT_SET_LEVEL(vec, 0x0F); // Priority
}
vec = (frr & 0x0FFF0000) >> 16; // Number of interrupt sources
while (vec-- > 0) {
HAL_READ_UINT32LE(_CSB281_EPIC_IACK, iack);
HAL_WRITE_UINT32LE(_CSB281_EPIC_EOI, 0);
}
HAL_WRITE_UINT32LE(_CSB281_EPIC_PCTPR, 1); // Enables interrupts
#ifndef CYGSEM_HAL_USE_ROM_MONITOR
// Reset peripherals
HAL_READ_UINT32(_CSB281_BCSR, bcsr);
HAL_WRITE_UINT32(_CSB281_BCSR, _zero_bit(bcsr, _CSB281_BCSR_PRESET));
HAL_WRITE_UINT32(_CSB281_BCSR, _one_bit(bcsr, _CSB281_BCSR_PRESET));
_csb281_i2c_init();
_csb281_fs6377_init(0);
#endif
#ifdef CYGSEM_CSB281_LCD_COMM
lcd_comm_init();
#endif
_csb281_pci_init();
}
void
hal_interrupt_set_level(int vector, int level)
{
cyg_uint32 pvr;
CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
// Can't do much with non-external interrupts
return;
}
HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
pvr &= ~(_CSB281_EPIC_PVR_PRIO_MASK<<_CSB281_EPIC_PVR_PRIO_SHIFT);
pvr |= (level<<_CSB281_EPIC_PVR_PRIO_SHIFT);
HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
}
void
hal_interrupt_unmask(int vector)
{
cyg_uint32 pvr;
CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
// Can't do much with non-external interrupts
return;
}
HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
pvr &= ~_CSB281_EPIC_PVR_M;
HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
// diag_printf("%s(%d)\n", __FUNCTION__, vector);
}
externC cyg_uint32
hal_ppc405_pci_cfg_read_uint32(int bus, int devfn, int offset)
{
cyg_uint32 cfg_addr;
cyg_uint32 cfg_val = (cyg_uint32) 0xFFFFFFFF;
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
#endif // CYGPKG_IO_PCI_DEBUG
cfg_addr = _cfg_addr(bus, devfn, offset);
HAL_WRITE_UINT32LE(PCIC0_CFGADDR, cfg_addr);
HAL_READ_UINT32LE(PCIC0_CFGDATA, cfg_val);
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%x\n", cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
return cfg_val;
}
