externC void
hal_ppc405_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val)
{
cyg_uint32 cfg_addr;
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
cfg_addr = _cfg_addr(bus, devfn, offset);
HAL_WRITE_UINT32LE(PCIC0_CFGADDR, cfg_addr);
HAL_WRITE_UINT32LE(PCIC0_CFGDATA, cfg_val);
}
void
hal_interrupt_configure(int vector, int level, int up)
{
cyg_uint32 pvr;
CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
// Can't do much with non-external interrupts
return;
}
// diag_printf("%s(%d, %d, %d)\n", __FUNCTION__, vector, level, up);
HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
pvr &= _CSB281_EPIC_PVR_M; // Preserve mask
pvr |= vector;
if (level) {
pvr |= _CSB281_EPIC_PVR_S;
} else {
pvr &= ~_CSB281_EPIC_PVR_S;
}
if (up) {
pvr |= _CSB281_EPIC_PVR_P;
} else {
pvr &= ~_CSB281_EPIC_PVR_P;
}
HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
}
//--------------------------------------------------------------------------
// Platform init code.
void
hal_platform_init(void)
{
cyg_uint32 bcsr, gcr, frr, eicr, iack;
int vec;
// Initialize I/O interfaces
hal_if_init();
// Reset interrupt controller/state
HAL_READ_UINT32LE(_CSB281_EPIC_GCR, gcr);
HAL_READ_UINT32LE(_CSB281_EPIC_FRR, frr);
HAL_WRITE_UINT32LE(_CSB281_EPIC_GCR, gcr | _CSB281_EPIC_GCR_R);
do {
HAL_READ_UINT32LE(_CSB281_EPIC_GCR, gcr);
} while ((gcr & _CSB281_EPIC_GCR_R) != 0);
HAL_WRITE_UINT32LE(_CSB281_EPIC_GCR, gcr | _CSB281_EPIC_GCR_M);
HAL_READ_UINT32LE(_CSB281_EPIC_EICR, eicr); // Force direct interrupts
eicr &= ~_CSB281_EPIC_EICR_SIE;
HAL_WRITE_UINT32LE(_CSB281_EPIC_EICR, eicr);
for (vec = CYGNUM_HAL_INTERRUPT_IRQ0; vec <= CYGNUM_HAL_ISR_MAX; vec++) {
HAL_INTERRUPT_CONFIGURE(vec, 0, 0); // Default to low-edge
HAL_INTERRUPT_SET_LEVEL(vec, 0x0F); // Priority
}
vec = (frr & 0x0FFF0000) >> 16; // Number of interrupt sources
while (vec-- > 0) {
HAL_READ_UINT32LE(_CSB281_EPIC_IACK, iack);
HAL_WRITE_UINT32LE(_CSB281_EPIC_EOI, 0);
}
HAL_WRITE_UINT32LE(_CSB281_EPIC_PCTPR, 1); // Enables interrupts
#ifndef CYGSEM_HAL_USE_ROM_MONITOR
// Reset peripherals
HAL_READ_UINT32(_CSB281_BCSR, bcsr);
HAL_WRITE_UINT32(_CSB281_BCSR, _zero_bit(bcsr, _CSB281_BCSR_PRESET));
HAL_WRITE_UINT32(_CSB281_BCSR, _one_bit(bcsr, _CSB281_BCSR_PRESET));
_csb281_i2c_init();
_csb281_fs6377_init(0);
#endif
#ifdef CYGSEM_CSB281_LCD_COMM
lcd_comm_init();
#endif
_csb281_pci_init();
}
void
hal_interrupt_set_level(int vector, int level)
{
cyg_uint32 pvr;
CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
// Can't do much with non-external interrupts
return;
}
HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
pvr &= ~(_CSB281_EPIC_PVR_PRIO_MASK<<_CSB281_EPIC_PVR_PRIO_SHIFT);
pvr |= (level<<_CSB281_EPIC_PVR_PRIO_SHIFT);
HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
}
void
hal_interrupt_unmask(int vector)
{
cyg_uint32 pvr;
CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
// Can't do much with non-external interrupts
return;
}
HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
pvr &= ~_CSB281_EPIC_PVR_M;
HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
// diag_printf("%s(%d)\n", __FUNCTION__, vector);
}
externC cyg_uint32
hal_ppc405_pci_cfg_read_uint32(int bus, int devfn, int offset)
{
cyg_uint32 cfg_addr;
cyg_uint32 cfg_val = (cyg_uint32) 0xFFFFFFFF;
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
#endif // CYGPKG_IO_PCI_DEBUG
cfg_addr = _cfg_addr(bus, devfn, offset);
HAL_WRITE_UINT32LE(PCIC0_CFGADDR, cfg_addr);
HAL_READ_UINT32LE(PCIC0_CFGDATA, cfg_val);
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%x\n", cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
return cfg_val;
}
//
// Prepare for a config cycle on the PCI bus
//
static __inline__ cyg_uint32
_cfg_sel(int bus, int devfn, int offset)
{
cyg_uint32 cfg_addr, addr;
cyg_uint32 bcsr;
HAL_READ_UINT32(_CSB281_BCSR, bcsr);
bcsr = (bcsr & ~0x07) | (1<<(CYG_PCI_DEV_GET_DEV(devfn)-CYG_PCI_MIN_DEV));
HAL_WRITE_UINT32(_CSB281_BCSR, bcsr);
cfg_addr = _EXT_ENABLE |
(bus << 16) |
(CYG_PCI_DEV_GET_DEV(devfn) << 11) |
(CYG_PCI_DEV_GET_FN(devfn) << 8) |
((offset & 0xFF) << 0);
HAL_WRITE_UINT32LE(_CSB281_PCI_CONFIG_ADDR, cfg_addr);
addr = _CSB281_PCI_CONFIG_DATA + (offset & 0x03);
return addr;
}
externC void
_csb281_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val)
{
cyg_uint32 addr;
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
addr = _cfg_sel(bus, devfn, offset);
HAL_WRITE_UINT32LE(addr, cfg_val);
#if 0
HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
if (status & _CSB281_PCI_STAT_ERROR_MASK) {
// Cycle failed - clean up and get out
HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
}
#endif
HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
}
externC void
hal_ppc405_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state, bridge_state;
if (_init) return;
_init = 1;
// Configure PCI bridge
HAL_WRITE_UINT32LE(PCIL0_PMM0PCILA, 0);
HAL_WRITE_UINT32LE(PCIL0_PMM0PCIHA, 0);
HAL_WRITE_UINT32LE(PCIL0_PMM0LA, HAL_PCI_PHYSICAL_MEMORY_BASE);
HAL_WRITE_UINT32LE(PCIL0_PMM0MA, ~(0x10000000-1) | 0x00000001);
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_1, 0);
HAL_WRITE_UINT32LE(PCIL0_PTM1LA, 0);
HAL_WRITE_UINT32LE(PCIL0_PTM1MS, ~(0x10000000-1) | 0x00000001);
// Indicate that the bridge has been configured
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state);
bridge_state |= 0x0001;
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state);
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
cyg_pci_init();
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
#if defined(CYGPKG_IO_PCI_DEBUG)
diag_printf("Configure PCI bus\n");
#endif
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
#if defined(CYGSEM_HAL_POWERPC_PPC405_PCI_SHOW_BUS)
if (1) {
cyg_uint8 req;
cyg_uint8 devfn;
cyg_pci_device_id devid;
cyg_pci_device dev_info;
int i;
devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN;
while (cyg_pci_find_next(devid, &devid)) {
devfn = CYG_PCI_DEV_GET_DEVFN(devid);
cyg_pci_get_device_info(devid, &dev_info);
HAL_PCI_CFG_READ_UINT8(0, devfn, CYG_PCI_CFG_INT_PIN, req);
diag_printf("\n");
diag_printf("Bus: %d", CYG_PCI_DEV_GET_BUS(devid));
diag_printf(", PCI Device: %d", CYG_PCI_DEV_GET_DEV(devfn));
diag_printf(", PCI Func: %d\n", CYG_PCI_DEV_GET_FN(devfn));
diag_printf(" Vendor Id: 0x%04X", dev_info.vendor);
diag_printf(", Device Id: 0x%04X", dev_info.device);
diag_printf(", Command: 0x%04X", dev_info.command);
diag_printf(", IRQ: %d\n", req);
for (i = 0; i < dev_info.num_bars; i++) {
diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
dev_info.base_size[i], dev_info.base_map[i]);
}
}
}
#endif
}
