/* Text representation of status */
void tty_report(int cyc) {
sim_log("\nCycle %d. CC=%s, Stat=%s\n", cyc, cc_name(cc), stat_name(status));
sim_log("F: predPC = 0x%x\n", pc_curr->pc);
sim_log("D: instr = %s, rA = %s, rB = %s, valC = 0x%x, valP = 0x%x, Stat = %s\n",
iname(HPACK(if_id_curr->icode, if_id_curr->ifun)),
reg_name(if_id_curr->ra), reg_name(if_id_curr->rb),
if_id_curr->valc, if_id_curr->valp,
stat_name(if_id_curr->status));
sim_log("E: instr = %s, valC = 0x%x, valA = 0x%x, valB = 0x%x\n srcA = %s, srcB = %s, dstE = %s, dstM = %s, Stat = %s\n",
iname(HPACK(id_ex_curr->icode, id_ex_curr->ifun)),
id_ex_curr->valc, id_ex_curr->vala, id_ex_curr->valb,
reg_name(id_ex_curr->srca), reg_name(id_ex_curr->srcb),
reg_name(id_ex_curr->deste), reg_name(id_ex_curr->destm),
stat_name(id_ex_curr->status));
sim_log("M: instr = %s, Cnd = %d, valE = 0x%x, valA = 0x%x\n dstE = %s, dstM = %s, Stat = %s\n",
iname(HPACK(ex_mem_curr->icode, ex_mem_curr->ifun)),
ex_mem_curr->takebranch,
ex_mem_curr->vale, ex_mem_curr->vala,
reg_name(ex_mem_curr->deste), reg_name(ex_mem_curr->destm),
stat_name(ex_mem_curr->status));
sim_log("W: instr = %s, valE = 0x%x, valM = 0x%x, dstE = %s, dstM = %s, Stat = %s\n",
iname(HPACK(mem_wb_curr->icode, mem_wb_curr->ifun)),
mem_wb_curr->vale, mem_wb_curr->valm,
reg_name(mem_wb_curr->deste), reg_name(mem_wb_curr->destm),
stat_name(mem_wb_curr->status));
}
void do_if_stage()
{
byte_t instr = HPACK(I_NOP, F_NONE);
byte_t regids = HPACK(REG_NONE, REG_NONE);
word_t valc = 0;
word_t valp = f_pc = gen_f_pc();
/* Ready to fetch instruction. Speculatively fetch register byte
and immediate word
*/
imem_error = !get_byte_val(mem, valp+START_PLACE, &instr);
imem_icode = HI4(instr);
imem_ifun = LO4(instr);
if (!imem_error) {
byte_t junk;
/* Make sure can read maximum length instruction */
imem_error = !get_byte_val(mem, valp+5 + START_PLACE, &junk);
}
if_id_next->icode = gen_f_icode();
if_id_next->ifun = gen_f_ifun();
if (!imem_error) {
sim_log("\tFetch: f_pc = 0x%x, imem_instr = %s, f_instr = %s\n",
f_pc, iname(instr),
iname(HPACK(if_id_next->icode, if_id_next->ifun)));
}
instr_valid = gen_instr_valid();
if (!instr_valid)
sim_log("\tFetch: Instruction code 0x%x invalid\n", instr);
if_id_next->status = gen_f_stat();
valp++;
if (gen_need_regids()) {
get_byte_val(mem, valp + START_PLACE, ®ids);
valp ++;
}
if_id_next->ra = HI4(regids);
if_id_next->rb = LO4(regids);
if (gen_need_valC()) {
get_word_val(mem, valp + START_PLACE, &valc);
valp+= 4;
}
if_id_next->valp = valp;
if_id_next->valc = valc;
/*
if(gen_need_regids() && if_id_next->valc)
printf("##### vap: %d %d %d\n", if_id_next->ra, if_id_next->rb, if_id_next->valc);
*/
pc_next->pc = gen_f_predPC();
pc_next->status = (if_id_next->status == STAT_AOK) ? STAT_AOK : STAT_BUB;
if_id_next->stage_pc = f_pc;
}
void do_mem_stage()
{
bool_t read = gen_mem_read();
bool_t mem_ok = TRUE;
word_t valm = 0;
mem_addr = gen_mem_addr();
mem_data = ex_mem_curr->vala;
mem_write = gen_mem_write();
if (read) {
mem_ok = get_word_val(mem, mem_addr, &valm);
sim_log("Memory: Read 0x%x from 0x%x, instruction = %s\n",
valm, mem_addr,
iname(HPACK(ex_mem_curr->icode, ex_mem_curr->ifun)));
}
if (mem_write) {
word_t sink;
/* Do a read of address just to check validity */
mem_ok = get_word_val(mem, mem_addr, &sink);
}
mem_wb_next->icode = ex_mem_curr->icode;
mem_wb_next->ifun = ex_mem_curr->ifun;
mem_wb_next->vale = ex_mem_curr->vale;
mem_wb_next->valm = valm;
mem_wb_next->deste = ex_mem_curr->deste;
mem_wb_next->destm = ex_mem_curr->destm;
mem_wb_next->exception = mem_ok ? ex_mem_curr->exception : EXC_ADDR;
mem_wb_next->stage_pc = ex_mem_curr->stage_pc;
}
/* Implements both ID and WB */
void do_id_wb_stages()
{
/* Set up write backs. Don't occur until end of cycle */
wb_destE = gen_w_dstE();
wb_valE = gen_w_valE();
wb_destM = gen_w_dstM();
wb_valM = gen_w_valM();
id_ex_next->srca = gen_new_E_srcA();
id_ex_next->srcb = gen_new_E_srcB();
id_ex_next->deste = gen_new_E_dstE();
id_ex_next->destm = gen_new_E_dstM();
/* Read the registers */
d_regvala = get_reg_val(reg, id_ex_next->srca);
d_regvalb = get_reg_val(reg, id_ex_next->srcb);
/* Do forwarding and valA selection */
id_ex_next->vala = gen_new_E_valA();
id_ex_next->valb = gen_new_E_valB();
id_ex_next->icode = if_id_curr->icode;
id_ex_next->ifun = if_id_curr->ifun;
id_ex_next->valc = if_id_curr->valc;
id_ex_next->stage_pc = if_id_curr->stage_pc;
id_ex_next->exception = (if_id_curr->icode == I_HALT) ?
EXC_HALT : if_id_curr->exception;
sim_log("Decode: instr = %s, exc=%s\n",
iname(HPACK(if_id_curr->icode, if_id_curr->ifun)),
exc_name(if_id_curr->exception));
}
void sim_reset()
{
if (!initialized)
sim_init();
clear_mem(reg);
minAddr = 0;
memCnt = 0;
#ifdef HAS_GUI
if (gui_mode) {
signal_register_clear();
create_memory_display(minAddr, memCnt);
sim_report();
}
#endif
if (plusmode) {
prev_icode = prev_icode_in = I_NOP;
prev_ifun = prev_ifun_in = 0;
prev_valc = prev_valc_in = 0;
prev_valm = prev_valm_in = 0;
prev_valp = prev_valp_in = 0;
prev_bcond = prev_bcond_in = FALSE;
pc = 0;
} else {
pc_in = 0;
}
cc = DEFAULT_CC;
cc_in = DEFAULT_CC;
destE = REG_NONE;
destM = REG_NONE;
mem_write = FALSE;
mem_addr = 0;
mem_data = 0;
/* Reset intermediate values to clear display */
icode = I_NOP;
ifun = 0;
instr = HPACK(I_NOP, F_NONE);
ra = REG_NONE;
rb = REG_NONE;
valc = 0;
valp = 0;
srcA = REG_NONE;
srcB = REG_NONE;
destE = REG_NONE;
destM = REG_NONE;
vala = 0;
valb = 0;
vale = 0;
cond = FALSE;
bcond = FALSE;
valm = 0;
sim_report();
}
void do_ex_stage()
{
alu_t alufun = gen_alufun();
bool_t setcc = gen_set_cc();
word_t alua, alub;
alua = gen_aluA();
alub = gen_aluB();
e_bcond = take_branch(cc, id_ex_curr->ifun);
ex_mem_next->takebranch = id_ex_curr->icode == I_JMP &&
e_bcond;
if (id_ex_curr->icode == I_JMP)
sim_log("Execute: %s instruction, cc = %s, branch %staken\n",
iname(HPACK(id_ex_curr->icode, id_ex_curr->ifun)),
cc_name(cc),
ex_mem_next->takebranch ? "" : "not ");
/* Perform the ALU operation */
ex_mem_next->vale = compute_alu(alufun, alua, alub);
{
byte_t instr = HPACK(id_ex_curr->icode, id_ex_curr->ifun);
sim_log("Execute: Instruction %s\n",
iname(instr));
}
if (setcc) {
cc_in = compute_cc(alufun, alua, alub);
sim_log("Execute: CC cc = %s\n", cc_name(cc_in));
}
ex_mem_next->icode = id_ex_curr->icode;
ex_mem_next->ifun = id_ex_curr->ifun;
ex_mem_next->vala = gen_new_M_valA();
ex_mem_next->deste = id_ex_curr->deste;
ex_mem_next->destm = id_ex_curr->destm;
ex_mem_next->srca = id_ex_curr->srca;
ex_mem_next->exception = id_ex_curr->exception;
ex_mem_next->stage_pc = id_ex_curr->stage_pc;
}
char *format_if_id(if_id_ptr state){
char valcstring[9];
char valpstring[9];
wstring(state->valc, 4, 32, valcstring);
wstring(state->valp, 4, 32, valpstring);
sprintf(status_msg, "%s %s %s %s %s %s",
stat_name(state->status),
iname(HPACK(state->icode,state->ifun)),
reg_name(state->ra),
reg_name(state->rb),
valcstring,
valpstring);
return status_msg;
}
static char *format_f()
{
char valcstring[9];
char valpstring[9];
wstring(valc, 4, 32, valcstring);
wstring(valp, 4, 32, valpstring);
sprintf(status_msg, "%s %s %s %s %s",
iname(HPACK(icode, ifun)),
reg_name(ra),
reg_name(rb),
valcstring,
valpstring);
return status_msg;
}
char *format_mem_wb(mem_wb_ptr state){
char valestring[9];
char valmstring[9];
wstring(state->vale, 4, 32, valestring);
wstring(state->valm, 4, 32, valmstring);
sprintf(status_msg, "%s %s %s %s %s %s",
stat_name(state->status),
iname(HPACK(state->icode, state->ifun)),
valestring,
valmstring,
reg_name(state->deste),
reg_name(state->destm));
return status_msg;
}
/* SEQ+ */
static char *format_prev()
{
char istring[9];
char mstring[9];
char pstring[9];
wstring(prev_valc, 4, 32, istring);
wstring(prev_valm, 4, 32, mstring);
wstring(prev_valp, 4, 32, pstring);
sprintf(status_msg, "%c %s %s %s %s",
prev_bcond ? 'Y' : 'N',
iname(HPACK(prev_icode, prev_ifun)),
istring, mstring, pstring);
return status_msg;
}
char *format_ex_mem(ex_mem_ptr state){
char valestring[9];
char valastring[9];
wstring(state->vale, 4, 32, valestring);
wstring(state->vala, 4, 32, valastring);
sprintf(status_msg, "%s %s %c %s %s %s %s",
stat_name(state->status),
iname(HPACK(state->icode, state->ifun)),
state->takebranch ? 'Y' : 'N',
valestring,
valastring,
reg_name(state->deste),
reg_name(state->destm));
return status_msg;
}
char *format_id_ex(id_ex_ptr state){
char valcstring[9];
char valastring[9];
char valbstring[9];
wstring(state->valc, 4, 32, valcstring);
wstring(state->vala, 4, 32, valastring);
wstring(state->valb, 4, 32, valbstring);
sprintf(status_msg, "%s %s %s %s %s %s %s %s %s",
stat_name(state->status),
iname(HPACK(state->icode, state->ifun)),
valcstring,
valastring,
valbstring,
reg_name(state->deste),
reg_name(state->destm),
reg_name(state->srca),
reg_name(state->srcb));
return status_msg;
}
void do_ex_stage()
{
alu_t alufun = gen_alufun();
bool_t setcc = gen_set_cc();
word_t alua, alub;
alua = gen_aluA();
alub = gen_aluB();
e_bcond = cond_holds(cc, id_ex_curr->ifun);
ex_mem_next->takebranch = e_bcond;
if (id_ex_curr->icode == I_JMP)
sim_log("\tExecute: instr = %s, cc = %s, branch %staken\n",
iname(HPACK(id_ex_curr->icode, id_ex_curr->ifun)),
cc_name(cc),
ex_mem_next->takebranch ? "" : "not ");
/* Perform the ALU operation */
word_t aluout = compute_alu(alufun, alua, alub);
ex_mem_next->vale = aluout;
sim_log("\tExecute: ALU: %c 0x%x 0x%x --> 0x%x\n",
op_name(alufun), alua, alub, aluout);
if (setcc) {
cc_in = compute_cc(alufun, alua, alub);
sim_log("\tExecute: New cc = %s\n", cc_name(cc_in));
}
ex_mem_next->icode = id_ex_curr->icode;
ex_mem_next->ifun = id_ex_curr->ifun;
ex_mem_next->vala = gen_e_valA();
ex_mem_next->deste = gen_e_dstE();
ex_mem_next->destm = id_ex_curr->destm;
ex_mem_next->srca = id_ex_curr->srca;
ex_mem_next->status = id_ex_curr->status;
ex_mem_next->stage_pc = id_ex_curr->stage_pc;
}
word_t prev_valc_in = 0; word_t prev_valm_in = 0; word_t prev_valp_in = 0; bool_t prev_bcond_in = FALSE; /* Program Counter */ word_t pc = 0; /* Program counter value */ word_t pc_in = 0;/* Input to program counter */ /* Intermediate values */ byte_t imem_icode = I_NOP; byte_t imem_ifun = F_NONE; byte_t icode = I_NOP; word_t ifun = 0; byte_t instr = HPACK(I_NOP, F_NONE); word_t ra = REG_NONE; word_t rb = REG_NONE; word_t valc = 0; word_t valp = 0; bool_t imem_error; bool_t instr_valid; word_t srcA = REG_NONE; word_t srcB = REG_NONE; word_t destE = REG_NONE; word_t destM = REG_NONE; word_t vala = 0; word_t valb = 0; word_t vale = 0;
byte_t prev_icode_in = I_NOP; byte_t prev_ifun_in = 0; word_t prev_valc_in = 0; word_t prev_valm_in = 0; word_t prev_valp_in = 0; bool_t prev_bcond_in = FALSE; /* Program Counter */ word_t pc = 0; /* Program counter value */ word_t pc_in = 0;/* Input to program counter */ /* Intermediate values */ byte_t icode = I_NOP; word_t ifun = 0; byte_t instr = HPACK(I_NOP, 0); word_t ra = REG_NONE; word_t rb = REG_NONE; word_t valc = 0; word_t valp = 0; word_t srcA = REG_NONE; word_t srcB = REG_NONE; word_t destE = REG_NONE; word_t destM = REG_NONE; word_t vala = 0; word_t valb = 0; word_t vale = 0; bool_t bcond = FALSE; word_t valm = 0;
/* Return resulting status */
static byte_t sim_step()
{
word_t aluA;
word_t aluB;
word_t alufun;
status = STAT_AOK;
imem_error = dmem_error = FALSE;
update_state(); /* Update state from last cycle */
if (plusmode) {
pc = gen_pc();
}
valp = pc;
instr = HPACK(I_NOP, F_NONE);
imem_error = !get_byte_val(mem, valp, &instr);
if (imem_error) {
sim_log("Couldn't fetch at address 0x%x\n", valp);
}
imem_icode = HI4(instr);
imem_ifun = LO4(instr);
icode = gen_icode();
ifun = gen_ifun();
instr_valid = gen_instr_valid();
valp++;
if (gen_need_regids()) {
byte_t regids;
if (get_byte_val(mem, valp, ®ids)) {
ra = GET_RA(regids);
rb = GET_RB(regids);
} else {
ra = REG_NONE;
rb = REG_NONE;
status = STAT_ADR;
sim_log("Couldn't fetch at address 0x%x\n", valp);
}
valp++;
} else {
ra = REG_NONE;
rb = REG_NONE;
}
if (gen_need_valC()) {
if (get_word_val(mem, valp, &valc)) {
} else {
valc = 0;
status = STAT_ADR;
sim_log("Couldn't fetch at address 0x%x\n", valp);
}
valp+=4;
} else {
valc = 0;
}
sim_log("IF: Fetched %s at 0x%x. ra=%s, rb=%s, valC = 0x%x\n",
iname(HPACK(icode,ifun)), pc, reg_name(ra), reg_name(rb), valc);
if (status == STAT_AOK && icode == I_HALT) {
status = STAT_HLT;
}
srcA = gen_srcA();
if (srcA != REG_NONE) {
vala = get_reg_val(reg, srcA);
} else {
vala = 0;
}
srcB = gen_srcB();
if (srcB != REG_NONE) {
valb = get_reg_val(reg, srcB);
} else {
valb = 0;
}
cond = cond_holds(cc, ifun);
destE = gen_dstE();
destM = gen_dstM();
aluA = gen_aluA();
aluB = gen_aluB();
alufun = gen_alufun();
vale = compute_alu(alufun, aluA, aluB);
cc_in = cc;
if (gen_set_cc())
cc_in = compute_cc(alufun, aluA, aluB);
bcond = cond && (icode == I_JMP);
mem_addr = gen_mem_addr();
mem_data = gen_mem_data();
if (gen_mem_read()) {
dmem_error = dmem_error || !get_word_val(mem, mem_addr, &valm);
if (dmem_error) {
sim_log("Couldn't read at address 0x%x\n", mem_addr);
}
} else
valm = 0;
mem_write = gen_mem_write();
if (mem_write) {
/* Do a test read of the data memory to make sure address is OK */
word_t junk;
dmem_error = dmem_error || !get_word_val(mem, mem_addr, &junk);
}
status = gen_Stat();
if (plusmode) {
prev_icode_in = icode;
prev_ifun_in = ifun;
prev_valc_in = valc;
prev_valm_in = valm;
prev_valp_in = valp;
prev_bcond_in = bcond;
} else {
/* Update PC */
pc_in = gen_new_pc();
}
sim_report();
return status;
}
/* Return resulting exception status */
static exc_t sim_step()
{
word_t aluA;
word_t aluB;
word_t alufun;
exc_t status = update_state(); /* Update state from last cycle */
if (plusmode) {
pc = gen_pc();
}
valp = pc;
if (get_byte_val(mem, valp, &instr)) {
icode = HI4(instr);
ifun = LO4(instr);
} else {
instr = HPACK(I_NOP,0);
icode = I_NOP;
ifun = 0;
status = EXC_ADDR;
sim_log("Couldn't fetch at address 0x%x\n", valp);
}
valp++;
if (gen_need_regids()) {
byte_t regids;
if (get_byte_val(mem, valp, ®ids)) {
ra = GET_RA(regids);
rb = GET_RB(regids);
} else {
ra = REG_NONE;
rb = REG_NONE;
status = EXC_ADDR;
sim_log("Couldn't fetch at address 0x%x\n", valp);
}
valp++;
} else {
ra = REG_NONE;
rb = REG_NONE;
}
if (gen_need_valC()) {
if (get_word_val(mem, valp, &valc)) {
} else {
valc = 0;
status = EXC_ADDR;
sim_log("Couldn't fetch at address 0x%x\n", valp);
}
valp+=4;
} else {
valc = 0;
}
if (status == EXC_NONE && !gen_instr_valid()) {
status = EXC_INSTR;
}
sim_log("IF: Fetched %s at 0x%x. ra=%s, rb=%s, valC = 0x%x\n",
iname(HPACK(icode,ifun)), pc, reg_name(ra), reg_name(rb), valc);
if (status == EXC_NONE && icode == I_HALT) {
status = EXC_HALT;
}
srcA = gen_srcA();
if (srcA != REG_NONE) {
vala = get_reg_val(reg, srcA);
} else {
vala = 0;
}
srcB = gen_srcB();
if (srcB != REG_NONE) {
valb = get_reg_val(reg, srcB);
} else {
valb = 0;
}
destE = gen_dstE();
destM = gen_dstM();
aluA = gen_aluA();
aluB = gen_aluB();
alufun = gen_alufun();
vale = compute_alu(alufun, aluA, aluB);
cc_in = cc;
if (gen_set_cc())
cc_in = compute_cc(alufun, aluA, aluB);
bcond = (icode == I_JMP) && take_branch(cc, ifun);
mem_addr = gen_mem_addr();
mem_data = gen_mem_data();
if (status == EXC_NONE && gen_mem_read()) {
if (!get_word_val(mem, mem_addr, &valm)) {
sim_log("Couldn't read at address 0x%x\n", mem_addr);
return EXC_ADDR;
}
} else
valm = 0;
mem_write = status == EXC_NONE && gen_mem_write();
if (plusmode) {
prev_icode_in = icode;
prev_ifun_in = ifun;
prev_valc_in = valc;
prev_valm_in = valm;
prev_valp_in = valp;
prev_bcond_in = bcond;
} else {
/* Update PC */
pc_in = gen_new_pc();
}
sim_report();
return status;
}
void do_if_stage()
{
exc_t nstatus = EXC_NONE;
word_t fetchpc = gen_f_pc();
word_t valp = fetchpc;
bool_t fetch_ok;
byte_t instr;
byte_t regids = HPACK(REG_NONE, REG_NONE);
word_t valc = 0;
f_pc = fetchpc;
if (fetchpc == 0) {
sim_log("Fetch: Fetch pc = 0, nominal pc = 0x%x\n",
pc_curr->pc);
}
/* Ready to fetch instruction. Speculatively fetch register byte
and immediate word
*/
fetch_ok = get_byte_val(mem, valp, &instr);
if (fetch_ok) {
if_id_next->icode = GET_ICODE(instr);
if_id_next->ifun = GET_FUN(instr);
} else {
if_id_next->icode = I_NOP;
if_id_next->ifun = 0;
nstatus = EXC_ADDR;
}
valp++;
if (fetch_ok && gen_need_regids()) {
fetch_ok = get_byte_val(mem, valp, ®ids);
valp ++;
}
if_id_next->ra = HI4(regids);
if_id_next->rb = LO4(regids);
if (fetch_ok && gen_need_valC()) {
fetch_ok = get_word_val(mem, valp, &valc);
valp+= 4;
}
if_id_next->valp = valp;
if_id_next->valc = valc;
pc_next->pc = gen_new_F_predPC();
if (!gen_instr_valid())
{
byte_t instr = HPACK(if_id_next->icode, if_id_next->ifun);
sim_log("Fetch: Instruction code %s (0x%x) invalid\n",
iname(instr), instr);
nstatus = EXC_INSTR;
}
pc_next->exception = (nstatus == EXC_NONE) ? EXC_NONE : EXC_BUBBLE;
if_id_next->stage_pc = fetchpc;
if_id_next->exception = nstatus;
/* Recompute icode for one-write implementation of popl */
if_id_next->icode = gen_new_D_icode();
sim_log("Fetch: Fetched %s at 0x%x, ra = %s, rb = %s, valp = 0x%x, status = %s\n",
iname(HPACK(if_id_next->icode, if_id_next->ifun)),
if_id_next->stage_pc,
reg_name(if_id_next->ra), reg_name(if_id_next->rb),
if_id_next->valp,
exc_name(nstatus));
}
{
if (id >= 0 && id < REG_NONE)
return reg_table[id].name;
else
return reg_table[REG_NONE].name;
}
/* Is the given register ID a valid program register? */
int reg_valid(reg_id_t id)
{
return id >= 0 && id < REG_NONE && reg_table[id].id == id;
}
instr_t instruction_set[] =
{
{"nop", HPACK(I_NOP, F_NONE), 1, NO_ARG, 0, 0, NO_ARG, 0, 0 },
{"halt", HPACK(I_HALT, F_NONE), 1, NO_ARG, 0, 0, NO_ARG, 0, 0 },
{"rrmovl", HPACK(I_RRMOVL, F_NONE), 2, R_ARG, 1, 1, R_ARG, 1, 0 },
/* Conditional move instructions are variants of RRMOVL */
{"cmovle", HPACK(I_RRMOVL, C_LE), 2, R_ARG, 1, 1, R_ARG, 1, 0 },
{"cmovl", HPACK(I_RRMOVL, C_L), 2, R_ARG, 1, 1, R_ARG, 1, 0 },
{"cmove", HPACK(I_RRMOVL, C_E), 2, R_ARG, 1, 1, R_ARG, 1, 0 },
{"cmovne", HPACK(I_RRMOVL, C_NE), 2, R_ARG, 1, 1, R_ARG, 1, 0 },
{"cmovge", HPACK(I_RRMOVL, C_GE), 2, R_ARG, 1, 1, R_ARG, 1, 0 },
{"cmovg", HPACK(I_RRMOVL, C_G), 2, R_ARG, 1, 1, R_ARG, 1, 0 },
/* arg1hi indicates number of bytes */
{"irmovl", HPACK(I_IRMOVL, F_NONE), 6, I_ARG, 2, 4, R_ARG, 1, 0 },
{"rmmovl", HPACK(I_RMMOVL, F_NONE), 6, R_ARG, 1, 1, M_ARG, 1, 0 },
{"mrmovl", HPACK(I_MRMOVL, F_NONE), 6, M_ARG, 1, 0, R_ARG, 1, 1 },
{"addl", HPACK(I_ALU, A_ADD), 2, R_ARG, 1, 1, R_ARG, 1, 0 },
{"subl", HPACK(I_ALU, A_SUB), 2, R_ARG, 1, 1, R_ARG, 1, 0 },
if (!strcmp(name, reg_table[i].name))
return reg_table[i].id;
return REG_NONE;
}
char *reg_name(reg_id_t id)
{
if (id < REG_NONE)
return reg_table[id].name;
else
return reg_table[REG_NONE].name;
}
instr_t instruction_set[] =
{
{"nop", HPACK(I_NOP, 0), 1, NO_ARG, 0, 0, NO_ARG, 0, 0 },
{"halt", HPACK(I_HALT, 0), 1, NO_ARG, 0, 0, NO_ARG, 0, 0 },
{"rrmovl", HPACK(I_RRMOVL, 0), 6, R_ARG, 1, 1, R_ARG, 1, 0 },
/* arg1hi indicates number of bytes */
{"irmovl", HPACK(I_IRMOVL, 0), 6, I_ARG, 2, 4, R_ARG, 1, 0 },
{"rmmovl", HPACK(I_RMMOVL, 0), 6, R_ARG, 1, 1, M_ARG, 1, 0 },
{"mrmovl", HPACK(I_MRMOVL, 0), 6, M_ARG, 1, 0, R_ARG, 1, 1 },
{"addl", HPACK(I_ALU, A_ADD), 6, R_ARG, 1, 1, R_ARG, 1, 0 },
{"subl", HPACK(I_ALU, A_SUB), 6, R_ARG, 1, 1, R_ARG, 1, 0 },
{"andl", HPACK(I_ALU, A_AND), 6, R_ARG, 1, 1, R_ARG, 1, 0 },
{"xorl", HPACK(I_ALU, A_XOR), 6, R_ARG, 1, 1, R_ARG, 1, 0 },
/* JB ajout sall et sarl (shift arithmetic left/right) */
{"sall", HPACK(I_ALU, A_SAL), 6, R_ARG, 1, 1, R_ARG, 1, 0 },
{"sarl", HPACK(I_ALU, A_SAR), 6, R_ARG, 1, 1, R_ARG, 1, 0 },
/* arg1hi indicates number of bytes */
{"jmp", HPACK(I_JXX, J_YES), 5, I_ARG, 1, 4, NO_ARG, 0, 0 },
if (!strcmp(name, reg_table[i].name))
return reg_table[i].id;
return REG_NONE;
}
char *reg_name(reg_id_t id)
{
if (id < REG_NONE)
return reg_table[id].name;
else
return reg_table[REG_NONE].name;
}
instr_t instruction_set[] =
{
{"nop", HPACK(I_NOP, 0), 1, NO_ARG, 0, 0, NO_ARG, 0, 0 },
{"halt", HPACK(I_HALT, 0), 1, NO_ARG, 0, 0, NO_ARG, 0, 0 },
{"rrmovl", HPACK(I_RRMOVL, 0), 6, R_ARG, 1, 1, R_ARG, 1, 0 },
/* arg1hi indicates number of bytes */
{"irmovl", HPACK(I_IRMOVL, 0), 6, I_ARG, 2, 4, R_ARG, 1, 0 },
{"rmmovl", HPACK(I_RMMOVL, 0), 6, R_ARG, 1, 1, M_ARG, 1, 0 },
{"mrmovl", HPACK(I_MRMOVL, 0), 6, M_ARG, 1, 0, R_ARG, 1, 1 },
{"addl", HPACK(I_ALU, A_ADD), 6, R_ARG, 1, 1, R_ARG, 1, 0 },
{"subl", HPACK(I_ALU, A_SUB), 6, R_ARG, 1, 1, R_ARG, 1, 0 },
{"andl", HPACK(I_ALU, A_AND), 6, R_ARG, 1, 1, R_ARG, 1, 0 },
{"xorl", HPACK(I_ALU, A_XOR), 6, R_ARG, 1, 1, R_ARG, 1, 0 },
/* intruction mul */
{"mul", HPACK(I_MUL, 0), 2, R_ARG, 1, 1, R_ARG, 1, 0 },
{"mul1", HPACK(I_MUL, 1), 2, R_ARG, 1, 1, R_ARG, 1, 0 },
{"mul2", HPACK(I_MUL, 2), 2, R_ARG, 1, 1, R_ARG, 1, 0 },
/* JB ajout sall et sarl (shift arithmetic left/right) */
