/*************************************************************************
* FUNCTION
* HW_TDMA_Enable_CTIRQ1
*
* DESCRIPTION
* This function enable TDMA module CTIRQ1.
*
* PARAMETERS
*
* RETURNS
* None
*
* GLOBALS AFFECTED
*
*************************************************************************/
void HW_TDMA_Enable_CTIRQ1(void)
{
kal_uint32 dX;
HW_TDMA_Start();
HW_WRITE(CTIRQ1, MD_DRV_TQ_CTIRQ1);
HW_WRITE(TQ_WRAP, MD_DRV_TQ_WRAP_COUNT-1);
HW_WRITE(TQ_EVENT_VALID, MD_DRV_TQ_VALIDATE_COUNT);
dX = HW_READ(EVENT_ENA(0));
dX |= 0x2;
HW_WRITE(EVENT_ENA(0), dX);
}
void Frequency_hopping_enable( void )
{
#if MD_DRV_IS_UDVT_FH_SUPPORT
int d16;
sFHset FHset = { (1 << FREE_RUN_BASE), 0 }; // -1%
/*Enable DDS. Let RG_MDDS_EN[0] = 1*/
/*It is done in INT_SetPLL()*/
/*Power on TDMA*/
HW_TDMA_Start();
/*Init TQ_WRAP and Event validate*/
HW_WRITE( TQ_WRAP, MD_DRV_TQ_WRAP_COUNT-1 );
HW_WRITE( TQ_EVENT_VALID, MD_DRV_TQ_VALIDATE_COUNT );
/*Low index of FH_table_UDVT first*/
d16 = HW_READ(TDMA_FHCON(0));
d16 &= TDMA_FHCON0_MASK;
HW_WRITE( TDMA_FHCON(0), d16 );
/*MNPLL free run range*/
L1D_SET_MNPLL_FREE_RUN_RANGE();
/*EFPLL free run range*/
L1D_SET_EFPLL_FREE_RUN_RANGE();
/*MNPLL FH type*/
L1D_SET_MNPLL_FH_TYPE();
/*EFPLL FH type*/
L1D_SET_EFPLL_FH_TYPE();
/*Reset FH TDMA timer*/
ReSet_MPLLFH_FHSTR();
/*init frequency hopping table*/
FH_init_FHtable();
FH_set_fhset( 0, &FHset );
HW_WRITE( TQ_BIAS_CONT, 0 );
HW_WRITE( TDMA_FHSTR(0), 0 );
#endif
}
/**********************************************************
Description : Wait for 32KHz clock srouce stable.
Input : None
Output : None
***********************************************************/
void WaitFor32KStable(void)
{
#if ( defined(MT6516) && defined(__APPLICATION_PROCESSOR__) ) || defined(MT6270A)
return;
#else /* MT6516 && __APPLICATION_PROCESSOR__ */
kal_uint32 i;
/* 32K calibration */
HW_TDMA_Start();
for (i = 0; i < 1000; i++) {
}
HW_wait_32k_start();
#endif /* MT6516 && __APPLICATION_PROCESSOR__ */
}
