// These functions may be called at system bootup time,
// so we need to keep the code and data in primary MAUI
void L1D_HW_TDMA_AUX_TIME_SETUP(kal_uint16 event0, kal_uint16 event1)
{
kal_uint16 d16 = (kal_uint16)HW_READ(TDMA_AUXEVENA);
HW_WRITE(TDMA_AUXEV0, event0);
HW_WRITE(TDMA_AUXEV1, event1);
HW_WRITE(TDMA_AUXEVENA, (d16|0x3));
}
static void FH_set_fhset( unsigned short win_idx, sFHset* _fhset )
{
/*MNPLL*/
HW_WRITE( MNPLL_FHSET(win_idx,0), ( _fhset->fh_set_l & 0xFFFF) );
HW_WRITE( MNPLL_FHSET(win_idx,1), ( (_fhset->fh_set_l>>16) & 0xFFFF) );
HW_WRITE( MNPLL_FHSET(win_idx,2), ( _fhset->fh_set_h & 0xFFFF) );
HW_WRITE( MNPLL_FHSET(win_idx,3), ( (_fhset->fh_set_h>>16) & 0xFFFF) );
}
/*************************************************************************
* FUNCTION
* HW_TDMA_Enable_CTIRQ1
*
* DESCRIPTION
* This function enable TDMA module CTIRQ1.
*
* PARAMETERS
*
* RETURNS
* None
*
* GLOBALS AFFECTED
*
*************************************************************************/
void HW_TDMA_Enable_CTIRQ1(void)
{
kal_uint32 dX;
HW_TDMA_Start();
HW_WRITE(CTIRQ1, MD_DRV_TQ_CTIRQ1);
HW_WRITE(TQ_WRAP, MD_DRV_TQ_WRAP_COUNT-1);
HW_WRITE(TQ_EVENT_VALID, MD_DRV_TQ_VALIDATE_COUNT);
dX = HW_READ(EVENT_ENA(0));
dX |= 0x2;
HW_WRITE(EVENT_ENA(0), dX);
}
void HW_wait_32k_start(void)
{
#if MD_DRV_IS_CENTRALIZED_SMM_CHIP
#ifdef __UE_SIMULATOR__
#undef FRC_CMD_MAGIC_VALUE
#define FRC_CMD_MAGIC_VALUE 0x62760000
#endif
/*CSMM use 26M to calibrate 32K at TOPSM HW module*/
kal_uint32 result;
int count = 0;
int waiting_32k_count = 80000;
kal_uint32 tmp_T0 = 0, tmp_T1 = 0, tmp_D0 = 0, tmp_D1 = 0;
/* Enable FRC for FM. */
HW_WRITE( SM_FRC_CON, (FRC_CMD_MAGIC_VALUE+0x00000001) );
HW_WRITE( SM_FM_CAL, 2 ); /*calibrate 2T 32K, ideal got 1586.9T 26M*/
while(count < waiting_32k_count)
{
/* Enable FM and no need to Unmask FM INT. */
HW_WRITE(SM_FM_CON, 0x11);
/* Polling until FM_EN bit is cleared. */
while((HW_READ(SM_FM_CON) & 0x1)) ;
tmp_T0 = (HW_READ(SM_FM_T0)) & 0xFFFFFF;
tmp_D0 = (HW_READ(SM_FM_T0)) >> 24;
tmp_T1 = (HW_READ(SM_FM_T1)) & 0xFFFFFF;
tmp_D1 = (HW_READ(SM_FM_T1)) >> 24;
if( tmp_T1 > tmp_T0 )
{
result = (tmp_T1*26+tmp_D1) - (tmp_T0*26+tmp_D0);
}
else /* 1MHz FRC wrap case: */
{
result = ((tmp_T1+0x1000000)*26+tmp_D1) - (tmp_T0*26+tmp_D0);
}
if( FM_RESULT_LOWER_BOUND < result && result < FM_RESULT_UPPER_BOUND )
{
/* Clear INT of FM. Need to set bit[4] to mask it. */
HW_WRITE(SM_FM_CON, 0x110);
break;
}
count++;
}
#else
#error "Please implement HW_wait_32k_start() for non-centralized-sleep-mode chip"
#endif
}
static void FH_init_FHtable(void)
{
int i;
unsigned int d16;
/*Indicate write FH table at addr 0*/
HW_WRITE( TDMA_FHCON(2), TDMA_FHCON2_DEFAULT );
/*Write FH table*/
for( i = 0 ; i < FH_table_UDVT_SIZE; i++ )
{ d16 = TDMA_FHCON3_DEFAULT_INT | FH_table_UDVT[i];
HW_WRITE( TDMA_FHCON(3), d16 );
MD_DRV_WAIT_TIME_QB(1);
}
}
int console_init( Console* cons )
{
ptr base = 0;
int status = 0;
uint channel = 0;
uint control = 0;
base = console_getbase( cons );
channel = cons->channel == CONSOLE_1 ? COM1 : COM2;
/* Reset port first */
cons->write_bytes = 0;
cons->read_bytes = 0;
status = bwsetspeed( channel, cons->speed );
control = HW_READ( base, UART_LCRH_OFFSET );
if( cons->fifo ){
control |= FEN_MASK;
} else {
control &= ( ~FEN_MASK );
}
if( cons->dbl_stop ){
control |= STP2_MASK;
}
HW_WRITE( base, UART_LCRH_OFFSET, control );
ASSERT( status == ERR_NONE );
/* Leave no garbage */
console_drain( cons );
return ERR_NONE;
}
static void ReSet_MPLLFH_FHSTR( void )
{
int i;
for( i = 0; i < 6; i++ )
{ HW_WRITE(TDMA_FHSTR(i), MD_DRV_TQ_MAXIMUM); }
}
static inline int clk_enable_direct( uint clk, uint ctrl )
{
ptr base = clk_getbase( clk );
HW_WRITE( base, TIMER_CTRL_OFFSET, ctrl );
return ERR_NONE;
}
int clk_clear( uint clk )
{
ptr base = clk_getbase( clk );
HW_WRITE( base, TIMER_CLR_OFFSET, 1 );
return ERR_NONE;
}
static void MD_DRV_L1D_DisableAllIRQ( void )
{
HW_WRITE( EVENT_ENA(0), (HW_READ(EVENT_ENA(0))&0x0000)|MD_DRV_EVTENA0_SLOW_EN_SEL );
HW_WRITE( EVENT_ENA(1), (HW_READ(EVENT_ENA(1))&0x0080) );
HW_WRITE( EVENT_ENA(2), 0x0000 );
HW_WRITE( EVENT_ENA(3), 0x0000 );
HW_WRITE( EVENT_ENA(4), 0x0000 );
HW_WRITE( EVENT_ENA(5), 0x0000 );
HW_WRITE( EVENT_ENA(6), 0x0000 );
#if MD_DRV_IS_TXPC_CL_AUXADC_SUPPORT
HW_WRITE( EVENT_ENA(7), (HW_READ(EVENT_ENA(7))&0x0003) );
#endif
#if MD_DRV_IS_CHIP_MT6290 || MD_DRV_IS_CHIP_MT6595 || MD_DRV_IS_CHIP_MT6752_MD1 || MD_DRV_IS_CHIP_MT6752_MD2 || MD_DRV_IS_CHIP_MT6735
HW_WRITE( EVENT_ENA(8), 0x0000 );
HW_WRITE( EVENT_ENA(9), 0x0000 );
#endif
}
void Frequency_hopping_enable( void )
{
#if MD_DRV_IS_UDVT_FH_SUPPORT
int d16;
sFHset FHset = { (1 << FREE_RUN_BASE), 0 }; // -1%
/*Enable DDS. Let RG_MDDS_EN[0] = 1*/
/*It is done in INT_SetPLL()*/
/*Power on TDMA*/
HW_TDMA_Start();
/*Init TQ_WRAP and Event validate*/
HW_WRITE( TQ_WRAP, MD_DRV_TQ_WRAP_COUNT-1 );
HW_WRITE( TQ_EVENT_VALID, MD_DRV_TQ_VALIDATE_COUNT );
/*Low index of FH_table_UDVT first*/
d16 = HW_READ(TDMA_FHCON(0));
d16 &= TDMA_FHCON0_MASK;
HW_WRITE( TDMA_FHCON(0), d16 );
/*MNPLL free run range*/
L1D_SET_MNPLL_FREE_RUN_RANGE();
/*EFPLL free run range*/
L1D_SET_EFPLL_FREE_RUN_RANGE();
/*MNPLL FH type*/
L1D_SET_MNPLL_FH_TYPE();
/*EFPLL FH type*/
L1D_SET_EFPLL_FH_TYPE();
/*Reset FH TDMA timer*/
ReSet_MPLLFH_FHSTR();
/*init frequency hopping table*/
FH_init_FHtable();
FH_set_fhset( 0, &FHset );
HW_WRITE( TQ_BIAS_CONT, 0 );
HW_WRITE( TDMA_FHSTR(0), 0 );
#endif
}
/*************************************************************************
* FUNCTION
* USC_Get_TimeStamp
*
* DESCRIPTION
* This function calculate the frame number.
*
* PARAMETERS
* none
*
* RETURNS
* Frame number since system power up
*
*************************************************************************/
kal_uint32 DEVDRV_LS_INTSRAM_ROCODE USC_Get_TimeStamp( void )
{
#if defined(__ALIGN_2G_CLOCK__)
kal_uint32 uscnti,curFrame,_savedMask;
_savedMask = SaveAndSetIRQMask();
uscnti= ust_get_current_time();
if (uscnti >= Pre_USCNTI) {
curFrame = USCNT_TO_FRAME( uscnti - Pre_USCNTI ); // dur/3250/(120/26)
} else {
curFrame = USCNT_TO_FRAME((USCNT_WRAP - Pre_USCNTI) + uscnti);
}
FrameCount += curFrame;
Pre_USCNTI += FRAME_TO_USCNT(curFrame);
if( Pre_USCNTI > USCNT_WRAP )
{
Pre_USCNTI -= USCNT_WRAP;
}
RestoreIRQMask(_savedMask);
return FrameCount;
#else
kal_uint32 uscnti,curFrame,_savedMask;
_savedMask = SaveAndSetIRQMask();
#if defined(__HW_OSTICK_CNT__)
HW_WRITE(OST_CMD, CMD_MAGIC_VALUE | 0x02);
curFrame = HW_READ(OST_TIMER_CNT_R);
#else
uscnti= ust_get_current_time();
if (uscnti >= Pre_USCNTI) {
Total_USCNTI += (uscnti - Pre_USCNTI);
} else {
Total_USCNTI += ((USCNT_WRAP - Pre_USCNTI) + uscnti);
}
Pre_USCNTI = uscnti;
curFrame = USCNT_TO_FRAME(Total_USCNTI);
#endif
RestoreIRQMask(_savedMask);
return curFrame;
#endif
}
void SetupMPLLFH( void )
{
ReSet_MPLLFH_FHSTR();
if( MPLL_FH_idx%FH_table_UDVT_SIZE < 32)
{ l1dfh_udvt.FHset_Modem.fh_set_l = 1 << (MPLL_FH_idx%FH_table_UDVT_SIZE);
l1dfh_udvt.FHset_Modem.fh_set_h = 0;
}
else
{ l1dfh_udvt.FHset_Modem.fh_set_l = 0;
l1dfh_udvt.FHset_Modem.fh_set_h = 1 << ((MPLL_FH_idx%FH_table_UDVT_SIZE)-32);
}
MPLL_FH_idx++;
FH_set_fhset( 0 , &l1dfh_udvt.FHset_Modem );
HW_WRITE( TQ_BIAS_CONT, 0 );
HW_WRITE( TDMA_FHSTR(0), 256 );
}
int clk_disable( uint clk )
{
ptr base = clk_getbase( clk );
HW_WRITE( base, TIMER_CTRL_OFFSET, 0 );
clkLastVal[ clk ] = 0;
return ERR_NONE;
}
/*************************************************************************
* FUNCTION
* USC_Stop
*
* DESCRIPTION
* This function stops the uscounter.
*
* PARAMETERS
* none
*
* RETURNS
* none
*
*************************************************************************/
void USC_Stop()
{
#ifdef ESIM_BUILD_CONFIG
HW_WRITE(USCNT_CON, 1);
#else
kal_uint32 SHOULD_NOT_STOP_US_COUNTER = 0;
ASSERT(SHOULD_NOT_STOP_US_COUNTER);
//DRV_WriteReg32(BASE_ADDR_MDTOPSM+0x80, 1);
#endif
}
void uVtc_Disable(void)
{
uio_handle Vtc_handle;
assert(gVtcInfo.isInitialized == XIL_COMPONENT_IS_READY);
uio_get_Handler(&gVtcInfo, &Vtc_handle);
assert(Vtc_handle.IsReady == XIL_COMPONENT_IS_READY);
HW_WRITE(Vtc_handle.Control_bus_BaseAddress, VTC_CR , 0x0);
uio_release_handle(&gVtcInfo,&Vtc_handle);
}
void uTpg_Disable(void)
{
uio_handle tpg_handle;
assert(gTpgInfo.isInitialized == XIL_COMPONENT_IS_READY);
uio_get_Handler(&gTpgInfo, &tpg_handle);
assert(tpg_handle.IsReady == XIL_COMPONENT_IS_READY);
HW_WRITE(tpg_handle.Control_bus_BaseAddress, TPG_CONTROL, TPG_RST_RESET);
uio_release_handle(&gTpgInfo,&tpg_handle);
}
void uVtc_Enable(void)
{
uio_handle Vtc_handle;
assert(gVtcInfo.isInitialized == XIL_COMPONENT_IS_READY);
uio_get_Handler(&gVtcInfo, &Vtc_handle);
assert(Vtc_handle.IsReady == XIL_COMPONENT_IS_READY);
HW_WRITE(Vtc_handle.Control_bus_BaseAddress, VTC_CR , 0x3F7FF0F); // Control register, has to be written at last.
uio_release_handle(&gVtcInfo,&Vtc_handle);
}
void uTpg_Enable(void)
{
uio_handle tpg_handle;
assert(gTpgInfo.isInitialized == XIL_COMPONENT_IS_READY);
uio_get_Handler(&gTpgInfo, &tpg_handle);
assert(tpg_handle.IsReady == XIL_COMPONENT_IS_READY);
HW_WRITE(tpg_handle.Control_bus_BaseAddress, TPG_CONTROL, (TPG_CTL_EN_MASK | TPG_CTL_RUE_MASK));
uio_release_handle(&gTpgInfo,&tpg_handle);
}
void uVtc_Configure(VtcConfig *config)
{
uio_handle Vtc_handle;
//assert(config != NULL);
assert(gVtcInfo.isInitialized == XIL_COMPONENT_IS_READY);
uio_get_Handler(&gVtcInfo, &Vtc_handle);
assert(Vtc_handle.IsReady == XIL_COMPONENT_IS_READY);
HW_WRITE(Vtc_handle.Control_bus_BaseAddress, VTC_ACT_SIZE, (config->vActive << SHIFT_16) | config->hActive);
HW_WRITE(Vtc_handle.Control_bus_BaseAddress, VTC_ENCODE , 0x00000002);
HW_WRITE(Vtc_handle.Control_bus_BaseAddress, VTC_POL , 0x0000003F);
HW_WRITE(Vtc_handle.Control_bus_BaseAddress, VTC_HSIZE , config->hTotal);
HW_WRITE(Vtc_handle.Control_bus_BaseAddress, VTC_VSIZE , config->vTotal);
HW_WRITE(Vtc_handle.Control_bus_BaseAddress, VTC_HSYNC , (config->hSync_end << SHIFT_16) | config->hSync_start);
HW_WRITE(Vtc_handle.Control_bus_BaseAddress, VTC_VBLANKH , (config->vBlankh_end << SHIFT_16) | config->vBlankh_start);
HW_WRITE(Vtc_handle.Control_bus_BaseAddress, VTC_VSYNC , (config->vSync_end << SHIFT_16) | config->vSync_start);
HW_WRITE(Vtc_handle.Control_bus_BaseAddress, VTC_VSYNCH , (config->vSyncH_end << SHIFT_16) | config->vSyncH_start);
uio_release_handle(&gVtcInfo,&Vtc_handle);
}
int clk_reset( uint clk, uint initial )
{
ptr base = clk_getbase( clk );
uint ctrlVal = 0;
int status;
ctrlVal = HW_READ( base, TIMER_CTRL_OFFSET );
status = clk_disable( clk );
ASSERT( status == ERR_NONE );
HW_WRITE( base, TIMER_LDR_OFFSET, initial );
status = clk_enable_direct( clk, ctrlVal );
ASSERT( status == ERR_NONE );
return ERR_NONE;
}
/* Send one byte through the UART port.
Set block to 1 to busy wait until ready bit is set.
*/
static inline int console_transmit( Console* cons, uchar data, uint blocking )
{
ptr base = console_getbase( cons );
do {
if( console_ready_write( cons ) ){
HW_WRITE( base, UART_DATA_OFFSET, data );
cons->write_bytes += 1;
break;
} else if( blocking ){
continue;
} else {
return ERR_CONSOLE_NOT_READY;
}
} while( 1 );
return ERR_NONE;
}
void uTpg_Configure(TpgConfig *config)
{
uio_handle tpg_handle;
//assert(config != NULL);
assert(gTpgInfo.isInitialized == XIL_COMPONENT_IS_READY);
uio_get_Handler(&gTpgInfo, &tpg_handle);
assert(tpg_handle.IsReady == XIL_COMPONENT_IS_READY);
HW_WRITE(tpg_handle.Control_bus_BaseAddress, TPG_PATTERN_CONTROL, config->pattern);
HW_WRITE(tpg_handle.Control_bus_BaseAddress, TPG_MOTION_SPEED, config->motion_param);
HW_WRITE(tpg_handle.Control_bus_BaseAddress, TPG_ACTIVE_SIZE, config->frm_height << SHIFT_16 | config->frm_width);
HW_WRITE(tpg_handle.Control_bus_BaseAddress, TPG_ZPLATE_HOR_CONTROL, config->h_zplate);
HW_WRITE(tpg_handle.Control_bus_BaseAddress, TPG_ZPLATE_VER_CONTROL, config->v_zplate);
HW_WRITE(tpg_handle.Control_bus_BaseAddress, TPG_BOX_SIZE, config->box_size);
HW_WRITE(tpg_handle.Control_bus_BaseAddress, TPG_BOX_COLOR, config->box_color);
uio_release_handle(&gTpgInfo,&tpg_handle);
}
int clk_enable( uint clk, uint mode, uint clksrc, uint initial )
{
ptr base = clk_getbase( clk );
uint control = 0;
ASSERT( mode < CLK_MODE_COUNT &&
clksrc < CLK_SRC_COUNT );
base = clk_getbase( clk );
control = TIMER_ENABLE_MASK;
switch( mode ){
case CLK_MODE_FREE_RUN:
// Default
break;
case CLK_MODE_INTERRUPT:
control |= TIMER_MODE_MASK;
break;
}
switch( clksrc ){
case CLK_SRC_2KHZ:
// Default
break;
case CLK_SRC_508KHZ:
control |= TIMER_CLKSEL_MASK;
break;
}
HW_WRITE( base, TIMER_LDR_OFFSET, initial );
/* Initialize clock book keeping */
clkLastVal[ clk ] = initial;
clk_enable_direct( clk, control );
return ERR_NONE;
}
/*************************************************************************
* FUNCTION
* USC_Start
*
* DESCRIPTION
* This function starts the uscounter.
*
* PARAMETERS
* none
*
* RETURNS
* none
*
*************************************************************************/
void USC_Start()
{
#ifdef ESIM_BUILD_CONFIG
HW_WRITE(USCNT_CON, 1);
#elif !defined(__CENTRALIZED_SLEEP_MANAGER__)
#define FRC_CON (TOPSM_base+0x80)
#if defined(MT6290)
#define ALC_CON (0x90000000UL)
DRV_Reg32(FRC_CON) = 0x72080001;
DRV_Reg32(ALC_CON) = 0x00000001;
#elif defined(MT6595)||(defined(MT6752)&&defined(__MD1__))||defined(MT6735)
#define ALC_CON ((volatile kal_uint32*)BASE_ADDR_ALC)
PDN_CLR(PDN_TOPSM);
DRV_Reg32(FRC_CON) = 0x11530001;
DRV_Reg32(ALC_CON) = 0x00000001;
#endif /* MTxxxx */
#else
MD_TOPSM_EnableFRC();
#endif
}
void L1D_Xmode_Latch(void)
{
unsigned short d16;
unsigned short ctrl = 0x1C3F; // SCTRL_IMOD(0,29);
unsigned long data = 0x0FBDD4D0; // CW251[D19]:DCXO_XMODE_LATCH = 0x1
volatile long addr;
unsigned long BSI_base80 = 0x83070000;
unsigned long dummy_read;
/* init BSI */
HW_WRITE( PDN_CLR2, PDN_CON_BSI );
HW_WRITE( PDN_CLR4, PDN_CON_BSI );
d16 = HW_READ( ((APBADDR) (BSI_base80+0x0C08)) ); // BSI_IO_CON
d16 &= ~( 0x1<<8 ); /* clear RESET_MODE (bit 8) */
HW_WRITE( ((APBADDR) (BSI_base80+0x0C08)), d16 ); // BSI_IO_CON
/* immediately send BSI */
HW_WRITE( ((APBADDR32)(BSI_base80+0x0000)), 0x0008001 ); // HW_WRITE( BSI_CON, SCTRL_IMOD_MAIN );
addr = (long)((APBADDR) (BSI_base80+0x0004)); // BSI_Dn_CON(0);
HW_WRITE( (APBADDR)addr, ctrl ); addr += 4;
HW_WRITE( (APBADDR32)(addr), (data) ); // HW_WRITE_BSI_DATA( addr, data );
dummy_read = HW_READ( (APBADDR32)(addr) );
HW_WRITE( ((APBADDR) (BSI_base80+0x0508)), 0x8000 ); // HW_WRITE( GSM_BSI_ACTUPT, 0x8000 );
dummy_read = HW_READ( (APBADDR32)(addr) );
(void)dummy_read;
HW_WRITE( ((APBADDR32)(BSI_base80+0x0000)), 0x8401 ); // HW_WRITE( BSI_CON, SCTRL_IMOD_SEND );
/* immediately mode end */
HW_WRITE( ((APBADDR32)(BSI_base80+0x0000)), 0x0008001 ); // HW_WRITE( BSI_CON, SCTRL_MAIN );
HW_WRITE( ((APBADDR32)(BSI_base80+0x0500)), 0xFFFFFFFF ); // MT6280 is 42
HW_WRITE( ((APBADDR32)(BSI_base80+0x0504)), 0x000003FF );
}
/*************************************************************************
* FUNCTION
* USC_Cal_32KFM
*
* DESCRIPTION
* This function calibrates the uscounter.
*
* PARAMETERS
* Cal_32K - 32K crystal counts
* Cal_26M - counts of 26M clock when 32K crystal count to Cal_32K
*
* RETURNS
* none
*
*************************************************************************/
void USC_Cal_32KFM( kal_uint32 Cal_32K, kal_uint32 Cal_26M)
{
double Ratio;
Ratio = ((double)Cal_26M)* ( ((double)USCNT_FREQ) * ( (double)(1<<18) ) / 26000000 ) / ((double)Cal_32K);
HW_WRITE(F32K_FM, (kal_uint32)(Ratio));
}
/*************************************************************************
* FUNCTION
* HW_TDMA_Start
*
* DESCRIPTION
* This function powers on TDMA module.
*
* PARAMETERS
*
* RETURNS
* None
*
* GLOBALS AFFECTED
*
*************************************************************************/
void HW_TDMA_Start(void)
{
HW_WRITE( PDN_CLR2, PDN_CON_TDMA ); /*power on TDMA*/
}
static void MD_DRV_L1D_PWR_SLEEP( void )
{
#if MD_DRV_IS_CHIP_MT6250 || MD_DRV_IS_CHIP_MT6280 || MD_DRV_IS_CHIP_MT6583_MD1 || MD_DRV_IS_CHIP_MT6583_MD2 || MD_DRV_IS_CHIP_MT6572 || MD_DRV_IS_CHIP_MT6290 || MD_DRV_IS_CHIP_MT6595 || MD_DRV_IS_CHIP_MT6752_MD1 || MD_DRV_IS_CHIP_MT6752_MD2 || MD_DRV_IS_CHIP_MT6735
HW_WRITE( PDN_SET2, SLPOFF&MODEMSYS_MASK );
HW_WRITE( MD2G_PDN_SET0, SLPOFF&MD2G_MASK1 );
HW_WRITE( MD2G_PDN_SET2, SLPOFF&MD2G_MASK2 );
HW_WRITE( PDN_CLR2, SLPON &MODEMSYS_MASK );
HW_WRITE( MD2G_PDN_CLR0, SLPON &MD2G_MASK1 );
HW_WRITE( MD2G_PDN_CLR2, SLPON &MD2G_MASK2 );
#elif MD_DRV_IS_CHIP_MT6575
HW_WRITE( PDN_SET2, SLPOFF&MCUSYS_MASK1 );
HW_WRITE( PDN_SET3, SLPOFF&MCUSYS_MASK2 );
HW_WRITE( MD2G_PDN_SET1, SLPOFF&MD2G_MASK );
HW_WRITE( PDN_CLR2, SLPON &MCUSYS_MASK1 );
HW_WRITE( PDN_CLR3, SLPON &MCUSYS_MASK2 );
HW_WRITE( MD2G_PDN_CLR1, SLPON &MD2G_MASK );
#elif MD_DRV_IS_CHIP_MT6573
HW_WRITE( PDN_SET2, SLPOFF&MCUSYS_MASK );
HW_WRITE( MD2G_PDN_SET1, SLPOFF&MD2G_MASK );
HW_WRITE( PDN_CLR2, SLPON &MCUSYS_MASK );
HW_WRITE( MD2G_PDN_CLR1, SLPON &MD2G_MASK );
HW_WRITE( AP_PDN_CLR1, SLPON &APMCUSYS_MASK );
#elif MD_DRV_IS_CHIP_MT6276
HW_WRITE( PDN_SET2, SLPOFF&MCUSYS_MASK );
HW_WRITE( MD2G_PDN_SET1, SLPOFF&MD2G_MASK );
HW_WRITE( PDN_CLR2, SLPON &MCUSYS_MASK );
HW_WRITE( MD2G_PDN_CLR1, SLPON &MD2G_MASK );
#else
#error "Please check PDN related settings"
#endif
}
/*************************************************************************
* FUNCTION
* USC_Stop
*
* DESCRIPTION
* This function stops the uscounter.
*
* PARAMETERS
* none
*
* RETURNS
* none
*
*************************************************************************/
void USC_Stop()
{
HW_WRITE(USCNT_CON,USCNT_STOP_CODE);
}
