コード例 #1
0
int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	struct rtc_time tm;
	int rcode = 0;
	int old_bus;

	/* switch to correct I2C bus */
	old_bus = I2C_GET_BUS();
	I2C_SET_BUS(CONFIG_SYS_RTC_BUS_NUM);

	switch (argc) {
	case 2:			/* set date & time */
		if (strcmp(argv[1],"reset") == 0) {
			puts ("Reset RTC...\n");
			rtc_reset ();
		} else {
			/* initialize tm with current time */
			rcode = rtc_get (&tm);

			if(!rcode) {
				/* insert new date & time */
				if (mk_date (argv[1], &tm) != 0) {
					puts ("## Bad date format\n");
					break;
				}
				/* and write to RTC */
				rcode = rtc_set (&tm);
				if(rcode)
					puts("## Set date failled\n");
			} else {
				puts("## Get date failled\n");
			}
		}
		/* FALL TROUGH */
	case 1:			/* get date & time */
		rcode = rtc_get (&tm);

		if (rcode) {
			puts("## Get date failled\n");
			break;
		}

		printf ("Date: %4d-%02d-%02d (%sday)    Time: %2d:%02d:%02d\n",
			tm.tm_year, tm.tm_mon, tm.tm_mday,
			(tm.tm_wday<0 || tm.tm_wday>6) ?
				"unknown " : RELOC(weekdays[tm.tm_wday]),
			tm.tm_hour, tm.tm_min, tm.tm_sec);

		break;
	default:
		cmd_usage(cmdtp);
		rcode = 1;
	}

	/* switch back to original I2C bus */
	I2C_SET_BUS(old_bus);

	return rcode;
}
コード例 #2
0
ファイル: dtt.c プロジェクト: 01hyang/u-boot
void dtt_init(void)
{
	int old_bus;

	/* switch to correct I2C bus */
	old_bus = I2C_GET_BUS();
	I2C_SET_BUS(CONFIG_SYS_DTT_BUS_NUM);

	_initialize_dtt();

	/* switch back to original I2C bus */
	I2C_SET_BUS(old_bus);
}
コード例 #3
0
int tps65911_read(u8 addr, u8* buf, int length)
{
	int old_bus;

	old_bus = I2C_GET_BUS();
	I2C_SET_BUS(0);
	if (i2c_read(TPS65911_SLAVE_ADDR, addr, 0x1, buf, length) != 0) {
		puts ("Error reading tps65911.\n");
		return -1;
	}
	if(old_bus != 0)
		I2C_SET_BUS(old_bus);
	return 0;
}
コード例 #4
0
int tps65911_config(u8 addr, u8 val)
{
	int ret;
	int old_bus;

	old_bus = I2C_GET_BUS();
	I2C_SET_BUS(0);
	ret = i2c_write(TPS65911_SLAVE_ADDR, addr, 0x1, &val, 0x1);
	if (ret != 0) {
		puts ("Error writing tps65911.\n");
	}
	if(old_bus != 0)
		I2C_SET_BUS(old_bus);
	return ret;
}
コード例 #5
0
ファイル: cmd_dtt.c プロジェクト: sparkmbox/w732_kernel_src
int do_dtt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
    int i;
    unsigned char sensors[] = CONFIG_DTT_SENSORS;
    int old_bus;

    /* switch to correct I2C bus */
    old_bus = I2C_GET_BUS();
    I2C_SET_BUS(CONFIG_SYS_DTT_BUS_NUM);

    /*
     * Loop through sensors, read
     * temperature, and output it.
     */
    for (i = 0; i < sizeof (sensors); i++)
        printf ("DTT%d: %i C\n", i + 1, dtt_get_temp (sensors[i]));

    /* switch back to original I2C bus */
    I2C_SET_BUS(old_bus);

    return 0;
}	/* do_dtt() */
コード例 #6
0
ファイル: dtt.c プロジェクト: 01hyang/u-boot
int dtt_i2c(void)
{
#if defined CONFIG_DTT_SENSORS
	int i;
	unsigned char sensors[] = CONFIG_DTT_SENSORS;
	int old_bus;

	/* Force a compilation error, if there are more then 32 sensors */
	BUILD_BUG_ON(sizeof(sensors) > 32);
	/* switch to correct I2C bus */
#ifdef CONFIG_SYS_I2C
	old_bus = i2c_get_bus_num();
	i2c_set_bus_num(CONFIG_SYS_DTT_BUS_NUM);
#else
	old_bus = I2C_GET_BUS();
	I2C_SET_BUS(CONFIG_SYS_DTT_BUS_NUM);
#endif

	_initialize_dtt();

	/*
	 * Loop through sensors, read
	 * temperature, and output it.
	 */
	for (i = 0; i < sizeof(sensors); i++)
		printf("DTT%d: %i C\n", i + 1, dtt_get_temp(sensors[i]));

	/* switch back to original I2C bus */
#ifdef CONFIG_SYS_I2C
	i2c_set_bus_num(old_bus);
#else
	I2C_SET_BUS(old_bus);
#endif
#endif

	return 0;
}
コード例 #7
0
ファイル: denali_spd_ddr2.c プロジェクト: AvalueAES/rev-sa01
/*-----------------------------------------------------------------------------
 * Function:	 initdram
 * Description:  Configures SDRAM memory banks for DDR operation.
 *		 Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 *		 via the IIC bus and then configures the DDR SDRAM memory
 *		 banks appropriately. If Auto Memory Configuration is
 *		 not used, it is assumed that no DIMM is plugged
 *-----------------------------------------------------------------------------*/
phys_size_t initdram(int board_type)
{
	unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
	unsigned long dimm_ranks[MAXDIMMS];
	unsigned long ranks;
	unsigned long rows;
	unsigned long banks;
	unsigned long cols;
	unsigned long width;
	unsigned long const sdram_freq = get_bus_freq(0);
	unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr);	/* on board dimm banks */
	unsigned long cas_latency = 0;	/* to quiet initialization warning */
	unsigned long dram_size;

	debug("\nEntering initdram()\n");

	/*------------------------------------------------------------------
	 * Stop the DDR-SDRAM controller.
	 *-----------------------------------------------------------------*/
	mtsdram(DDR0_02, DDR0_02_START_ENCODE(0));

	/*
	 * Make sure I2C controller is initialized
	 * before continuing.
	 */
	/* switch to correct I2C bus */
	I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

	/*------------------------------------------------------------------
	 * Clear out the serial presence detect buffers.
	 * Perform IIC reads from the dimm.  Fill in the spds.
	 * Check to see if the dimm slots are populated
	 *-----------------------------------------------------------------*/
	get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks);

	/*------------------------------------------------------------------
	 * Check the frequency supported for the dimms plugged.
	 *-----------------------------------------------------------------*/
	check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);

	/*------------------------------------------------------------------
	 * Check and get size information.
	 *-----------------------------------------------------------------*/
	get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks,
		      &cols, &width);

	/*------------------------------------------------------------------
	 * Check the voltage type for the dimms plugged.
	 *-----------------------------------------------------------------*/
	check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks);

	/*------------------------------------------------------------------
	 * Program registers for SDRAM controller.
	 *-----------------------------------------------------------------*/
	mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) |
		DDR0_00_DLL_START_POINT_DECODE(0x0A));

	mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) |
		DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) |
		DDR0_01_INT_MASK_ENCODE(0xFF));

	program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
			rows, &cas_latency);

	program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);

	program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);

	program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);

	/*
	 * TODO: tFAW not found in SPD.  Value of 13 taken from Sequoia
	 * board SDRAM, but may be overly conservative.
	 */
	mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
		DDR0_07_TFAW_ENCODE(13) |
		DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
		DDR0_07_AREFRESH_ENCODE(0));

	mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) |
		DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) |
		DDR0_08_DDRII_ENCODE(1));

	mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) |
		DDR0_09_RTT_0_ENCODE(0x1) |
		DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) |
		DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20));

	program_ddr0_10(dimm_ranks, ranks);

	program_ddr0_11(sdram_freq);

	mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3));

	mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) |
		DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) |
		DDR0_14_REG_DIMM_ENABLE_ENCODE(0));

	mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY));

	mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) |
		DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) |
		DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) |
		DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY));

	mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) |
		DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) |
		DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) |
		DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY));

	mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) |
		DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) |
		DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) |
		DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS));

	mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) |
		DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) |
		DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) |
		DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS));

	program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width);

	mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) |
		DDR0_23_FWC_ENCODE(0));

	program_ddr0_24(ranks);

	program_ddr0_26(sdram_freq);

	program_ddr0_27(sdram_freq);

	mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) |
		DDR0_28_EMRS2_DATA_ENCODE(0x0000));

	mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));

	mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) |
		DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));

	program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
			cols, banks);

	program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);

	denali_sdram_register_dump();

	dram_size = (width >= 64) ? 8 : 4;
	dram_size *= 1 << cols;
	dram_size *= banks;
	dram_size *= 1 << rows;
	dram_size *= ranks;
	debug("dram_size = %lu\n", dram_size);

	/* Start the SDRAM controler */
	mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
	denali_wait_for_dlllock();

#if defined(CONFIG_DDR_DATA_EYE)
	/*
	 * Map the first 1 MiB of memory in the TLB, and perform the data eye
	 * search.
	 */
	program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
	denali_core_search_data_eye();
	denali_sdram_register_dump();
	remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE);
#endif

#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
	program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0);
	sync();
	/* Zero the memory */
	debug("Zeroing SDRAM...");
#if defined(CONFIG_SYS_MEM_TOP_HIDE)
	dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE);
#else
#error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file
#endif
	/* Write modified dcache lines back to memory */
	clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE);
	debug("Completed\n");
	sync();
	remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size);

#if defined(CONFIG_DDR_ECC)
	/*
	 * If ECC is enabled, clear and enable interrupts
	 */
	if (is_ecc_enabled()) {
		u32 val;

		sync();
		/* Clear error status */
		mfsdram(DDR0_00, val);
		mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
		/* Set 'int_mask' parameter to functionnal value */
		mfsdram(DDR0_01, val);
		mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) |
			DDR0_01_INT_MASK_ALL_OFF);
#if defined(CONFIG_DDR_DATA_EYE)
		/*
		 * Running denali_core_search_data_eye() when ECC is enabled
		 * causes non-ECC machine checks.  This clears them.
		 */
		print_mcsr();
		mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
		print_mcsr();
#endif
		sync();
	}
#endif /* defined(CONFIG_DDR_ECC) */
#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */

	program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
	return dram_size;
}
コード例 #8
0
ファイル: date.c プロジェクト: Noltari/u-boot
static int do_date(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	struct rtc_time tm;
	int rcode = 0;
	int old_bus __maybe_unused;

	/* switch to correct I2C bus */
#ifdef CONFIG_DM_RTC
	struct udevice *dev;

	rcode = uclass_get_device(UCLASS_RTC, 0, &dev);
	if (rcode) {
		printf("Cannot find RTC: err=%d\n", rcode);
		return CMD_RET_FAILURE;
	}
#elif defined(CONFIG_SYS_I2C)
	old_bus = i2c_get_bus_num();
	i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
#else
	old_bus = I2C_GET_BUS();
	I2C_SET_BUS(CONFIG_SYS_RTC_BUS_NUM);
#endif

	switch (argc) {
	case 2:			/* set date & time */
		if (strcmp(argv[1],"reset") == 0) {
			puts ("Reset RTC...\n");
#ifdef CONFIG_DM_RTC
			rcode = dm_rtc_reset(dev);
			if (!rcode)
				rcode = dm_rtc_set(dev, &default_tm);
#else
			rtc_reset();
			rcode = rtc_set(&default_tm);
#endif
			if (rcode)
				puts("## Failed to set date after RTC reset\n");
		} else {
			/* initialize tm with current time */
#ifdef CONFIG_DM_RTC
			rcode = dm_rtc_get(dev, &tm);
#else
			rcode = rtc_get(&tm);
#endif
			if (!rcode) {
				/* insert new date & time */
				if (mk_date(argv[1], &tm) != 0) {
					puts ("## Bad date format\n");
					break;
				}
				/* and write to RTC */
#ifdef CONFIG_DM_RTC
				rcode = dm_rtc_set(dev, &tm);
#else
				rcode = rtc_set(&tm);
#endif
				if (rcode) {
					printf("## Set date failed: err=%d\n",
					       rcode);
				}
			} else {
				puts("## Get date failed\n");
			}
		}
		/* FALL TROUGH */
	case 1:			/* get date & time */
#ifdef CONFIG_DM_RTC
		rcode = dm_rtc_get(dev, &tm);
#else
		rcode = rtc_get(&tm);
#endif
		if (rcode) {
			puts("## Get date failed\n");
			break;
		}

		printf ("Date: %4d-%02d-%02d (%sday)    Time: %2d:%02d:%02d\n",
			tm.tm_year, tm.tm_mon, tm.tm_mday,
			(tm.tm_wday<0 || tm.tm_wday>6) ?
				"unknown " : RELOC(weekdays[tm.tm_wday]),
			tm.tm_hour, tm.tm_min, tm.tm_sec);

		break;
	default:
		rcode = CMD_RET_USAGE;
	}

	/* switch back to original I2C bus */
#ifdef CONFIG_SYS_I2C
	i2c_set_bus_num(old_bus);
#elif !defined(CONFIG_DM_RTC)
	I2C_SET_BUS(old_bus);
#endif

	return rcode ? CMD_RET_FAILURE : 0;
}
コード例 #9
0
static int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	int i;
	int ret;
	int cur_config_nr = -1;
	u8 cur_config[CONFIG_4xx_CONFIG_BLOCKSIZE];

	/*
	 * First switch to correct I2C bus. This is I2C bus 0
	 * for all currently available 4xx derivats.
	 */
	I2C_SET_BUS(0);

#ifdef CONFIG_CMD_EEPROM
	ret = eeprom_read(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
			  CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET,
			  cur_config, CONFIG_4xx_CONFIG_BLOCKSIZE);
#else
	ret = i2c_read(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
		       CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET,
		       1, cur_config, CONFIG_4xx_CONFIG_BLOCKSIZE);
#endif
	if (ret) {
		printf("Error reading EEPROM at addr 0x%x\n",
		       CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR);
		return -1;
	}

	/*
	 * Search the current configuration
	 */
	for (i = 0; i < ppc4xx_config_count; i++) {
		if (memcmp(cur_config, ppc4xx_config_val[i].val,
			   CONFIG_4xx_CONFIG_BLOCKSIZE) == 0)
			cur_config_nr = i;
	}

	if (cur_config_nr == -1) {
		printf("Warning: The I2C bootstrap values don't match any"
		       " of the available options!\n");
		printf("I2C bootstrap EEPROM values are (I2C address 0x%02x):\n",
			CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR);
		for (i = 0; i < CONFIG_4xx_CONFIG_BLOCKSIZE; i++) {
			printf("%02x ", cur_config[i]);
		}
		printf("\n");
	}

	if (argc < 2) {
		printf("Available configurations (I2C address 0x%02x):\n",
		       CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR);
		print_configs(cur_config_nr);
		return 0;
	}

	for (i = 0; i < ppc4xx_config_count; i++) {
		/*
		 * Search for configuration name/label
		 */
		if (strcmp(argv[1], ppc4xx_config_val[i].label) == 0) {
			printf("Using configuration:\n%-16s - %s\n",
			       ppc4xx_config_val[i].label,
			       ppc4xx_config_val[i].description);

#ifdef CONFIG_CMD_EEPROM
			ret = eeprom_write(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
					   CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET,
					   ppc4xx_config_val[i].val,
					   CONFIG_4xx_CONFIG_BLOCKSIZE);
#else
			ret = i2c_write(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
					CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET,
					1, ppc4xx_config_val[i].val,
					CONFIG_4xx_CONFIG_BLOCKSIZE);
#endif
			udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
			if (ret) {
				printf("Error updating EEPROM at addr 0x%x\n",
				       CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR);
				return -1;
			}

			printf("done (dump via 'i2c md %x 0.1 %x')\n",
			       CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR,
			       CONFIG_4xx_CONFIG_BLOCKSIZE);
			printf("Reset the board for the changes to"
			       " take effect\n");
			return 0;
		}
	}

	printf("Configuration %s not found!\n", argv[1]);
	print_configs(cur_config_nr);
	return -1;
}