void Audio_Init(uint32_t samplefreq)
{
I2S_MODEConf_Type I2S_ClkConfig;
I2S_CFG_Type I2S_ConfigStruct;
Audio_Reset_Data_Buffer();
NVIC_DisableIRQ(I2SIRQ);
switch(samplefreq){
case 11025:
case 22050:
case 44100:
audio_buffer_size = 1764;
break;
case 8000:
case 16000:
case 32000:
case 48000:
default:
audio_buffer_size = samplefreq * 4 * AUDIO_MAX_PC / 1000;
break;
}
/* Reset UDA1380 on board Hitex */
// scu_pinmux(8,2,MD_PUP, FUNC0);
// GPIO_SetDir(4, 1<<2, 1);
// GPIO_ClearValue(4, 1<<2);
/* Initialize I2S peripheral ------------------------------------*/
/* Init I2C */
I2C_Init(LPC_I2C, 100000);
/* Enable Slave I2C operation */
I2C_Cmd(LPC_I2C, ENABLE);
/* Init UDA1380 CODEC */
UDA1380_init();
/* Initialize I2S peripheral ------------------------------------*/
scu_pinmux(6,0, MD_PUP, 4); // I2S_RX_SCK
scu_pinmux(6,1, MD_PUP, 3); // I2S_RX_WS
scu_pinmux(6,2, MD_PUP, 3); // I2S_RX_SDA
scu_pinmux(3,0, MD_PUP, 2); // I2S_TX_SCK
scu_pinmux(3,1, MD_PUP, 0); // I2S_TX_WS
scu_pinmux(3,2, MD_PUP, 0); // I2S_TX_SDA
I2S_Init(I2S);
/* setup:
* - wordwidth: 16 bits
* - stereo mode
* - master mode for I2S_TX
* - Frequency = 44.1 kHz
*/
/* Audio Config*/
I2S_ConfigStruct.wordwidth = I2S_WORDWIDTH_16;
I2S_ConfigStruct.mono = I2S_STEREO;
I2S_ConfigStruct.stop = I2S_STOP_ENABLE;
I2S_ConfigStruct.reset = I2S_RESET_ENABLE;
I2S_ConfigStruct.ws_sel = I2S_MASTER_MODE;
I2S_ConfigStruct.mute = I2S_MUTE_DISABLE;
I2S_Config(I2S,I2S_TX_MODE,&I2S_ConfigStruct);
/* Clock Mode Config*/
I2S_ClkConfig.clksel = I2S_CLKSEL_FRDCLK;
I2S_ClkConfig.fpin = I2S_4PIN_DISABLE;
I2S_ClkConfig.mcena = I2S_MCLK_DISABLE;
I2S_ModeConfig(I2S,&I2S_ClkConfig,I2S_TX_MODE);
I2S_FreqConfig(I2S, samplefreq, I2S_TX_MODE);
I2S_Stop(I2S, I2S_TX_MODE);
/* TX FIFO depth is 4 */
I2S_IRQConfig(I2S,I2S_TX_MODE,I2S_TX_LEVEL);
I2S_IRQCmd(I2S,I2S_TX_MODE,ENABLE);
I2S_Start(I2S);
NVIC_EnableIRQ(I2SIRQ);
}
/*********************************************************************//**
* @brief c_entry: Main program body
* @param[in] None
* @return int
**********************************************************************/
int c_entry (void) { /* Main Program */
I2S_MODEConf_Type I2S_ClkConfig;
I2S_CFG_Type I2S_ConfigStruct;
PINSEL_CFG_Type PinCfg;
uint32_t i;
/* Initialize debug via UART0
* – 115200bps
* – 8 data bit
* – No parity
* – 1 stop bit
* – No flow control
*/
debug_frmwrk_init();
//print menu screen
print_menu();
/* Initialize I2S peripheral ------------------------------------*/
/* Pin configuration:
* Assign: - P0.4 as I2SRX_CLK
* - P0.5 as I2SRX_WS
* - P0.6 as I2SRX_SDA
* - P0.7 as I2STX_CLK
* - P0.8 as I2STX_WS
* - P0.9 as I2STX_SDA
*/
PinCfg.Funcnum = 1;
PinCfg.OpenDrain = 0;
PinCfg.Pinmode = 0;
PinCfg.Pinnum = 4;
PinCfg.Portnum = 0;
PINSEL_ConfigPin(&PinCfg);
PinCfg.Pinnum = 5;
PINSEL_ConfigPin(&PinCfg);
PinCfg.Pinnum = 6;
PINSEL_ConfigPin(&PinCfg);
PinCfg.Pinnum = 7;
PINSEL_ConfigPin(&PinCfg);
PinCfg.Pinnum = 8;
PINSEL_ConfigPin(&PinCfg);
PinCfg.Pinnum = 9;
PINSEL_ConfigPin(&PinCfg);
Buffer_Init();
I2S_Init(LPC_I2S);
/* setup:
* - wordwidth: 16 bits
* - stereo mode
* - master mode for I2S_TX and slave for I2S_RX
* - ws_halfperiod is 31
* - not use mute mode
* - use reset and stop mode
* - select the fractional rate divider clock output as the source,
* - disable 4-pin mode
* - MCLK ouput is disable
* - Frequency = 44.1 kHz
* Because we use mode I2STXMODE[3:0]= 0000, I2SDAO[5]=0 and
* I2SRX[3:0]=0000, I2SDAI[5] = 1. So we have I2SRX_CLK = I2STX_CLK
* --> I2SRXBITRATE = 1 (not divide TXCLK to produce RXCLK)
*/
/* Audio Config*/
I2S_ConfigStruct.wordwidth = I2S_WORDWIDTH_16;
I2S_ConfigStruct.mono = I2S_STEREO;
I2S_ConfigStruct.stop = I2S_STOP_ENABLE;
I2S_ConfigStruct.reset = I2S_RESET_ENABLE;
I2S_ConfigStruct.ws_sel = I2S_MASTER_MODE;
I2S_ConfigStruct.mute = I2S_MUTE_DISABLE;
I2S_Config(LPC_I2S,I2S_TX_MODE,&I2S_ConfigStruct);
I2S_ConfigStruct.ws_sel = I2S_SLAVE_MODE;
I2S_Config(LPC_I2S,I2S_RX_MODE,&I2S_ConfigStruct);
/* Clock Mode Config*/
I2S_ClkConfig.clksel = I2S_CLKSEL_FRDCLK;
I2S_ClkConfig.fpin = I2S_4PIN_DISABLE;
I2S_ClkConfig.mcena = I2S_MCLK_DISABLE;
I2S_ModeConfig(LPC_I2S,&I2S_ClkConfig,I2S_TX_MODE);
I2S_ModeConfig(LPC_I2S,&I2S_ClkConfig,I2S_RX_MODE);
I2S_FreqConfig(LPC_I2S, 44100, I2S_TX_MODE);
I2S_SetBitRate(LPC_I2S, 0, I2S_RX_MODE);
I2S_Stop(LPC_I2S, I2S_TX_MODE);
I2S_Stop(LPC_I2S, I2S_RX_MODE);
NVIC_EnableIRQ(I2S_IRQn);
/* RX FIFO depth is 1, TX FIFO depth is 8. */
I2S_IRQConfig(LPC_I2S,I2S_TX_MODE,8);
I2S_IRQConfig(LPC_I2S,I2S_RX_MODE,1);
I2S_IRQCmd(LPC_I2S,I2S_RX_MODE,ENABLE);
I2S_Start(LPC_I2S);
/* I2S transmit ---------------------------------------------------*/
while ( I2SWriteLength < BUFFER_SIZE )
{
while(I2S_GetLevel(LPC_I2S, I2S_TX_MODE)==TXFIFO_FULL);
I2S_Send(LPC_I2S, I2STXBuffer[I2SWriteLength++]);
}
I2STXDone = 1;
/* Wait for transmit/receive complete */
while ( !I2SRXDone || !I2STXDone );
for(i=0;i<BUFFER_SIZE;i++)
{
_DBH32(I2SRXBuffer[i]);_DBG_("");
}
/* Verify RX and TX Buffer */
if(Buffer_Verify())
{
_DBG_("Verify Buffer: OK...");
}
else
{
_DBG_("Verify Buffer: ERROR...");
}
return 0;
}