/* * Description: AIROHA IFRF chip init function * * Parameters: * In: * dwIoBase - I/O base address * Out: * none * * Return Value: TRUE if succeeded; FALSE if failed. * */ BOOL RFbAL2230Init (DWORD_PTR dwIoBase) { int ii; BOOL bResult; bResult = TRUE; //3-wire control for normal mode VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0); MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | SOFTPWRCTL_TXPEINV)); //2008-8-21 chester <add> // PLL Off MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); //patch abnormal AL2230 frequency output //2008-8-21 chester <add> IFRFbWriteEmbeded(dwIoBase, (0x07168700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++) bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL2230InitTable[ii]); //2008-8-21 chester <add> MACvTimer0MicroSDelay(dwIoBase, 30); //delay 30 us // PLL On MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); MACvTimer0MicroSDelay(dwIoBase, 150);//150us bResult &= IFRFbWriteEmbeded(dwIoBase, (0x00d80f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); MACvTimer0MicroSDelay(dwIoBase, 30);//30us bResult &= IFRFbWriteEmbeded(dwIoBase, (0x00780f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); MACvTimer0MicroSDelay(dwIoBase, 30);//30us bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]); MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | SOFTPWRCTL_SWPE2 | SOFTPWRCTL_SWPECTI | SOFTPWRCTL_TXPEINV)); //3-wire control for power saving mode VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000 return bResult; }
BOOL RFbAL2230SelectChannel (DWORD_PTR dwIoBase, BYTE byChannel) { BOOL bResult; bResult = TRUE; bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL2230ChannelTable0[byChannel-1]); bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL2230ChannelTable1[byChannel-1]); // Set Channel[7] = 0 to tell H/W channel is changing now. VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F)); MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL2230); // Set Channel[7] = 1 to tell H/W channel change is done. VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80)); return bResult; }
bool RFbAL2230SelectChannel (unsigned long dwIoBase, unsigned char byChannel) { bool bResult; bResult = true; bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL2230ChannelTable0[byChannel-1]); bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL2230ChannelTable1[byChannel-1]); // Set Channel[7] = 0 to tell H/W channel is changing now. VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F)); MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL2230); // Set Channel[7] = 1 to tell H/W channel change is done. VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80)); return bResult; }
BOOL RFbRawSetPower ( IN PSDevice pDevice, IN BYTE byPwr, IN UINT uRATE ) { BOOL bResult = TRUE; DWORD dwMax7230Pwr = 0; if (byPwr >= pDevice->byMaxPwrLevel) { return (FALSE); } switch (pDevice->byRFType) { case RF_AIROHA : bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]); if (uRATE <= RATE_11M) { bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); } else { bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); } break; case RF_AL2230S : bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]); if (uRATE <= RATE_11M) { bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); }else { bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); } break; case RF_AIROHA7230: // 0x080F1B00 for 3 wire control TxGain(D10) and 0x31 as TX Gain value dwMax7230Pwr = 0x080C0B00 | ( (byPwr) << 12 ) | (BY_AL7230_REG_LEN << 3 ) | IFREGCTL_REGW; bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, dwMax7230Pwr); break; default : break; } return bResult; }
bool RFbRawSetPower ( PSDevice pDevice, unsigned char byPwr, unsigned int uRATE ) { bool bResult = true; unsigned long dwMax7230Pwr = 0; if (byPwr >= pDevice->byMaxPwrLevel) { return (false); } switch (pDevice->byRFType) { case RF_AIROHA : bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]); if (uRATE <= RATE_11M) { bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); } else { bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); } break; case RF_AL2230S : bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]); if (uRATE <= RATE_11M) { bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); } else { bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); } break; case RF_AIROHA7230: // 0x080F1B00 for 3 wire control TxGain(D10) and 0x31 as TX Gain value dwMax7230Pwr = 0x080C0B00 | ( (byPwr) << 12 ) | (BY_AL7230_REG_LEN << 3 ) | IFREGCTL_REGW; bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, dwMax7230Pwr); break; default : break; } return bResult; }
/* * Description: AIROHA IFRF chip init function * * Parameters: * In: * dwIoBase - I/O base address * Out: * none * * Return Value: TRUE if succeeded; FALSE if failed. * */ BOOL s_bAL7230Init (DWORD_PTR dwIoBase) { int ii; BOOL bResult; bResult = TRUE; //3-wire control for normal mode VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0); MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | SOFTPWRCTL_TXPEINV)); BBvPowerSaveModeOFF(dwIoBase); //RobertYu:20050106, have DC value for Calibration for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[ii]); // PLL On MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); //Calibration MACvTimer0MicroSDelay(dwIoBase, 150);//150us bResult &= IFRFbWriteEmbeded(dwIoBase, (0x9ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:active, RCK:diable MACvTimer0MicroSDelay(dwIoBase, 30);//30us bResult &= IFRFbWriteEmbeded(dwIoBase, (0x3ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:diable, RCK:active MACvTimer0MicroSDelay(dwIoBase, 30);//30us bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]); //TXDCOC:diable, RCK:diable MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | SOFTPWRCTL_SWPE2 | SOFTPWRCTL_SWPECTI | SOFTPWRCTL_TXPEINV)); BBvPowerSaveModeON(dwIoBase); // RobertYu:20050106 // PE1: TX_ON, PE2: RX_ON, PE3: PLLON //3-wire control for power saving mode VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000 return bResult; }
// Need to Pull PLLON low when writing channel registers through 3-wire interface BOOL s_bAL7230SelectChannel (DWORD_PTR dwIoBase, BYTE byChannel) { BOOL bResult; bResult = TRUE; // PLLON Off MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL7230ChannelTable0[byChannel-1]); //Reg0 bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL7230ChannelTable1[byChannel-1]); //Reg1 bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL7230ChannelTable2[byChannel-1]); //Reg4 // PLLOn On MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); // Set Channel[7] = 0 to tell H/W channel is changing now. VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F)); MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL7230); // Set Channel[7] = 1 to tell H/W channel change is done. VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80)); return bResult; }
/* * Description: RF ShutDown function * * Parameters: * In: * byBBType * byRFType * Out: * none * * Return Value: TRUE if succeeded; FALSE if failed. * */ BOOL RFbShutDown ( IN PSDevice pDevice ) { BOOL bResult = TRUE; switch (pDevice->byRFType) { case RF_AIROHA7230 : bResult = IFRFbWriteEmbeded (pDevice->PortOffset, 0x1ABAEF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW); break; default : bResult = TRUE; break; } return bResult; }
// Post processing for the 11b/g and 11a. // for save time on changing Reg2,3,5,7,10,12,15 bool RFbAL7230SelectChannelPostProcess (unsigned long dwIoBase, unsigned char byOldChannel, unsigned char byNewChannel) { bool bResult; bResult = true; // if change between 11 b/g and 11a need to update the following register // Channel Index 1~14 if( (byOldChannel <= CB_MAX_CHANNEL_24G) && (byNewChannel > CB_MAX_CHANNEL_24G) ) { // Change from 2.4G to 5G bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[2]); //Reg2 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[3]); //Reg3 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[5]); //Reg5 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[7]); //Reg7 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[10]);//Reg10 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[12]);//Reg12 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[15]);//Reg15 } else if( (byOldChannel > CB_MAX_CHANNEL_24G) && (byNewChannel <= CB_MAX_CHANNEL_24G) ) { // change from 5G to 2.4G bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[2]); //Reg2 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[3]); //Reg3 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[5]); //Reg5 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[7]); //Reg7 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[10]);//Reg10 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[12]);//Reg12 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[15]);//Reg15 } return bResult; }
BOOL RFbRawSetPower ( PSDevice pDevice, BYTE byPwr, unsigned int uRATE ) { BOOL bResult = TRUE; if (pDevice->byCurPwr == byPwr) return TRUE; pDevice->byCurPwr = byPwr; switch (pDevice->byRFType) { case RF_AL2230 : if (pDevice->byCurPwr >= AL2230_PWR_IDX_LEN) return FALSE; bResult &= IFRFbWriteEmbeded(pDevice, dwAL2230PowerTable[pDevice->byCurPwr]); if (uRATE <= RATE_11M) bResult &= IFRFbWriteEmbeded(pDevice, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); else bResult &= IFRFbWriteEmbeded(pDevice, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); break; case RF_AL2230S : if (pDevice->byCurPwr >= AL2230_PWR_IDX_LEN) return FALSE; bResult &= IFRFbWriteEmbeded(pDevice, dwAL2230PowerTable[pDevice->byCurPwr]); if (uRATE <= RATE_11M) { bResult &= IFRFbWriteEmbeded(pDevice, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); bResult &= IFRFbWriteEmbeded(pDevice, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); }else { bResult &= IFRFbWriteEmbeded(pDevice, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); bResult &= IFRFbWriteEmbeded(pDevice, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); } break; case RF_AIROHA7230: { DWORD dwMax7230Pwr; if (uRATE <= RATE_11M) { bResult &= IFRFbWriteEmbeded(pDevice, 0x111BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW); } else { bResult &= IFRFbWriteEmbeded(pDevice, 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW); } if (pDevice->byCurPwr > AL7230_PWR_IDX_LEN) return FALSE; dwMax7230Pwr = 0x080C0B00 | ( (pDevice->byCurPwr) << 12 ) | (BY_AL7230_REG_LEN << 3 ) | IFREGCTL_REGW; bResult &= IFRFbWriteEmbeded(pDevice, dwMax7230Pwr); break; } break; case RF_VT3226: { DWORD dwVT3226Pwr; if (pDevice->byCurPwr >= VT3226_PWR_IDX_LEN) return FALSE; dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x17 << 8 ) | (BY_VT3226_REG_LEN << 3 ) | IFREGCTL_REGW; bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226Pwr); break; } case RF_VT3226D0: { DWORD dwVT3226Pwr; if (pDevice->byCurPwr >= VT3226_PWR_IDX_LEN) return FALSE; if (uRATE <= RATE_11M) { dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0xE07 << 8 ) | (BY_VT3226_REG_LEN << 3 ) | IFREGCTL_REGW; bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226Pwr); bResult &= IFRFbWriteEmbeded(pDevice, 0x03C6A200+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); if (pDevice->sMgmtObj.eScanState != WMAC_NO_SCANNING) { DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"@@@@ RFbRawSetPower> 11B mode uCurrChannel[%d]\n", pDevice->sMgmtObj.uScanChannel); bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226D0LoCurrentTable[pDevice->sMgmtObj.uScanChannel-1]); } else { DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"@@@@ RFbRawSetPower> 11B mode uCurrChannel[%d]\n", pDevice->sMgmtObj.uCurrChannel); bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226D0LoCurrentTable[pDevice->sMgmtObj.uCurrChannel-1]); } bResult &= IFRFbWriteEmbeded(pDevice, 0x015C0800+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); } else { DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"@@@@ RFbRawSetPower> 11G mode\n"); dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x7 << 8 ) | (BY_VT3226_REG_LEN << 3 ) | IFREGCTL_REGW; bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226Pwr); bResult &= IFRFbWriteEmbeded(pDevice, 0x00C6A200+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); bResult &= IFRFbWriteEmbeded(pDevice, 0x016BC600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); bResult &= IFRFbWriteEmbeded(pDevice, 0x00900800+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); } break; } case RF_VT3342A0: { DWORD dwVT3342Pwr; if (pDevice->byCurPwr >= VT3342_PWR_IDX_LEN) return FALSE; dwVT3342Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x27 << 8 ) | (BY_VT3342_REG_LEN << 3 ) | IFREGCTL_REGW; bResult &= IFRFbWriteEmbeded(pDevice, dwVT3342Pwr); break; } default : break; } return bResult; }
/* * Description: Set Tx power * * Parameters: * In: * dwIoBase - I/O base address * dwRFPowerTable - RF Tx Power Setting * Out: * none * * Return Value: TRUE if succeeded; FALSE if failed. * */ BOOL RFbRawSetPower ( IN PSDevice pDevice, IN BYTE byPwr, IN UINT uRATE ) { BOOL bResult = TRUE; if (pDevice->byCurPwr == byPwr) return TRUE; pDevice->byCurPwr = byPwr; switch (pDevice->byRFType) { case RF_AL2230 : if (pDevice->byCurPwr >= AL2230_PWR_IDX_LEN) return FALSE; bResult &= IFRFbWriteEmbeded(pDevice, dwAL2230PowerTable[pDevice->byCurPwr]); if (uRATE <= RATE_11M) bResult &= IFRFbWriteEmbeded(pDevice, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); else bResult &= IFRFbWriteEmbeded(pDevice, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); break; case RF_AL2230S : if (pDevice->byCurPwr >= AL2230_PWR_IDX_LEN) return FALSE; bResult &= IFRFbWriteEmbeded(pDevice, dwAL2230PowerTable[pDevice->byCurPwr]); if (uRATE <= RATE_11M) { bResult &= IFRFbWriteEmbeded(pDevice, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); bResult &= IFRFbWriteEmbeded(pDevice, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); }else { bResult &= IFRFbWriteEmbeded(pDevice, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); bResult &= IFRFbWriteEmbeded(pDevice, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); } break; case RF_AIROHA7230: { DWORD dwMax7230Pwr; if (uRATE <= RATE_11M) { //RobertYu:20060426, for better 11b mask bResult &= IFRFbWriteEmbeded(pDevice, 0x111BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW); } else { bResult &= IFRFbWriteEmbeded(pDevice, 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW); } if (pDevice->byCurPwr > AL7230_PWR_IDX_LEN) return FALSE; // 0x080F1B00 for 3 wire control TxGain(D10) and 0x31 as TX Gain value dwMax7230Pwr = 0x080C0B00 | ( (pDevice->byCurPwr) << 12 ) | (BY_AL7230_REG_LEN << 3 ) | IFREGCTL_REGW; bResult &= IFRFbWriteEmbeded(pDevice, dwMax7230Pwr); break; } break; case RF_VT3226: //RobertYu:20051111, VT3226C0 and before { DWORD dwVT3226Pwr; if (pDevice->byCurPwr >= VT3226_PWR_IDX_LEN) return FALSE; dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x17 << 8 ) /* Reg7 */ | (BY_VT3226_REG_LEN << 3 ) | IFREGCTL_REGW; bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226Pwr); break; } case RF_VT3226D0: //RobertYu:20051228 { DWORD dwVT3226Pwr; if (pDevice->byCurPwr >= VT3226_PWR_IDX_LEN) return FALSE; if (uRATE <= RATE_11M) { dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0xE07 << 8 ) /* Reg7 */ | //RobertYu:20060420, TWIF 1.10 (BY_VT3226_REG_LEN << 3 ) | IFREGCTL_REGW; bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226Pwr); bResult &= IFRFbWriteEmbeded(pDevice, 0x03C6A200+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); if (pDevice->sMgmtObj.eScanState != WMAC_NO_SCANNING) { // scanning, the channel number is pDevice->uScanChannel DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"@@@@ RFbRawSetPower> 11B mode uCurrChannel[%d]\n", pDevice->sMgmtObj.uScanChannel); bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226D0LoCurrentTable[pDevice->sMgmtObj.uScanChannel-1]); //RobertYu:20060420, sometimes didn't change channel just set power with different rate } else { DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"@@@@ RFbRawSetPower> 11B mode uCurrChannel[%d]\n", pDevice->sMgmtObj.uCurrChannel); bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226D0LoCurrentTable[pDevice->sMgmtObj.uCurrChannel-1]); //RobertYu:20060420, sometimes didn't change channel just set power with different rate } bResult &= IFRFbWriteEmbeded(pDevice, 0x015C0800+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060420, ok now, new switching power (mini-pci can have bigger power consumption) } else { DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"@@@@ RFbRawSetPower> 11G mode\n"); dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x7 << 8 ) /* Reg7 */ | //RobertYu:20060420, TWIF 1.10 (BY_VT3226_REG_LEN << 3 ) | IFREGCTL_REGW; bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226Pwr); bResult &= IFRFbWriteEmbeded(pDevice, 0x00C6A200+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060327 bResult &= IFRFbWriteEmbeded(pDevice, 0x016BC600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060111 bResult &= IFRFbWriteEmbeded(pDevice, 0x00900800+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060111 } break; } //{{RobertYu:20060609 case RF_VT3342A0: { DWORD dwVT3342Pwr; if (pDevice->byCurPwr >= VT3342_PWR_IDX_LEN) return FALSE; dwVT3342Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x27 << 8 ) /* Reg7 */ | (BY_VT3342_REG_LEN << 3 ) | IFREGCTL_REGW; bResult &= IFRFbWriteEmbeded(pDevice, dwVT3342Pwr); break; } default : break; } return bResult; }