static void ov5640_mipi_camera_io_init(void)
{
IOMUX_SETUP(mipi_pads);
pr_info("%s\n", __func__);
mipi_pwm = pwm_request(2, "mipi_clock");
if (IS_ERR(mipi_pwm)) {
pr_err("unable to request PWM for mipi_clock\n");
} else {
unsigned period = 1000/22;
pr_info("got pwm for mipi_clock\n");
pwm_config(mipi_pwm, period >> 1, period);
pwm_enable(mipi_pwm);
}
camera_reset(IMX_GPIO_NR(6, 9), 1, IMX_GPIO_NR(2, 5), IMX_GPIO_NR(6, 11));
/* for mx6dl, mipi virtual channel 1 connect to csi 1*/
if (cpu_is_mx6dl())
mxc_iomux_set_gpr_register(13, 3, 3, 1);
}
static void wand_suspend_exit(void) {
gpio_direction_output(IMX_GPIO_NR(2, 8), 1);
gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
gpio_direction_output(WAND_WL_RST_N, 1);
if (wand_revision == WAND_REV_C1) {
gpio_set_value(WAND_BT_WAKE_C1, 1);
gpio_direction_output(WAND_WL_REF_ON_C1, 1);
} else {
gpio_direction_output(WAND_WL_REF_ON_AB, 1);
gpio_set_value(WAND_BT_WAKE_AB, 1);
}
gpio_direction_output(WAND_WL_REG_ON, 1);
gpio_set_value(WAND_WL_WAKE, 1);
gpio_set_value(WAND_USB_HOST_PWR_EN, 1);
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
gpio_direction_input(IMX_GPIO_NR(1, 4));
ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
break;
case USDHC4_BASE_ADDR:
gpio_direction_input(IMX_GPIO_NR(2, 6));
ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
break;
default:
printf("Bad USDHC interface\n");
}
return ret;
}
static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
int ret;
ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
if (ret)
printk(KERN_ERR
"pca100: Failed to request irq for sd/mmc detection\n");
return ret;
}
int board_ehci_hcd_init(int port)
{
if (port == 0) {
/* USB OTG PWRON */
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
/* USB OTG Over Current */
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
} else if (port == 1) {
/* USB Host PWRON */
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
/* USB Host Over Current */
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
}
return 0;
}
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg;
enable_ipu_clock();
imx_setup_hdmi();
/* Turn on LDB0,IPU,IPU DI0 clocks */
reg = __raw_readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
writel(reg, &mxc_ccm->CCGR3);
/* set LDB0, LDB1 clk select to 011/011 */
reg = readl(&mxc_ccm->cs2cdr);
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
|MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
|(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->cs2cdr);
reg = readl(&mxc_ccm->cscmr2);
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
writel(reg, &mxc_ccm->cscmr2);
reg = readl(&mxc_ccm->chsccdr);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
|IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
|IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
|IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
|IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
|IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
|IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
|IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
|IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
writel(reg, &iomux->gpr[2]);
reg = readl(&iomux->gpr[3]);
reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
writel(reg, &iomux->gpr[3]);
/* LVDS Backlight GPIO on LVDS connector - output low */
SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
}
int board_early_init_f(void)
{
setup_iomux_uart();
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
ARRAY_SIZE(peri_3v3_pads));
/* Active high for ncp692 */
gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
return 0;
}
static void __init mx27pdk_init(void)
{
int ret;
imx27_soc_init();
mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
"mx27pdk");
mx27_3ds_sdhc1_enable_level_translator();
imx27_add_imx_uart0(&uart_pdata);
imx27_add_fec(NULL);
imx27_add_imx_keypad(&mx27_3ds_keymap_data);
imx27_add_mxc_mmc(0, &sdhc1_pdata);
imx27_add_imx2_wdt();
otg_phy_init();
if (otg_mode_host) {
otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
ULPI_OTG_DRVVBUS_EXT);
if (otg_pdata.otg)
imx27_add_mxc_ehci_otg(&otg_pdata);
}
if (!otg_mode_host)
imx27_add_fsl_usb2_udc(&otg_device_pdata);
imx27_add_spi_imx1(&spi2_pdata);
imx27_add_spi_imx0(&spi1_pdata);
mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT);
spi_register_board_info(mx27_3ds_spi_devs,
ARRAY_SIZE(mx27_3ds_spi_devs));
if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28)))
pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
platform_add_devices(devices, ARRAY_SIZE(devices));
imx27_add_imx_fb(&mx27_3ds_fb_data);
ret = gpio_request_array(mx27_3ds_camera_gpios,
ARRAY_SIZE(mx27_3ds_camera_gpios));
if (ret) {
pr_err("Failed to request camera gpios");
iclink_ov2640.power = NULL;
}
imx27_add_mx2_camera(&mx27_3ds_cam_pdata);
imx27_add_imx_ssi(0, &mx27_3ds_ssi_pdata);
imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
}
int board_recovery_init_f(void)
{
gpio_direction_input(IMX_GPIO_NR(3, 16));
if (!gpio_get_value(IMX_GPIO_NR(3, 16))) {
puts("RECOVERY SWITCH PRESSED\n");
puts("trying to assume sensible defaults\n");
setenv("bootdelay", "30");
setenv("recovery", "1");
/* these have to be set before setup_display() */
setenv("hdmi_xres", "640");
setenv("hdmi_yres", "480");
setenv("hdmi_refresh", "60");
/* prevent a misconfigured preboot from breaking recovery */
setenv("preboot", "usb start");
} else {
setenv("recovery", "0");
}
return 0;
}
void do_enable_lvds(struct lcd_panel_info_t const *dev)
{
enable_lcdif_clock(dev->lcdif_base_addr);
enable_lvds(dev->lcdif_base_addr);
imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads,
ARRAY_SIZE(lvds_ctrl_pads));
#ifdef CONFIG_MAX7310_IOEXP
/* LVDS Enable pin */
gpio_exp_direction_output(LVDS_EN_PIN , 1);
#endif
/* Set Brightness to high */
gpio_direction_output(IMX_GPIO_NR(6, 3) , 1);
}
static void __init pcm038_init(void)
{
imx27_soc_init();
mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
"PCM038");
pcm038_init_sram();
imx27_add_imx_uart0(&uart_pdata);
imx27_add_imx_uart1(&uart_pdata);
imx27_add_imx_uart2(&uart_pdata);
mxc_gpio_mode(PE16_AF_OWIRE);
imx27_add_mxc_nand(&pcm038_nand_board_info);
/* only the i2c master 1 is used on this CPU card */
i2c_register_board_info(1, pcm038_i2c_devices,
ARRAY_SIZE(pcm038_i2c_devices));
imx27_add_imx_i2c(1, &pcm038_i2c1_data);
/* PE18 for user-LED D40 */
mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
/* MC13783 IRQ */
mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
imx27_add_spi_imx0(&pcm038_spi0_data);
pcm038_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(2, 23));
spi_register_board_info(pcm038_spi_board_info,
ARRAY_SIZE(pcm038_spi_board_info));
imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_imx2_wdt();
imx27_add_mxc_w1();
#ifdef CONFIG_MACH_PCM970_BASEBOARD
pcm970_baseboard_init();
#endif
}
/*
* Board specific initialization.
*/
static void __init mx35_3ds_init(void)
{
struct platform_device *imx35_fb_pdev;
imx35_soc_init();
mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
imx35_add_fec(NULL);
imx35_add_imx2_wdt();
imx35_add_mxc_rtc();
platform_add_devices(devices, ARRAY_SIZE(devices));
imx35_add_imx_uart0(&uart_pdata);
if (otg_mode_host)
imx35_add_mxc_ehci_otg(&otg_pdata);
imx35_add_mxc_ehci_hs(&usb_host_pdata);
if (!otg_mode_host)
imx35_add_fsl_usb2_udc(&usb_otg_pdata);
imx35_add_mxc_nand(&mx35pdk_nand_board_info);
imx35_add_sdhci_esdhc_imx(0, NULL);
if (mxc_expio_init(MX35_CS5_BASE_ADDR, IMX_GPIO_NR(1, 1)))
pr_warn("Init of the debugboard failed, all "
"devices on the debugboard are unusable.\n");
imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
i2c_register_board_info(
0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
imx35_add_ipu_core();
platform_device_register(&mx35_3ds_ov2640);
imx35_3ds_init_camera();
imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
platform_device_register(&mx35_3ds_lcd);
imx35_3ds_init_mc13892();
}
static inline void tx51_fec_init(void)
{
int i;
/* Configure LAN8700 pads as GPIO and set up
* necessary strap options for PHY
*/
for (i = 0; i < ARRAY_SIZE(tx51_fec_gpios); i++) {
struct tx51_fec_gpio_setup *gs = &tx51_fec_gpios[i];
gpio_direction_output(IMX_GPIO_NR(gs->group, gs->shift ), gs->level);
mxc_iomux_v3_setup_pad(gs->pad);
}
/*
*Turn on phy power, leave in reset state
*/
gpio_set_value(TX51_FEC_PHY_PWR, 1);
/*
* Wait some time to let the phy activate the internal regulator
*/
mdelay(10);
/*
* Deassert reset, phy latches the rest of bootstrap pins
*/
gpio_set_value(TX51_FEC_PHY_RST, 1);
/* LAN7800 has an internal Power On Reset (POR) signal (OR'ed with
* the external RESET signal) which is deactivated 21ms after
* power on and latches the strap options.
* Delay for 22ms to ensure, that the internal POR is inactive
* before reconfiguring the strap pins.
*/
mdelay(22);
/*
* The phy is ready, now configure imx51 pads for fec operation
*/
mxc_iomux_v3_setup_multiple_pads(tx51_fec_pads,
ARRAY_SIZE(tx51_fec_pads));
}
static int imx51_babbage_xload_init_devices(void)
{
static int spi0_chipselects[] = {
IMX_GPIO_NR(4, 25),
};
static struct spi_imx_master spi0_pdata = {
.chipselect = spi0_chipselects,
.num_chipselect = ARRAY_SIZE(spi0_chipselects),
};
static const struct spi_board_info spi0_devices[] = {
{
.name = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 25 * 1000 * 1000,
.bus_num = 0,
},
};
static void setup_spi(void)
{
#ifdef CONFIG_TARGET_ZC5202
gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0");
gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1");
gpio_direction_output(IMX_GPIO_NR(5, 17), 1);
gpio_direction_output(IMX_GPIO_NR(5, 9), 1);
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
#endif
gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0");
gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
enable_spi_clk(true, 3);
}
/*
* GPIO_6 GPIO[1]:6 (ov5642) - J5 - CSI0 power down
* GPIO_8 GPIO[1]:8 (ov5642) - J5 - CSI0 reset
* NANDF_CS0 GPIO[6]:11 (ov5642) - J5 - reset
* SD1_DAT0 GPIO[1]:16 (ov5642) - J5 - GP
*/
static void ov5642_io_init(void)
{
IOMUX_SETUP(csi0_sensor_pads);
camera_reset(GP_CSI0_PWN, 1, GP_CSI0_RST, IMX_GPIO_NR(6, 11));
/* For MX6Q GPR1 bit19 and bit20 meaning:
* Bit19: 0 - Enable mipi to IPU1 CSI0
* virtual channel is fixed to 0
* 1 - Enable parallel interface to IPU1 CSI0
* Bit20: 0 - Enable mipi to IPU2 CSI1
* virtual channel is fixed to 3
* 1 - Enable parallel interface to IPU2 CSI1
* IPU1 CSI1 directly connect to mipi csi2,
* virtual channel is fixed to 1
* IPU2 CSI0 directly connect to mipi csi2,
* virtual channel is fixed to 2
*/
if (cpu_is_mx6q())
mxc_iomux_set_gpr_register(1, 19, 1, 1);
else
mxc_iomux_set_gpr_register(13, 0, 3, 4);
}
static void novena_spl_setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
/* Assert Ethernet PHY nRST */
gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
/*
* Use imx6 internal pull-ups to drive PHY mode pins during PHY reset
* de-assertion. The intention is to use weak signal drivers (pull-ups)
* to prevent the conflict between PHY pins becoming outputs after
* reset and imx6 still driving the pins. The issue is described in PHY
* datasheet, p.14
*/
gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */
gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */
gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */
gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */
gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */
gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */
/* Following reset timing (p.53, fig.8 from the PHY datasheet) */
mdelay(10);
/* De-assert Ethernet PHY nRST */
gpio_set_value(IMX_GPIO_NR(3, 23), 1);
/* PHY is now configured, connect FEC to the pads */
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
/*
* PHY datasheet recommends on p.53 to wait at least 100us after reset
* before using MII, so we enforce the delay here
*/
udelay(100);
}
int board_mmc_init(bd_t *bis)
{
static const iomux_v3_cfg_t sd1_pads[] = {
NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
MX53_PAD_EIM_DA13__GPIO3_13,
MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
};
esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
/* GPIO 2_31 is SD power */
gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
return fsl_esdhc_initialize(bis, &esdhc_cfg);
}
PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_40ohm)
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C2 for PMIC */
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6SX_PAD_GPIO1_IO02__I2C2_SCL | PC,
.gpio_mode = MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
.gp = IMX_GPIO_NR(1, 2),
},
.sda = {
.i2c_mode = MX6SX_PAD_GPIO1_IO03__I2C2_SDA | PC,
.gpio_mode = MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
.gp = IMX_GPIO_NR(1, 3),
},
};
/* I2C3 */
struct i2c_pads_info i2c_pad_info3 = {
.scl = {
.i2c_mode = MX6SX_PAD_KEY_COL4__I2C3_SCL | PC,
.gpio_mode = MX6SX_PAD_KEY_COL4__GPIO2_IO_14 | PC,
.gp = IMX_GPIO_NR(2, 14),
},
gpio_direction_output(IOX_STCP, 0);
udelay(500);
/*
* shift register will be output to pins
*/
gpio_direction_output(IOX_STCP, 1);
};
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC and EEPROM */
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
.gp = IMX_GPIO_NR(1, 28),
},
.sda = {
.i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
.gp = IMX_GPIO_NR(1, 29),
},
};
#ifdef CONFIG_POWER
#define I2C_PMIC 0
int power_init_board(void)
{
if (is_mx6ul_9x9_evk()) {
struct pmic *pfuze;
int ret;
static __init void wand_init_external_gpios(void)
{
#if defined(CONFIG_EDM)
/* GPIO export and setup is in EDM framework, see drivers/edm/edm.c */
wand_mux_pads_init_external_gpios();
#endif
}
/****************************************************************************
*
* SPI - while not used on the Wandboard, the pins are routed to baseboard
*
****************************************************************************/
static const int wand_spi1_chipselect[] = { IMX_GPIO_NR(2, 30) };
/* platform device */
static const struct spi_imx_master wand_spi1_data = {
.chipselect = (int *)wand_spi1_chipselect,
.num_chipselect = ARRAY_SIZE(wand_spi1_chipselect),
};
/* ------------------------------------------------------------------------ */
static const int wand_spi2_chipselect[] = { IMX_GPIO_NR(2, 26), IMX_GPIO_NR(2, 27) };
static const struct spi_imx_master wand_spi2_data = {
.chipselect = (int *)wand_spi2_chipselect,
.num_chipselect = ARRAY_SIZE(wand_spi2_chipselect),
};
static void power_init(void)
{
unsigned int val;
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
struct pmic *p;
int ret;
ret = pmic_init(I2C_PMIC);
if (ret)
return;
p = pmic_get("FSL_PMIC");
if (!p)
return;
/* Write needed to Power Gate 2 register */
pmic_reg_read(p, REG_POWER_MISC, &val);
val &= ~PWGT2SPIEN;
pmic_reg_write(p, REG_POWER_MISC, val);
/* Externally powered */
pmic_reg_read(p, REG_CHARGE, &val);
val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
pmic_reg_write(p, REG_CHARGE, val);
/* power up the system first */
pmic_reg_write(p, REG_POWER_MISC, PWUP);
/* Set core voltage to 1.1V */
pmic_reg_read(p, REG_SW_0, &val);
val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
pmic_reg_write(p, REG_SW_0, val);
/* Setup VCC (SW2) to 1.075v */
pmic_reg_read(p, REG_SW_1, &val);
val = (val & ~SWx_VOLT_MASK) | SWx_1_225V;
pmic_reg_write(p, REG_SW_1, val);
/* Setup 1V2_DIG1 (SW3) to 1.05v */
pmic_reg_read(p, REG_SW_2, &val);
val = (val & ~SWx_VOLT_MASK) | SWx_1_050V;
pmic_reg_write(p, REG_SW_2, val);
udelay(50);
/* Raise the core frequency to 800MHz */
writel(0x0, &mxc_ccm->cacrr);
/* Set switchers in Auto in NORMAL mode & STANDBY mode */
/* Setup the switcher mode for SW1 & SW2*/
pmic_reg_read(p, REG_SW_4, &val);
val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
(SWMODE_MASK << SWMODE2_SHIFT)));
val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
pmic_reg_write(p, REG_SW_4, val);
/* Setup the switcher mode for SW3 & SW4 */
pmic_reg_read(p, REG_SW_5, &val);
val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
(SWMODE_MASK << SWMODE4_SHIFT)));
val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
pmic_reg_write(p, REG_SW_5, val);
/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
pmic_reg_read(p, REG_SETTING_0, &val);
val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
pmic_reg_write(p, REG_SETTING_0, val);
/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
pmic_reg_read(p, REG_SETTING_1, &val);
val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
pmic_reg_write(p, REG_SETTING_1, val);
/* Configure VGEN3 and VCAM regulators to use external PNP */
val = VGEN3CONFIG | VCAMCONFIG;
pmic_reg_write(p, REG_MODE_1, val);
udelay(200);
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
VVIDEOEN | VAUDIOEN | VSDEN;
pmic_reg_write(p, REG_MODE_1, val);
if(1){/* testing LED */
unsigned int led_setting;
unsigned int driver_current = 0x04; /* [11:9] */
unsigned int drivers_duty_cycle = 0x20; /* [8:3] */
unsigned int drivers_period_control = 0x03; /* [1:0] */
unsigned int drivers_ramp = 0; /* [3] */
led_setting = (driver_current<<9) | (drivers_duty_cycle<<3) | (drivers_ramp<<2) | (drivers_period_control);
pmic_reg_write(p, REG_LED_CTL2, (val<<11)|val);
pmic_reg_write(p, REG_LED_CTL3, val);
}
if(1){/* testing LED D7 */
int i;
u32 val;
/* 0x73fa86bc bit[2:1] set 1 */
/* IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIN DSE(Drive Strength Field) set to max strength */
val = readl(0x73fa86bc);
val |= 0x06;
writel(val, 0x73fa86bc);
/* 0x73fa82bc bit[2] set to 1 */
/* IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIN MUX_MODE set to */
/* 0x100, ALT4 mux port: GPIO[5] of instance: gpio3. */
/* DISPB2_SER_DIN to be gpio3[5] */
/* Select mux mode: ALT4 mux port: GPIO[5] of instance: gpio3. */
writel(0x04, 0x73fa82bc);
/* 0x73fa8988 bit[0] set to 1 */
/* IOMUXC_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT DAISY */
/* Selecting BGA contact: DISPB2_SER_DIN for Mode: ALT4. */
val = readl(0x73fa8988);
val |= 0x01;
writel(val, 0x73fa8988);
/* 0x73f8c000---0x73f8ffff is GPIO3 IO memory map */
/* 0x73f8c004 bit[5] set to 1 */
/* let GPIO[5] to be output direction */
/* GPIO Direction: */
/* 0 GPIO is configured as input. */
/* 1 GPIO is configured as output. */
val = readl(0x73f8c004);
val |= 0x20;
writel(val, 0x73f8c004);
/* 0x73f8c014 bit[7:0] clear */
/* diable the least 8 pin interrupt. Seems too strong! */
/* I think only GPIO[5] should be disabled */
/* GPIO Interrupt Mask Register */
/* 0 The interrupt i is disabled. */
/* 1 The interrupt i is enabled. */
val = readl(0x73f8c014);
val &= ~0x20;
writel(val, 0x73f8c014);
/* // MX51_PAD_DISPB2_SER_DIN__GPIO3_5=lcd_led_en: */
/* writel(0x04, 0x73fa82bc); */
/* writel(0x01, 0x73fa8988); */
/* writel(0x85, 0x73fa86bc); */
board_access_gpio(0x30005, 'o', 0); /* set output */
for(i=0; i<5; ++i){
printf("loop for test LED: %d\n", i);
board_access_gpio(0x30005, 'w', 1);
udelay(1000*50);
board_access_gpio(0x30005, 'w', 0);
udelay(1000*50);
}
}
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
NO_PAD_CTRL));
gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
udelay(500);
gpio_set_value(IMX_GPIO_NR(2, 14), 1);
}
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 7)) : -1;
}
void setup_spinor(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
ARRAY_SIZE(ecspi1_pads));
gpio_direction_output(IMX_GPIO_NR(4, 7), 0);
}
/* There's a device, but link not established. Retry */ } return err; } #endif #ifdef CONFIG_SYS_I2C_MXC #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) I2C_PADS(i2c0_pads, PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL), IMX_GPIO_NR(3, 21), PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL), IMX_GPIO_NR(3, 28)); I2C_PADS(i2c1_pads, PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL), IMX_GPIO_NR(4, 12), PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL), IMX_GPIO_NR(4, 13)); I2C_PADS(i2c2_pads, PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
case BOOTSOURCE_MMC:
of_device_enable_path("/chosen/environment-sd");
break;
case BOOTSOURCE_SPI:
default:
of_device_enable_path("/chosen/environment-spi");
break;
}
return 0;
}
console_initcall(efikamx_usb_init);
static struct gpio_led leds[] = {
{
.gpio = IMX_GPIO_NR(1, 3),
.active_low = 1,
.led.name = "mail",
}, {
.gpio = IMX_GPIO_NR(2, 25),
.led.name = "white",
},
};
static int efikamx_late_init(void)
{
int i;
if (!of_machine_is_compatible("genesi,imx51-sb"))
return 0;
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
.gp = IMX_GPIO_NR(4, 8),
},
.sda = {
.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
.gp = IMX_GPIO_NR(4, 9),
},
};
#endif
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
void spl_dram_init(void)
{
/* ddr init */
if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
ddr_init(&dram_timing);
else
ddr_init(&dram_timing_b0);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "usb.h"
#include "devices-imx6q.h"
#include "crm_regs.h"
#include "cpu_op-mx6.h"
#define GPIOF_HIGH GPIOF_OUT_INIT_HIGH
struct gpio board_gpios[] __initdata = {
#define GP_LVDS0_12V_5V_BL_SELECT IMX_GPIO_NR(4, 5)
{.label = "lvds0_12_5_BL", .gpio = IMX_GPIO_NR(4, 5), .flags = 0}, /* GPIO_19 */
#define GP_RGB_LVDS1_12V_5V_BL_SELECT IMX_GPIO_NR(1, 7)
{.label = "rgb_lvds1_12_5_BL", .gpio = IMX_GPIO_NR(1, 7), .flags = 0}, /* GPIO_7 */
#define GP_12V_POWER_EN IMX_GPIO_NR(4, 20)
{.label = "12V_en", .gpio = IMX_GPIO_NR(4, 20), .flags = 0}, /* DI0_PIN4 */
{.label = "gp_led", .gpio = IMX_GPIO_NR(2, 7), .flags = 0}, /* GPIO_3 */
{.label = "sata_led", .gpio = IMX_GPIO_NR(2, 17), .flags = 0}, /* EIM_A21 */
{.label = "powerfail", .gpio = IMX_GPIO_NR(1, 6), .flags = GPIOF_DIR_IN}, /* GPIO_6 */
{.label = "rgb_mirror_vertical", .gpio = IMX_GPIO_NR(2, 27), .flags = 0}, /* EIM_LBA */
{.label = "rgb_mirror_horizontal", .gpio = IMX_GPIO_NR(2, 25), .flags = GPIOF_HIGH}, /* EIM_OE */
#define GP_USB_HUB_RESET IMX_GPIO_NR(7, 12)
{.label = "usb_hub_reset", .gpio = IMX_GPIO_NR(7, 12), .flags = 0}, /* EIM_OE */
#define GP_AMP_ENABLE IMX_GPIO_NR(1, 8)
{.label = "speaker_enable", .gpio = IMX_GPIO_NR(1, 8), .flags = 0}, /* EIM_OE */
#define GP_WL_EN IMX_GPIO_NR(6, 7) /* NANDF_CLE - active high */
#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
#define WEIM_NOR_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_PUS_PU100KOHM)
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
.gp = IMX_GPIO_NR(4, 8),
},
.sda = {
.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
.gp = IMX_GPIO_NR(4, 9),
},
};
/* I2C2 */
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC,
.gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC,
.gp = IMX_GPIO_NR(4, 10),
},