/*
========================================================================
Routine Description:
Process MGMT ring DMA done interrupt, running in DPC level
Arguments:
pAd Pointer to our adapter
Return Value:
None
IRQL = DISPATCH_LEVEL
Note:
========================================================================
*/
VOID RTMPHandleMgmtRingDmaDoneInterrupt(
IN PRTMP_ADAPTER pAd)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PNDIS_PACKET pPacket;
// int i;
UCHAR FREE = 0;
PRTMP_MGMT_RING pMgmtRing = &pAd->MgmtRing;
NdisAcquireSpinLock(&pAd->MgmtRingLock);
RTMP_IO_READ32(pAd, TX_MGMTDTX_IDX, &pMgmtRing->TxDmaIdx);
while (pMgmtRing->TxSwFreeIdx!= pMgmtRing->TxDmaIdx)
{
FREE++;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
#endif
pTxD->DMADONE = 0;
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket;
if (pPacket == NULL)
continue;
if (pPacket)
{
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket = NULL;
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket;
if (pPacket)
{
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket = NULL;
INC_RING_INDEX(pMgmtRing->TxSwFreeIdx, MGMT_RING_SIZE);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, TRUE, TYPE_TXD);
#endif
}
NdisReleaseSpinLock(&pAd->MgmtRingLock);
#ifdef CONFIG_STA_SUPPORT
#endif // CONFIG_STA_SUPPORT //
}
u16 RtmpPCI_WriteSingleTxResource(struct rt_rtmp_adapter *pAd,
struct rt_tx_blk *pTxBlk,
IN BOOLEAN bIsLast,
u16 * FreeNumber)
{
u8 *pDMAHeaderBufVA;
u16 TxIdx, RetTxIdx;
struct rt_txd * pTxD;
u32 BufBasePaLow;
struct rt_rtmp_tx_ring *pTxRing;
u16 hwHeaderLen;
/* */
/* get Tx Ring Resource */
/* */
pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
pDMAHeaderBufVA = (u8 *)pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
BufBasePaLow =
RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
/* copy TXINFO + TXWI + WLAN Header + LLC into DMA Header Buffer */
/*hwHeaderLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4); */
hwHeaderLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf,
TXINFO_SIZE + TXWI_SIZE + hwHeaderLen);
pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
/* */
/* build Tx Descriptor */
/* */
pTxD = (struct rt_txd *) pTxRing->Cell[TxIdx].AllocVa;
NdisZeroMemory(pTxD, TXD_SIZE);
pTxD->SDPtr0 = BufBasePaLow;
pTxD->SDLen0 = TXINFO_SIZE + TXWI_SIZE + hwHeaderLen; /* include padding */
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, PCI_DMA_TODEVICE);
pTxD->SDLen1 = pTxBlk->SrcBufLen;
pTxD->LastSec0 = 0;
pTxD->LastSec1 = (bIsLast) ? 1 : 0;
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
RetTxIdx = TxIdx;
/* */
/* Update Tx index */
/* */
INC_RING_INDEX(TxIdx, TX_RING_SIZE);
pTxRing->TxCpuIdx = TxIdx;
*FreeNumber -= 1;
return RetTxIdx;
}
VOID RTUSBBulkReceive(
IN PRTMP_ADAPTER pAd)
{
PRX_CONTEXT pRxContext;
unsigned long IrqFlags;
/* sanity check */
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_HANDLE_RX)
&& !RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_POLL_IDLE))
return;
while(1)
{
RTMP_IRQ_LOCK(&pAd->BulkInLock, IrqFlags);
pRxContext = &(pAd->RxContext[pAd->NextRxBulkInReadIndex]);
if (((pRxContext->InUse == FALSE) && (pRxContext->Readable == TRUE)) &&
(pRxContext->bRxHandling == FALSE))
{
pRxContext->bRxHandling = TRUE;
RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
/* read RxContext, Since not */
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
STARxDoneInterruptHandle(pAd, TRUE);
#endif /* CONFIG_STA_SUPPORT */
/* Finish to handle this bulkIn buffer.*/
RTMP_IRQ_LOCK(&pAd->BulkInLock, IrqFlags);
pRxContext->BulkInOffset = 0;
pRxContext->Readable = FALSE;
pRxContext->bRxHandling = FALSE;
pAd->ReadPosition = 0;
pAd->TransferBufferLength = 0;
INC_RING_INDEX(pAd->NextRxBulkInReadIndex, RX_RING_SIZE);
RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
}
else
{
RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
break;
}
}
if (!((RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_RX)
&& (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_POLL_IDLE)))))
{
#ifdef CONFIG_STA_SUPPORT
if(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF) )
return;
#endif /* CONFIG_STA_SUPPORT */
DoBulkIn(pAd);
}
}
/*++
Routine Description:
handle TXDone interrupt routine..
Arguments:
FdoData Pointer to our FdoData
Return Value:
None
--*/
VOID
BthHandleTxRingDmaDoneInterrupt(
IN PRTBTH_ADAPTER pAd,
IN INT_SOURCE_CSR_STRUC TxRingBitmap)
{
PRT_TX_RING pTxRing;
PTXD_STRUC pTxD;
UCHAR RingIdx;
UCHAR Count;
UINT8 TxRingSize;
for (RingIdx = 0; RingIdx < NUM_OF_TX_RING; RingIdx++)
{
Count = 0;
pTxRing = &pAd->TxRing[RingIdx];
KeAcquireSpinLockAtDpcLevel(&pAd->SendLock);
RT_IO_READ32(pAd, TX_DTX_IDX0 + RingIdx * RINGREG_DIFF, &pTxRing->TxDmaIdx);
while ((pTxRing->TxDmaIdx != 0xffffffff) && (pTxRing->TxSwFreeIdx != pTxRing->TxDmaIdx))
{
#if 0
if (pTxRing->TxDmaIdx >= TX_RING_SIZE)
{
DebugPrint(ERROR, DBG_MISC, "BthHandleTxRingDmaDoneInterrupt: Invalid pTxRing->TxDmaIdx = 0x%08x\n", pTxRing->TxDmaIdx);
//
// Invalid value, try to read it again.
// It should be fine after read again.
//
RT_IO_READ32(pAd, TX_DTX_IDX0 + RingIdx * RINGREG_DIFF, &pTxRing->TxDmaIdx);
Count++;
if (Count > 10)
break;
continue;
}
#endif
pTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
if(pTxD->DmaDone == 0)
{
break;
}
//pTxD->DmaDone = 0;
//DebugPrint(TRACE, DBG_MISC, "-->%s(TxRing-%d):pTxRing->TxDmaIdx=0x%x, pTxRing->TxSwFreeIdx=0x%x!\n", __FUNCTION__, RingIdx, pTxRing->TxDmaIdx, pTxRing->TxSwFreeIdx);
TxRingSize = BthGetTxRingSize(pAd, RingIdx);
//INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TxRingSize);
KeSetEvent(&pAd->CoreEventTriggered, 1, FALSE);
}
KeReleaseSpinLockFromDpcLevel(&pAd->SendLock);
}
}
int RtmpPCIMgmtKickOut(
IN RTMP_ADAPTER *pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket,
IN PUCHAR pSrcBufVA,
IN UINT SrcBufLen)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
ULONG SwIdx = pAd->MgmtRing.TxCpuIdx;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC)pAd->MgmtRing.Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) pAd->MgmtRing.Cell[SwIdx].AllocVa;
#endif
pAd->MgmtRing.Cell[SwIdx].pNdisPacket = pPacket;
pAd->MgmtRing.Cell[SwIdx].pNextNdisPacket = NULL;
RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_MGMT);
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 1;
pTxD->DMADONE = 0;
pTxD->SDLen1 = 0;
pTxD->SDPtr0 = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
pTxD->SDLen0 = SrcBufLen;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
INC_RING_INDEX(pAd->MgmtRing.TxCpuIdx, MGMT_RING_SIZE);
RTMP_IO_WRITE32(pAd, TX_MGMTCTX_IDX, pAd->MgmtRing.TxCpuIdx);
return 0;
}
VOID RTUSBBulkReceive(
IN PRTMP_ADAPTER pAd)
{
PRX_CONTEXT pRxContext;
unsigned long IrqFlags;
/* sanity check */
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_HANDLE_RX))
return;
while(1)
{
RTMP_IRQ_LOCK(&pAd->BulkInLock, IrqFlags);
pRxContext = &(pAd->RxContext[pAd->NextRxBulkInReadIndex]);
if (((pRxContext->InUse == FALSE) && (pRxContext->Readable == TRUE)) &&
(pRxContext->bRxHandling == FALSE))
{
pRxContext->bRxHandling = TRUE;
RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
// read RxContext, Since not
STARxDoneInterruptHandle(pAd, TRUE);
// Finish to handle this bulkIn buffer.
RTMP_IRQ_LOCK(&pAd->BulkInLock, IrqFlags);
pRxContext->BulkInOffset = 0;
pRxContext->Readable = FALSE;
pRxContext->bRxHandling = FALSE;
pAd->ReadPosition = 0;
pAd->TransferBufferLength = 0;
INC_RING_INDEX(pAd->NextRxBulkInReadIndex, RX_RING_SIZE);
RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
}
else
{
RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
break;
}
}
if (!(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_RX)))
DoBulkIn(pAd);
}
/*
Must be run in Interrupt context
This function handle PCI specific TxDesc and cpu index update and kick the packet out.
*/
int RtmpPCIMgmtKickOut(struct rt_rtmp_adapter *pAd,
u8 QueIdx,
void *pPacket,
u8 *pSrcBufVA, u32 SrcBufLen)
{
struct rt_txd * pTxD;
unsigned long SwIdx = pAd->MgmtRing.TxCpuIdx;
pTxD = (struct rt_txd *) pAd->MgmtRing.Cell[SwIdx].AllocVa;
pAd->MgmtRing.Cell[SwIdx].pNdisPacket = pPacket;
pAd->MgmtRing.Cell[SwIdx].pNextNdisPacket = NULL;
RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_MGMT);
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 1;
pTxD->DMADONE = 0;
pTxD->SDLen1 = 0;
pTxD->SDPtr0 =
PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
pTxD->SDLen0 = SrcBufLen;
/*================================================================== */
/* DBGPRINT_RAW(RT_DEBUG_TRACE, ("MLMEHardTransmit\n"));
for (i = 0; i < (TXWI_SIZE+24); i++)
{
DBGPRINT_RAW(RT_DEBUG_TRACE, ("%x:", *(pSrcBufVA+i)));
if ( i%4 == 3)
DBGPRINT_RAW(RT_DEBUG_TRACE, (" :: "));
if ( i%16 == 15)
DBGPRINT_RAW(RT_DEBUG_TRACE, ("\n "));
}
DBGPRINT_RAW(RT_DEBUG_TRACE, ("\n "));*/
/*======================================================================= */
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
/* Increase TX_CTX_IDX, but write to register later. */
INC_RING_INDEX(pAd->MgmtRing.TxCpuIdx, MGMT_RING_SIZE);
RTMP_IO_WRITE32(pAd, TX_MGMTCTX_IDX, pAd->MgmtRing.TxCpuIdx);
return 0;
}
/*
========================================================================
Routine Description:
Process MGMT ring DMA done interrupt, running in DPC level
Arguments:
pAd Pointer to our adapter
Return Value:
None
IRQL = DISPATCH_LEVEL
Note:
========================================================================
*/
void RTMPHandleMgmtRingDmaDoneInterrupt(struct rt_rtmp_adapter *pAd)
{
struct rt_txd * pTxD;
void *pPacket;
/* int i; */
u8 FREE = 0;
struct rt_rtmp_mgmt_ring *pMgmtRing = &pAd->MgmtRing;
NdisAcquireSpinLock(&pAd->MgmtRingLock);
RTMP_IO_READ32(pAd, TX_MGMTDTX_IDX, &pMgmtRing->TxDmaIdx);
while (pMgmtRing->TxSwFreeIdx != pMgmtRing->TxDmaIdx) {
FREE++;
pTxD =
(struct rt_txd *) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].
AllocVa);
pTxD->DMADONE = 0;
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket;
if (pPacket) {
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0,
PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket = NULL;
pPacket =
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket;
if (pPacket) {
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1,
PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket = NULL;
INC_RING_INDEX(pMgmtRing->TxSwFreeIdx, MGMT_RING_SIZE);
}
NdisReleaseSpinLock(&pAd->MgmtRingLock);
}
/*
Must be run in Interrupt context
This function handle RT2870 specific TxDesc and cpu index update and kick the packet out.
*/
int RtmpUSBMgmtKickOut(
IN RTMP_ADAPTER *pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket,
IN PUCHAR pSrcBufVA,
IN UINT SrcBufLen)
{
PTXINFO_STRUC pTxInfo;
ULONG BulkOutSize;
UCHAR padLen;
PUCHAR pDest;
ULONG SwIdx = pAd->MgmtRing.TxCpuIdx;
PTX_CONTEXT pMLMEContext = (PTX_CONTEXT)pAd->MgmtRing.Cell[SwIdx].AllocVa;
unsigned long IrqFlags;
pTxInfo = (PTXINFO_STRUC)(pSrcBufVA);
// Build our URB for USBD
BulkOutSize = SrcBufLen;
BulkOutSize = (BulkOutSize + 3) & (~3);
RTMPWriteTxInfo(pAd, pTxInfo, (USHORT)(BulkOutSize - TXINFO_SIZE), TRUE, EpToQueue[MGMTPIPEIDX], FALSE, FALSE);
BulkOutSize += 4; // Always add 4 extra bytes at every packet.
// If BulkOutSize is multiple of BulkOutMaxPacketSize, add extra 4 bytes again.
if ((BulkOutSize % pAd->BulkOutMaxPacketSize) == 0)
BulkOutSize += 4;
padLen = BulkOutSize - SrcBufLen;
ASSERT((padLen <= RTMP_PKT_TAIL_PADDING));
// Now memzero all extra padding bytes.
pDest = (PUCHAR)(pSrcBufVA + SrcBufLen);
skb_put(GET_OS_PKT_TYPE(pPacket), padLen);
NdisZeroMemory(pDest, padLen);
RTMP_IRQ_LOCK(&pAd->MLMEBulkOutLock, IrqFlags);
pAd->MgmtRing.Cell[pAd->MgmtRing.TxCpuIdx].pNdisPacket = pPacket;
pMLMEContext->TransferBuffer = (PTX_BUFFER)(GET_OS_PKT_DATAPTR(pPacket));
// Length in TxInfo should be 8 less than bulkout size.
pMLMEContext->BulkOutSize = BulkOutSize;
pMLMEContext->InUse = TRUE;
pMLMEContext->bWaitingBulkOut = TRUE;
//for debug
//hex_dump("RtmpUSBMgmtKickOut", &pMLMEContext->TransferBuffer->field.WirelessPacket[0], (pMLMEContext->BulkOutSize > 16 ? 16 : pMLMEContext->BulkOutSize));
//pAd->RalinkCounters.KickTxCount++;
//pAd->RalinkCounters.OneSecTxDoneCount++;
//if (pAd->MgmtRing.TxSwFreeIdx == MGMT_RING_SIZE)
// needKickOut = TRUE;
// Decrease the TxSwFreeIdx and Increase the TX_CTX_IDX
pAd->MgmtRing.TxSwFreeIdx--;
INC_RING_INDEX(pAd->MgmtRing.TxCpuIdx, MGMT_RING_SIZE);
RTMP_IRQ_UNLOCK(&pAd->MLMEBulkOutLock, IrqFlags);
RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_MLME);
//if (needKickOut)
RTUSBKickBulkOut(pAd);
return 0;
}
/*
========================================================================
Routine Description:
Process MGMT ring DMA done interrupt, running in DPC level
Arguments:
pAd Pointer to our adapter
Return Value:
None
IRQL = DISPATCH_LEVEL
Note:
========================================================================
*/
VOID RTMPHandleMgmtRingDmaDoneInterrupt(
IN PRTMP_ADAPTER pAd)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PNDIS_PACKET pPacket;
/* int i;*/
UCHAR FREE = 0;
PRTMP_MGMT_RING pMgmtRing = &pAd->MgmtRing;
UINT8 TXWISize = pAd->chipCap.TXWISize;
NdisAcquireSpinLock(&pAd->MgmtRingLock);
RTMP_IO_READ32(pAd, TX_MGMTDTX_IDX, &pMgmtRing->TxDmaIdx);
while (pMgmtRing->TxSwFreeIdx!= pMgmtRing->TxDmaIdx)
{
FREE++;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
#endif
/* pTxD->DMADONE = 0; */
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket;
if (pPacket == NULL)
{
INC_RING_INDEX(pMgmtRing->TxSwFreeIdx, MGMT_RING_SIZE);
continue;
}
#define LMR_FRAME_GET() (GET_OS_PKT_DATAPTR(pPacket) + TXWISize)
#ifdef UAPSD_SUPPORT
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
UAPSD_QoSNullTxMgmtTxDoneHandle(pAd,
pPacket,
LMR_FRAME_GET());
}
#endif /* CONFIG_AP_SUPPORT */
#endif /* UAPSD_SUPPORT */
#ifdef CONFIG_AP_SUPPORT
#endif /* CONFIG_AP_SUPPORT */
if (pPacket)
{
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, RTMP_PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket = NULL;
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket;
if (pPacket)
{
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, RTMP_PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket = NULL;
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocPa,
RXD_SIZE);
INC_RING_INDEX(pMgmtRing->TxSwFreeIdx, MGMT_RING_SIZE);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, TRUE, TYPE_TXD);
#endif
}
NdisReleaseSpinLock(&pAd->MgmtRingLock);
}
/*
Must be run in Interrupt context
This function handle RT2870 specific TxDesc and cpu index update and kick the packet out.
*/
int RtmpUSBMgmtKickOut(struct rt_rtmp_adapter *pAd,
u8 QueIdx,
void *pPacket,
u8 *pSrcBufVA, u32 SrcBufLen)
{
struct rt_txinfo *pTxInfo;
unsigned long BulkOutSize;
u8 padLen;
u8 *pDest;
unsigned long SwIdx = pAd->MgmtRing.TxCpuIdx;
struct rt_tx_context *pMLMEContext =
(struct rt_tx_context *)pAd->MgmtRing.Cell[SwIdx].AllocVa;
unsigned long IrqFlags;
pTxInfo = (struct rt_txinfo *)(pSrcBufVA);
/* Build our URB for USBD */
BulkOutSize = SrcBufLen;
BulkOutSize = (BulkOutSize + 3) & (~3);
RTMPWriteTxInfo(pAd, pTxInfo, (u16)(BulkOutSize - TXINFO_SIZE),
TRUE, EpToQueue[MGMTPIPEIDX], FALSE, FALSE);
BulkOutSize += 4; /* Always add 4 extra bytes at every packet. */
/* If BulkOutSize is multiple of BulkOutMaxPacketSize, add extra 4 bytes again. */
if ((BulkOutSize % pAd->BulkOutMaxPacketSize) == 0)
BulkOutSize += 4;
padLen = BulkOutSize - SrcBufLen;
ASSERT((padLen <= RTMP_PKT_TAIL_PADDING));
/* Now memzero all extra padding bytes. */
pDest = (u8 *)(pSrcBufVA + SrcBufLen);
skb_put(GET_OS_PKT_TYPE(pPacket), padLen);
NdisZeroMemory(pDest, padLen);
RTMP_IRQ_LOCK(&pAd->MLMEBulkOutLock, IrqFlags);
pAd->MgmtRing.Cell[pAd->MgmtRing.TxCpuIdx].pNdisPacket = pPacket;
pMLMEContext->TransferBuffer =
(struct rt_tx_buffer *)(GET_OS_PKT_DATAPTR(pPacket));
/* Length in TxInfo should be 8 less than bulkout size. */
pMLMEContext->BulkOutSize = BulkOutSize;
pMLMEContext->InUse = TRUE;
pMLMEContext->bWaitingBulkOut = TRUE;
/*for debug */
/*hex_dump("RtmpUSBMgmtKickOut", &pMLMEContext->TransferBuffer->field.WirelessPacket[0], (pMLMEContext->BulkOutSize > 16 ? 16 : pMLMEContext->BulkOutSize)); */
/*pAd->RalinkCounters.KickTxCount++; */
/*pAd->RalinkCounters.OneSecTxDoneCount++; */
/*if (pAd->MgmtRing.TxSwFreeIdx == MGMT_RING_SIZE) */
/* needKickOut = TRUE; */
/* Decrease the TxSwFreeIdx and Increase the TX_CTX_IDX */
pAd->MgmtRing.TxSwFreeIdx--;
INC_RING_INDEX(pAd->MgmtRing.TxCpuIdx, MGMT_RING_SIZE);
RTMP_IRQ_UNLOCK(&pAd->MLMEBulkOutLock, IrqFlags);
RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_MLME);
/*if (needKickOut) */
RTUSBKickBulkOut(pAd);
return 0;
}
USHORT RtmpPCI_WriteMultiTxResource(
IN PRTMP_ADAPTER pAd,
IN TX_BLK *pTxBlk,
IN UCHAR frameNum,
OUT USHORT *FreeNumber)
{
BOOLEAN bIsLast;
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHdrLen;
UINT32 firstDMALen;
bIsLast = ((frameNum == (pTxBlk->TotalFrameNum - 1)) ? 1 : 0);
pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
BufBasePaLow = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
if (frameNum == 0)
{
if (pTxBlk->TxFrameType == TX_AMSDU_FRAME)
hwHdrLen = pTxBlk->MpduHeaderLen - LENGTH_AMSDU_SUBFRAMEHEAD + pTxBlk->HdrPadLen + LENGTH_AMSDU_SUBFRAMEHEAD;
else if (pTxBlk->TxFrameType == TX_RALINK_FRAME)
hwHdrLen = pTxBlk->MpduHeaderLen - LENGTH_ARALINK_HEADER_FIELD + pTxBlk->HdrPadLen + LENGTH_ARALINK_HEADER_FIELD;
else
hwHdrLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
firstDMALen = TXINFO_SIZE + TXWI_SIZE + hwHdrLen;
}
else
{
firstDMALen = pTxBlk->MpduHeaderLen;
}
NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf, firstDMALen);
pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
NdisZeroMemory(pTxD, TXD_SIZE);
pTxD->SDPtr0 = BufBasePaLow;
pTxD->SDLen0 = firstDMALen;
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, PCI_DMA_TODEVICE);;
pTxD->SDLen1 = pTxBlk->SrcBufLen;
pTxD->LastSec0 = 0;
pTxD->LastSec1 = (bIsLast) ? 1 : 0;
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
if (frameNum == 0)
RTMPFrameEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA+ TXINFO_SIZE + TXWI_SIZE), DIR_WRITE, FALSE);
if (frameNum != 0)
RTMPWIEndianChange((PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE), TYPE_TXWI);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
RetTxIdx = TxIdx;
INC_RING_INDEX(TxIdx, TX_RING_SIZE);
pTxRing->TxCpuIdx = TxIdx;
*FreeNumber -= 1;
return RetTxIdx;
}
USHORT RtmpPCI_WriteSingleTxResource(
IN PRTMP_ADAPTER pAd,
IN TX_BLK *pTxBlk,
IN BOOLEAN bIsLast,
OUT USHORT *FreeNumber)
{
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHeaderLen;
//
// get Tx Ring Resource
//
pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
BufBasePaLow = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
// copy TXINFO + TXWI + WLAN Header + LLC into DMA Header Buffer
//hwHeaderLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4);
hwHeaderLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf, TXINFO_SIZE + TXWI_SIZE + hwHeaderLen);
pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
//
// build Tx Descriptor
//
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
NdisZeroMemory(pTxD, TXD_SIZE);
pTxD->SDPtr0 = BufBasePaLow;
pTxD->SDLen0 = TXINFO_SIZE + TXWI_SIZE + hwHeaderLen; // include padding
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, PCI_DMA_TODEVICE);;
pTxD->SDLen1 = pTxBlk->SrcBufLen;
pTxD->LastSec0 = 0;
pTxD->LastSec1 = (bIsLast) ? 1 : 0;
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE), TYPE_TXWI);
RTMPFrameEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE + TXWI_SIZE), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif // RT_BIG_ENDIAN //
RetTxIdx = TxIdx;
//
// Update Tx index
//
INC_RING_INDEX(TxIdx, TX_RING_SIZE);
pTxRing->TxCpuIdx = TxIdx;
*FreeNumber -= 1;
return RetTxIdx;
}
NDIS_STATUS MlmeHardTransmitTxRing(
IN PRTMP_ADAPTER pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket)
{
PACKET_INFO PacketInfo;
PUCHAR pSrcBufVA;
UINT SrcBufLen;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PHEADER_802_11 pHeader_802_11;
BOOLEAN bAckRequired, bInsertTimestamp;
ULONG SrcBufPA;
//UCHAR TxBufIdx;
UCHAR MlmeRate;
ULONG SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
PTXWI_STRUC pFirstTxWI;
//ULONG i;
//HTTRANSMIT_SETTING MlmeTransmit; //Rate for this MGMT frame.
ULONG FreeNum;
MAC_TABLE_ENTRY *pMacEntry = NULL;
RTMP_QueryPacketInfo(pPacket, &PacketInfo, &pSrcBufVA, &SrcBufLen);
if (pSrcBufVA == NULL)
{
// The buffer shouldn't be NULL
return NDIS_STATUS_FAILURE;
}
// Make sure MGMT ring resource won't be used by other threads
//NdisAcquireSpinLock(&pAd->TxRingLock);
FreeNum = GET_TXRING_FREENO(pAd, QueIdx);
if (FreeNum == 0)
{
//NdisReleaseSpinLock(&pAd->TxRingLock);
return NDIS_STATUS_FAILURE;
}
SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC)pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
if (pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket)
{
DBGPRINT(RT_DEBUG_OFF, ("MlmeHardTransmit Error\n"));
//NdisReleaseSpinLock(&pAd->TxRingLock);
return NDIS_STATUS_FAILURE;
}
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
// outgoing frame always wakeup PHY to prevent frame lost
// if (pAd->StaCfg.Psm == PWR_SAVE)
if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
AsicForceWakeup(pAd, TRUE);
}
#endif // CONFIG_STA_SUPPORT //
pFirstTxWI =(PTXWI_STRUC)pSrcBufVA;
pHeader_802_11 = (PHEADER_802_11) (pSrcBufVA + TXWI_SIZE);
if (pHeader_802_11->Addr1[0] & 0x01)
{
MlmeRate = pAd->CommonCfg.BasicMlmeRate;
}
else
{
MlmeRate = pAd->CommonCfg.MlmeRate;
}
if ((pHeader_802_11->FC.Type == BTYPE_DATA) &&
(pHeader_802_11->FC.SubType == SUBTYPE_QOS_NULL))
{
pMacEntry = MacTableLookup(pAd, pHeader_802_11->Addr1);
}
// Verify Mlme rate for a / g bands.
if ((pAd->LatchRfRegs.Channel > 14) && (MlmeRate < RATE_6)) // 11A band
MlmeRate = RATE_6;
//
// Should not be hard code to set PwrMgmt to 0 (PWR_ACTIVE)
// Snice it's been set to 0 while on MgtMacHeaderInit
// By the way this will cause frame to be send on PWR_SAVE failed.
//
//
// In WMM-UAPSD, mlme frame should be set psm as power saving but probe request frame
#ifdef CONFIG_STA_SUPPORT
// Data-Null packets alse pass through MMRequest in RT2860, however, we hope control the psm bit to pass APSD
if (pHeader_802_11->FC.Type != BTYPE_DATA)
{
if ((pHeader_802_11->FC.SubType == SUBTYPE_PROBE_REQ) || !(pAd->CommonCfg.bAPSDCapable && pAd->CommonCfg.APEdcaParm.bAPSDCapable))
{
pHeader_802_11->FC.PwrMgmt = PWR_ACTIVE;
}
else
{
pHeader_802_11->FC.PwrMgmt = pAd->CommonCfg.bAPSDForcePowerSave;
}
}
#endif // CONFIG_STA_SUPPORT //
bInsertTimestamp = FALSE;
if (pHeader_802_11->FC.Type == BTYPE_CNTL) // must be PS-POLL
{
bAckRequired = FALSE;
}
else // BTYPE_MGMT or BTYPE_DATA(must be NULL frame)
{
if (pHeader_802_11->Addr1[0] & 0x01) // MULTICAST, BROADCAST
{
bAckRequired = FALSE;
pHeader_802_11->Duration = 0;
}
else
{
bAckRequired = TRUE;
pHeader_802_11->Duration = RTMPCalcDuration(pAd, MlmeRate, 14);
if (pHeader_802_11->FC.SubType == SUBTYPE_PROBE_RSP)
{
bInsertTimestamp = TRUE;
}
}
}
pHeader_802_11->Sequence = pAd->Sequence++;
if (pAd->Sequence > 0xfff)
pAd->Sequence = 0;
// Before radar detection done, mgmt frame can not be sent but probe req
// Because we need to use probe req to trigger driver to send probe req in passive scan
if ((pHeader_802_11->FC.SubType != SUBTYPE_PROBE_REQ)
&& (pAd->CommonCfg.bIEEE80211H == 1)
&& (pAd->CommonCfg.RadarDetect.RDMode != RD_NORMAL_MODE))
{
DBGPRINT(RT_DEBUG_ERROR,("MlmeHardTransmit --> radar detect not in normal mode !!!\n"));
//NdisReleaseSpinLock(&pAd->TxRingLock);
return (NDIS_STATUS_FAILURE);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader_802_11, DIR_WRITE, FALSE);
#endif
//
// fill scatter-and-gather buffer list into TXD. Internally created NDIS PACKET
// should always has only one ohysical buffer, and the whole frame size equals
// to the first scatter buffer size
//
// Initialize TX Descriptor
// For inter-frame gap, the number is for this frame and next frame
// For MLME rate, we will fix as 2Mb to match other vendor's implement
// pAd->CommonCfg.MlmeTransmit.field.MODE = 1;
// management frame doesn't need encryption. so use RESERVED_WCID no matter u are sending to specific wcid or not.
// Only beacon use Nseq=TRUE. So here we use Nseq=FALSE.
if (pMacEntry == NULL)
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE, bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, RESERVED_WCID, (SrcBufLen - TXWI_SIZE), PID_MGMT, 0, (UCHAR)pAd->CommonCfg.MlmeTransmit.field.MCS, IFS_BACKOFF, FALSE, &pAd->CommonCfg.MlmeTransmit);
}
else
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE,
bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, pMacEntry->Aid, (SrcBufLen - TXWI_SIZE),
pMacEntry->MaxHTPhyMode.field.MCS, 0,
(UCHAR)pMacEntry->MaxHTPhyMode.field.MCS,
IFS_BACKOFF, FALSE, &pMacEntry->MaxHTPhyMode);
}
pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket = pPacket;
pAd->TxRing[QueIdx].Cell[SwIdx].pNextNdisPacket = NULL;
// pFirstTxWI->MPDUtotalByteCount = SrcBufLen - TXWI_SIZE;
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)pFirstTxWI, TYPE_TXWI);
#endif
SrcBufPA = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_EDCA);
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 1;
pTxD->SDLen0 = SrcBufLen;
pTxD->SDLen1 = 0;
pTxD->SDPtr0 = SrcBufPA;
pTxD->DMADONE = 0;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
// Increase TX_CTX_IDX, but write to register later.
INC_RING_INDEX(pAd->TxRing[QueIdx].TxCpuIdx, TX_RING_SIZE);
RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QueIdx*0x10, pAd->TxRing[QueIdx].TxCpuIdx);
// Make sure to release MGMT ring resource
// NdisReleaseSpinLock(&pAd->TxRingLock);
return NDIS_STATUS_SUCCESS;
}
/*
==========================================================================
Description:
Update the station current power save mode. Calling this routine also
prove the specified client is still alive. Otherwise AP will age-out
this client once IdleCount exceeds a threshold.
==========================================================================
*/
BOOLEAN MtPsIndicate(RTMP_ADAPTER *pAd, UCHAR *pAddr, UCHAR wcid, UCHAR Psm)
{
MAC_TABLE_ENTRY *pEntry;
UCHAR old_psmode;
STA_TR_ENTRY *tr_entry;
if (wcid >= MAX_LEN_OF_MAC_TABLE)
{
return PWR_ACTIVE;
}
pEntry = &pAd->MacTab.Content[wcid];
tr_entry = &pAd->MacTab.tr_entry[wcid];
/*
Change power save mode first because we will call
RTMPDeQueuePacket() in RtmpHandleRxPsPoll().
Or when Psm = PWR_ACTIVE, we will not do Aggregation in
RTMPDeQueuePacket().
*/
old_psmode = pEntry->PsMode;
pEntry->NoDataIdleCount = 0;
pEntry->PsMode = Psm;
pAd->MacTab.tr_entry[wcid].PsMode = Psm;
if ((old_psmode == PWR_SAVE) && (Psm == PWR_ACTIVE))
{
/*
STA wakes up.
*/
if(tr_entry->ps_state == APPS_RETRIEVE_DONE)
{
tr_entry->ps_state = APPS_RETRIEVE_IDLE;
DBGPRINT(RT_DEBUG_INFO | DBG_FUNC_PS, ("%s(%d): STA wakes up!\n", __FUNCTION__, __LINE__));
MtHandleRxPsPoll(pAd, pAddr, wcid, TRUE);
}
else
DBGPRINT(RT_DEBUG_INFO | DBG_FUNC_PS, ("%s(%d):wcid=%d, old_psmode=%d, now_psmode=%d, wrong ps_state=%d ???\n",
__FUNCTION__, __LINE__, wcid, old_psmode, Psm, tr_entry->ps_state));
}
else if ((old_psmode == PWR_ACTIVE) && (Psm == PWR_SAVE))
{
/*
STA goes to sleep.
*/
if (tr_entry->ps_state == APPS_RETRIEVE_IDLE)
{
#ifdef MT_PS
DBGPRINT(RT_DEBUG_INFO | DBG_FUNC_PS, ("%s(%d):wcid=%d, old_psmode=%d, now_psmode=%d, ps_state=%d start retrieving!!\n",
__FUNCTION__, __LINE__, wcid, old_psmode, Psm, tr_entry->ps_state));
#if defined(MT7603) && defined(RTMP_PCI_SUPPORT)
if (MtStartPSRetrieve(pAd, wcid) == TRUE) {
tr_entry->ps_state = APPS_RETRIEVE_START_PS;
} else {
struct tx_swq_fifo *ps_fifo_swq;
INT enq_idx;
ps_fifo_swq = &pAd->apps_cr_q;
enq_idx = ps_fifo_swq->enqIdx;
if (ps_fifo_swq->swq[enq_idx] == 0)
{
ps_fifo_swq->swq[enq_idx] = wcid;
INC_RING_INDEX(ps_fifo_swq->enqIdx, TX_SWQ_FIFO_LEN);
tr_entry->ps_state = APPS_RETRIEVE_CR_PADDING;
} else {
INT idx;
tr_entry->ps_state = APPS_RETRIEVE_DONE;
DBGPRINT(RT_DEBUG_ERROR, ("%s: ERROR!! ps_fifo_swq->deqIdx=%d, ps_fifo_swq->enqIdx=%d\n", __FUNCTION__,ps_fifo_swq->deqIdx,ps_fifo_swq->enqIdx));
for (idx =0; idx < TX_SWQ_FIFO_LEN;idx++) {
DBGPRINT(RT_DEBUG_ERROR, (",[%d] =%d\n", idx, ps_fifo_swq->swq[idx]));
if ((idx % 16) == 0)
DBGPRINT(RT_DEBUG_ERROR, ("\n"));
}
DBGPRINT(RT_DEBUG_ERROR, ("\n"));
}
}
#else /* !MT7603 && RTMP_PCI_SUPPORT */
RTEnqueueInternalCmd(pAd, CMDTHREAD_PS_RETRIEVE_START, pEntry, sizeof(MAC_TABLE_ENTRY));
#endif /* MT7603 && RTMP_PCI_SUPPORT */
#else /* MT_PS */
tr_entry->ps_state = APPS_RETRIEVE_DONE;
#endif /* !MT_PS */
}
else
DBGPRINT(RT_DEBUG_INFO | DBG_FUNC_PS, ("%s(%d):wcid=%d, old_psmode=%d, now_psmode=%d, wrong ps_state=%d ???\n",
__FUNCTION__, __LINE__, wcid, old_psmode, Psm, tr_entry->ps_state));
}
else
{
DBGPRINT(RT_DEBUG_INFO | DBG_FUNC_PS, ("%s(%d): ps state is not changed, do nothing here.\n",
__FUNCTION__, __LINE__));
}
return old_psmode;
}
USHORT RtmpPCI_WriteTxResource(
IN PRTMP_ADAPTER pAd,
IN TX_BLK *pTxBlk,
IN BOOLEAN bIsLast,
OUT USHORT *FreeNumber)
{
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHeaderLen;
pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
BufBasePaLow = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
if (pTxBlk->TxFrameType == TX_AMSDU_FRAME)
{
hwHeaderLen = pTxBlk->MpduHeaderLen - LENGTH_AMSDU_SUBFRAMEHEAD + pTxBlk->HdrPadLen + LENGTH_AMSDU_SUBFRAMEHEAD;
}
else
{
hwHeaderLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
}
NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf, TXINFO_SIZE + TXWI_SIZE + hwHeaderLen);
pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
NdisZeroMemory(pTxD, TXD_SIZE);
pTxD->SDPtr0 = BufBasePaLow;
pTxD->SDLen0 = TXINFO_SIZE + TXWI_SIZE + hwHeaderLen;
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, PCI_DMA_TODEVICE);
pTxD->SDLen1 = pTxBlk->SrcBufLen;
pTxD->LastSec0 = 0;
pTxD->LastSec1 = (bIsLast) ? 1 : 0;
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
RetTxIdx = TxIdx;
INC_RING_INDEX(TxIdx, TX_RING_SIZE);
pTxRing->TxCpuIdx = TxIdx;
*FreeNumber -= 1;
return RetTxIdx;
}
BOOLEAN RTMPFreeTXDUponTxDmaDone(
IN PRTMP_ADAPTER pAd,
IN UCHAR QueIdx)
{
PRTMP_TX_RING pTxRing;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
#endif
PNDIS_PACKET pPacket;
UCHAR FREE = 0;
TXD_STRUC TxD, *pOriTxD;
BOOLEAN bReschedule = FALSE;
ASSERT(QueIdx < NUM_OF_TX_RING);
pTxRing = &pAd->TxRing[QueIdx];
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF, &pTxRing->TxDmaIdx);
while (pTxRing->TxSwFreeIdx != pTxRing->TxDmaIdx)
{
#ifdef RALINK_ATE
#ifdef RALINK_28xx_QA
PHEADER_802_11 pHeader80211;
if ((ATE_ON(pAd)) && (pAd->ate.bQATxStart == TRUE))
{
if (pAd->ate.QID == QueIdx)
{
pAd->ate.TxDoneCount++;
pAd->RalinkCounters.KickTxCount++;
ASSERT(pAd->ate.QID == 0);
pAd->ate.TxAc0++;
FREE++;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
pHeader80211 = pTxRing->Cell[pTxRing->TxSwFreeIdx].DmaBuf.AllocVa + sizeof(TXWI_STRUC);
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader80211, DIR_READ, FALSE);
#endif
pHeader80211->Sequence = ++pAd->ate.seq;
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader80211, DIR_WRITE, FALSE);
#endif
if ((pAd->ate.bQATxStart == TRUE) && (pAd->ate.Mode & ATE_TXFRAME) && (pAd->ate.TxDoneCount < pAd->ate.TxCount))
{
pAd->RalinkCounters.TransmittedByteCount += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecTransmittedByteCount += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecDmaDoneCount[QueIdx] ++;
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF , &pTxRing->TxDmaIdx);
goto kick_out;
}
else if ((pAd->ate.TxStatus == 1) && (pAd->ate.TxDoneCount == pAd->ate.TxCount))
{
DBGPRINT(RT_DEBUG_TRACE,("all Tx is done\n"));
pAd->ate.TxStatus = 0;
}
else if (!(pAd->ate.Mode & ATE_TXFRAME))
{
DBGPRINT(RT_DEBUG_ERROR,("not complete sending yet, but someone pressed the Stop TX bottom\n"));
DBGPRINT(RT_DEBUG_ERROR,("pAd->ate.Mode = 0x%02x\n", pAd->ate.Mode));
}
else
{
DBGPRINT(RT_DEBUG_OFF,("pTxRing->TxSwFreeIdx = %d\n", pTxRing->TxSwFreeIdx));
}
#ifndef RT_BIG_ENDIAN
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#else
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#endif
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
continue;
}
}
#endif
#endif
NICUpdateFifoStaCounters(pAd);
FREE++;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
#ifdef RALINK_ATE
if (!(ATE_ON(pAd)))
#endif
{
pPacket = pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket;
if (pPacket)
{
#ifdef CONFIG_5VT_ENHANCE
if (RTMP_GET_PACKET_5VT(pPacket))
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, 16, PCI_DMA_TODEVICE);
else
#endif
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket = NULL;
pPacket = pTxRing->Cell[pTxRing->TxSwFreeIdx].pNextNdisPacket;
ASSERT(pPacket == NULL);
if (pPacket)
{
#ifdef CONFIG_5VT_ENHANCE
if (RTMP_GET_PACKET_5VT(pPacket))
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, 16, PCI_DMA_TODEVICE);
else
#endif
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pTxRing->Cell[pTxRing->TxSwFreeIdx].pNextNdisPacket = NULL;
}
pAd->RalinkCounters.TransmittedByteCount += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecDmaDoneCount[QueIdx] ++;
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF , &pTxRing->TxDmaIdx);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#else
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#endif
#ifdef RALINK_ATE
#ifdef RALINK_28xx_QA
kick_out:
#endif
if ((pAd->ate.Mode & ATE_TXFRAME) && (pAd->ate.QID == QueIdx))
{
if (pAd->ate.bQATxStart == FALSE)
{
pAd->ate.TxDoneCount++;
}
if (((pAd->ate.TxCount - pAd->ate.TxDoneCount + 1) >= TX_RING_SIZE))
{
INC_RING_INDEX(pAd->TxRing[QueIdx].TxCpuIdx, TX_RING_SIZE);
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pAd->TxRing[QueIdx].TxCpuIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pAd->TxRing[QueIdx].TxCpuIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
#ifndef RT_BIG_ENDIAN
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#else
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#endif
RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QueIdx * RINGREG_DIFF, pAd->TxRing[QueIdx].TxCpuIdx);
pAd->RalinkCounters.KickTxCount++;
}
}
#endif
}
return bReschedule;
}
USHORT RtmpPCI_WriteFragTxResource(
IN PRTMP_ADAPTER pAd,
IN TX_BLK *pTxBlk,
IN UCHAR fragNum,
OUT USHORT *FreeNumber)
{
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHeaderLen;
UINT32 firstDMALen;
pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
BufBasePaLow = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
hwHeaderLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
firstDMALen = TXINFO_SIZE + TXWI_SIZE + hwHeaderLen;
NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf, firstDMALen);
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
NdisZeroMemory(pTxD, TXD_SIZE);
if (fragNum == pTxBlk->TotalFragNum)
{
pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
}
pTxD->SDPtr0 = BufBasePaLow;
pTxD->SDLen0 = firstDMALen;
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, PCI_DMA_TODEVICE);
pTxD->SDLen1 = pTxBlk->SrcBufLen;
pTxD->LastSec0 = 0;
pTxD->LastSec1 = 1;
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE), TYPE_TXWI);
RTMPFrameEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE + TXWI_SIZE), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
RetTxIdx = TxIdx;
pTxBlk->Priv += pTxBlk->SrcBufLen;
INC_RING_INDEX(TxIdx, TX_RING_SIZE);
pTxRing->TxCpuIdx = TxIdx;
*FreeNumber -= 1;
return RetTxIdx;
}
/*
========================================================================
Routine Description:
Read statistical counters from hardware registers and record them
in software variables for later on query
Arguments:
pAd Pointer to our adapter
Return Value:
None
IRQL = DISPATCH_LEVEL
========================================================================
*/
VOID NICUpdateRawCounters(RTMP_ADAPTER *pAd)
{
UINT32 OldValue;/*, Value2;*/
/*ULONG PageSum, OneSecTransmitCount;*/
/*ULONG TxErrorRatio, Retry, Fail;*/
RX_STA_CNT0_STRUC RxStaCnt0;
RX_STA_CNT1_STRUC RxStaCnt1;
RX_STA_CNT2_STRUC RxStaCnt2;
TX_STA_CNT0_STRUC TxStaCnt0;
TX_STA_CNT1_STRUC StaTx1;
TX_STA_CNT2_STRUC StaTx2;
#ifdef STATS_COUNT_SUPPORT
TX_NAG_AGG_CNT_STRUC TxAggCnt;
TX_AGG_CNT0_STRUC TxAggCnt0;
TX_AGG_CNT1_STRUC TxAggCnt1;
TX_AGG_CNT2_STRUC TxAggCnt2;
TX_AGG_CNT3_STRUC TxAggCnt3;
TX_AGG_CNT4_STRUC TxAggCnt4;
TX_AGG_CNT5_STRUC TxAggCnt5;
TX_AGG_CNT6_STRUC TxAggCnt6;
TX_AGG_CNT7_STRUC TxAggCnt7;
#endif /* STATS_COUNT_SUPPORT */
COUNTER_RALINK *pRalinkCounters;
// TODO: shiang-7603
if (pAd->chipCap.hif_type == HIF_MT) {
DBGPRINT(RT_DEBUG_OFF, ("%s(%d): Not support for HIF_MT yet!\n",
__FUNCTION__, __LINE__));
return;
}
pRalinkCounters = &pAd->RalinkCounters;
// TODO: shiang-7603, fix this!
if (pAd->chipCap.hif_type != HIF_MT) {
RTMP_IO_READ32(pAd, RX_STA_CNT0, &RxStaCnt0.word);
RTMP_IO_READ32(pAd, RX_STA_CNT2, &RxStaCnt2.word);
}
pAd->RalinkCounters.PhyErrCnt += RxStaCnt0.field.PhyErr;
#ifdef CONFIG_AP_SUPPORT
#ifdef CARRIER_DETECTION_SUPPORT
if ((pAd->CommonCfg.CarrierDetect.Enable == FALSE) || (pAd->OpMode == OPMODE_STA))
#endif /* CARRIER_DETECTION_SUPPORT */
#endif /* CONFIG_AP_SUPPORT */
{
// TODO: shiang-7603, fix this!
if (pAd->chipCap.hif_type != HIF_MT) {
RTMP_IO_READ32(pAd, RX_STA_CNT1, &RxStaCnt1.word);
}
/* Update RX PLCP error counter*/
pAd->RalinkCounters.PlcpErrCnt += RxStaCnt1.field.PlcpErr;
/* Update False CCA counter*/
pAd->RalinkCounters.OneSecFalseCCACnt = RxStaCnt1.field.FalseCca;
pAd->RalinkCounters.FalseCCACnt += RxStaCnt1.field.FalseCca;
}
#ifdef STATS_COUNT_SUPPORT
/* Update FCS counters*/
OldValue= pAd->WlanCounters.FCSErrorCount.u.LowPart;
pAd->WlanCounters.FCSErrorCount.u.LowPart += (RxStaCnt0.field.CrcErr); /* >> 7);*/
if (pAd->WlanCounters.FCSErrorCount.u.LowPart < OldValue)
pAd->WlanCounters.FCSErrorCount.u.HighPart++;
#endif /* STATS_COUNT_SUPPORT */
/* Add FCS error count to private counters*/
pRalinkCounters->OneSecRxFcsErrCnt += RxStaCnt0.field.CrcErr;
OldValue = pRalinkCounters->RealFcsErrCount.u.LowPart;
pRalinkCounters->RealFcsErrCount.u.LowPart += RxStaCnt0.field.CrcErr;
if (pRalinkCounters->RealFcsErrCount.u.LowPart < OldValue)
pRalinkCounters->RealFcsErrCount.u.HighPart++;
/* Update Duplicate Rcv check*/
pRalinkCounters->DuplicateRcv += RxStaCnt2.field.RxDupliCount;
#ifdef STATS_COUNT_SUPPORT
pAd->WlanCounters.FrameDuplicateCount.u.LowPart += RxStaCnt2.field.RxDupliCount;
#endif /* STATS_COUNT_SUPPORT */
/* Update RX Overflow counter*/
pAd->Counters8023.RxNoBuffer += (RxStaCnt2.field.RxFifoOverflowCount);
/*pAd->RalinkCounters.RxCount = 0;*/
/*if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED) || */
/* (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED) && (pAd->MacTab.Size != 1)))*/
if (!pAd->bUpdateBcnCntDone)
{
/* Update BEACON sent count*/
NicGetTxRawCounters(pAd, &TxStaCnt0, &StaTx1);
// TODO: shiang-7603, fix this!
if (pAd->chipCap.hif_type != HIF_MT) {
RTMP_IO_READ32(pAd, TX_STA_CNT2, &StaTx2.word);
}
}
/*if (pAd->bStaFifoTest == TRUE)*/
#ifdef STATS_COUNT_SUPPORT
{
// TODO: shiang-7603, fix this!
if (pAd->chipCap.hif_type != HIF_MT) {
RTMP_IO_READ32(pAd, TX_AGG_CNT, &TxAggCnt.word);
RTMP_IO_READ32(pAd, TX_AGG_CNT0, &TxAggCnt0.word);
RTMP_IO_READ32(pAd, TX_AGG_CNT1, &TxAggCnt1.word);
RTMP_IO_READ32(pAd, TX_AGG_CNT2, &TxAggCnt2.word);
RTMP_IO_READ32(pAd, TX_AGG_CNT3, &TxAggCnt3.word);
RTMP_IO_READ32(pAd, TX_AGG_CNT4, &TxAggCnt4.word);
RTMP_IO_READ32(pAd, TX_AGG_CNT5, &TxAggCnt5.word);
RTMP_IO_READ32(pAd, TX_AGG_CNT6, &TxAggCnt6.word);
RTMP_IO_READ32(pAd, TX_AGG_CNT7, &TxAggCnt7.word);
}
pRalinkCounters->TxAggCount += TxAggCnt.field.AggTxCount;
pRalinkCounters->TxNonAggCount += TxAggCnt.field.NonAggTxCount;
pRalinkCounters->TxAgg1MPDUCount += TxAggCnt0.field.AggSize1Count;
pRalinkCounters->TxAgg2MPDUCount += TxAggCnt0.field.AggSize2Count;
pRalinkCounters->TxAgg3MPDUCount += TxAggCnt1.field.AggSize3Count;
pRalinkCounters->TxAgg4MPDUCount += TxAggCnt1.field.AggSize4Count;
pRalinkCounters->TxAgg5MPDUCount += TxAggCnt2.field.AggSize5Count;
pRalinkCounters->TxAgg6MPDUCount += TxAggCnt2.field.AggSize6Count;
pRalinkCounters->TxAgg7MPDUCount += TxAggCnt3.field.AggSize7Count;
pRalinkCounters->TxAgg8MPDUCount += TxAggCnt3.field.AggSize8Count;
pRalinkCounters->TxAgg9MPDUCount += TxAggCnt4.field.AggSize9Count;
pRalinkCounters->TxAgg10MPDUCount += TxAggCnt4.field.AggSize10Count;
pRalinkCounters->TxAgg11MPDUCount += TxAggCnt5.field.AggSize11Count;
pRalinkCounters->TxAgg12MPDUCount += TxAggCnt5.field.AggSize12Count;
pRalinkCounters->TxAgg13MPDUCount += TxAggCnt6.field.AggSize13Count;
pRalinkCounters->TxAgg14MPDUCount += TxAggCnt6.field.AggSize14Count;
pRalinkCounters->TxAgg15MPDUCount += TxAggCnt7.field.AggSize15Count;
pRalinkCounters->TxAgg16MPDUCount += TxAggCnt7.field.AggSize16Count;
/* Calculate the transmitted A-MPDU count*/
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += TxAggCnt0.field.AggSize1Count;
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt0.field.AggSize2Count >> 1);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt1.field.AggSize3Count / 3);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt1.field.AggSize4Count >> 2);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt2.field.AggSize5Count / 5);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt2.field.AggSize6Count / 6);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt3.field.AggSize7Count / 7);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt3.field.AggSize8Count >> 3);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt4.field.AggSize9Count / 9);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt4.field.AggSize10Count / 10);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt5.field.AggSize11Count / 11);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt5.field.AggSize12Count / 12);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt6.field.AggSize13Count / 13);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt6.field.AggSize14Count / 14);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt7.field.AggSize15Count / 15);
pRalinkCounters->TransmittedAMPDUCount.u.LowPart += (TxAggCnt7.field.AggSize16Count >> 4);
}
#endif /* STATS_COUNT_SUPPORT */
#ifdef DBG_DIAGNOSE
{
RtmpDiagStruct *pDiag;
UCHAR ArrayCurIdx, i;
struct dbg_diag_info *diag_info;
pDiag = &pAd->DiagStruct;
ArrayCurIdx = pDiag->ArrayCurIdx;
if (pDiag->inited == 0)
{
NdisZeroMemory(pDiag, sizeof(struct _RtmpDiagStrcut_));
pDiag->ArrayStartIdx = pDiag->ArrayCurIdx = 0;
pDiag->inited = 1;
}
else
{
diag_info = &pDiag->diag_info[ArrayCurIdx];
/* Tx*/
diag_info->TxFailCnt = TxStaCnt0.field.TxFailCount;
#ifdef DBG_TX_AGG_CNT
diag_info->TxAggCnt = TxAggCnt.field.AggTxCount;
diag_info->TxNonAggCnt = TxAggCnt.field.NonAggTxCount;
diag_info->TxAMPDUCnt[0] = TxAggCnt0.field.AggSize1Count;
diag_info->TxAMPDUCnt[1] = TxAggCnt0.field.AggSize2Count;
diag_info->TxAMPDUCnt[2] = TxAggCnt1.field.AggSize3Count;
diag_info->TxAMPDUCnt[3] = TxAggCnt1.field.AggSize4Count;
diag_info->TxAMPDUCnt[4] = TxAggCnt2.field.AggSize5Count;
diag_info->TxAMPDUCnt[5] = TxAggCnt2.field.AggSize6Count;
diag_info->TxAMPDUCnt[6] = TxAggCnt3.field.AggSize7Count;
diag_info->TxAMPDUCnt[7] = TxAggCnt3.field.AggSize8Count;
diag_info->TxAMPDUCnt[8] = TxAggCnt4.field.AggSize9Count;
diag_info->TxAMPDUCnt[9] = TxAggCnt4.field.AggSize10Count;
diag_info->TxAMPDUCnt[10] = TxAggCnt5.field.AggSize11Count;
diag_info->TxAMPDUCnt[11] = TxAggCnt5.field.AggSize12Count;
diag_info->TxAMPDUCnt[12] = TxAggCnt6.field.AggSize13Count;
diag_info->TxAMPDUCnt[13] = TxAggCnt6.field.AggSize14Count;
diag_info->TxAMPDUCnt[14] = TxAggCnt7.field.AggSize15Count;
diag_info->TxAMPDUCnt[15] = TxAggCnt7.field.AggSize16Count;
#endif /* DBG_TX_AGG_CNT */
diag_info->RxCrcErrCnt = RxStaCnt0.field.CrcErr;
INC_RING_INDEX(pDiag->ArrayCurIdx, DIAGNOSE_TIME);
ArrayCurIdx = pDiag->ArrayCurIdx;
NdisZeroMemory(&pDiag->diag_info[ArrayCurIdx], sizeof(pDiag->diag_info[ArrayCurIdx]));
if (pDiag->ArrayCurIdx == pDiag->ArrayStartIdx)
INC_RING_INDEX(pDiag->ArrayStartIdx, DIAGNOSE_TIME);
}
}
#endif /* DBG_DIAGNOSE */
}
/*
========================================================================
Routine Description:
Process MGMT ring DMA done interrupt, running in DPC level
Arguments:
pAd Pointer to our adapter
Return Value:
None
IRQL = DISPATCH_LEVEL
Note:
========================================================================
*/
VOID RTMPHandleMgmtRingDmaDoneInterrupt(
IN PRTMP_ADAPTER pAd)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PNDIS_PACKET pPacket;
// int i;
UCHAR FREE = 0;
PRTMP_MGMT_RING pMgmtRing = &pAd->MgmtRing;
NdisAcquireSpinLock(&pAd->MgmtRingLock);
RTMP_IO_READ32(pAd, TX_MGMTDTX_IDX, &pMgmtRing->TxDmaIdx);
while (pMgmtRing->TxSwFreeIdx!= pMgmtRing->TxDmaIdx)
{
FREE++;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].AllocVa);
#endif
pTxD->DMADONE = 0;
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket;
if (pPacket == NULL)
continue;
#ifdef CONFIG_AP_SUPPORT
#define LMR_FRAME_GET() (GET_OS_PKT_DATAPTR(pPacket)+TXWI_SIZE)
#ifdef UAPSD_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
UAPSD_QoSNullTxMgmtTxDoneHandle(pAd,
pPacket,
LMR_FRAME_GET());
}
#endif // UAPSD_AP_SUPPORT //
#ifdef WMM_ACM_SUPPORT
{
HEADER_802_11 *pHeader;
/* handle Power Save ADDTS Response */
pHeader = (HEADER_802_11 *)(LMR_FRAME_GET());
if ((pHeader->FC.Type == BTYPE_MGMT) &&
(pHeader->FC.SubType == SUBTYPE_ACTION))
{
ACMP_PsRspDeltsSentOutHandle(pAd,
MacTableLookup(pAd, pHeader->Addr1),
((UCHAR *)pHeader)+sizeof(HEADER_802_11));
}
}
#endif // WMM_ACM_SUPPORT //
#endif // CONFIG_AP_SUPPORT //
if (pPacket)
{
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket = NULL;
pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket;
if (pPacket)
{
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket = NULL;
INC_RING_INDEX(pMgmtRing->TxSwFreeIdx, MGMT_RING_SIZE);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, TRUE, TYPE_TXD);
#endif
}
NdisReleaseSpinLock(&pAd->MgmtRingLock);
#ifdef CONFIG_STA_SUPPORT
#ifdef WMM_ACM_SUPPORT
/* return power save right if possible, ex:
0. sta enter PS mode;
1. sta enters ACTIVE mode;
2. sta sends ADDTS request frame;
3. sta receives ADDTS response frame;
4. sta enter PS mode; (ACMP_StaPsCtrlRightReturn) */
if (ACMR_IS_ENABLED(pAd))
ACMP_StaPsCtrlRightReturn(pAd);
/* End of if */
#endif // WMM_ACM_SUPPORT //
#endif // CONFIG_STA_SUPPORT //
}
PNDIS_PACKET GetPacketFromRxRing(
IN PRTMP_ADAPTER pAd,
OUT PRT28XX_RXD_STRUC pSaveRxD,
OUT BOOLEAN *pbReschedule,
IN OUT UINT32 *pRxPending)
{
PRXD_STRUC pRxD;
#ifdef RT_BIG_ENDIAN
PRXD_STRUC pDestRxD;
RXD_STRUC RxD;
#endif
PNDIS_PACKET pRxPacket = NULL;
PNDIS_PACKET pNewPacket;
PVOID AllocVa;
NDIS_PHYSICAL_ADDRESS AllocPa;
BOOLEAN bReschedule = FALSE;
RTMP_DMACB *pRxCell;
RTMP_SEM_LOCK(&pAd->RxRingLock);
if (*pRxPending == 0)
{
// Get how may packets had been received
RTMP_IO_READ32(pAd, RX_DRX_IDX , &pAd->RxRing.RxDmaIdx);
if (pAd->RxRing.RxSwReadIdx == pAd->RxRing.RxDmaIdx)
{
// no more rx packets
bReschedule = FALSE;
goto done;
}
// get rx pending count
if (pAd->RxRing.RxDmaIdx > pAd->RxRing.RxSwReadIdx)
*pRxPending = pAd->RxRing.RxDmaIdx - pAd->RxRing.RxSwReadIdx;
else
*pRxPending = pAd->RxRing.RxDmaIdx + RX_RING_SIZE - pAd->RxRing.RxSwReadIdx;
}
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx];
#ifdef RT_BIG_ENDIAN
pDestRxD = (PRXD_STRUC) pRxCell->AllocVa;
RxD = *pDestRxD;
pRxD = &RxD;
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
#else
// Point to Rx indexed rx ring descriptor
pRxD = (PRXD_STRUC) pRxCell->AllocVa;
#endif
if (pRxD->DDONE == 0)
{
*pRxPending = 0;
// DMAIndx had done but DDONE bit not ready
bReschedule = TRUE;
goto done;
}
// return rx descriptor
NdisMoveMemory(pSaveRxD, pRxD, RXD_SIZE);
pNewPacket = RTMP_AllocateRxPacketBuffer(pAd, RX_BUFFER_AGGRESIZE, FALSE, &AllocVa, &AllocPa);
if (pNewPacket)
{
// unmap the rx buffer
PCI_UNMAP_SINGLE(pAd, pRxCell->DmaBuf.AllocPa,
pRxCell->DmaBuf.AllocSize, PCI_DMA_FROMDEVICE);
pRxPacket = pRxCell->pNdisPacket;
pRxCell->DmaBuf.AllocSize = RX_BUFFER_AGGRESIZE;
pRxCell->pNdisPacket = (PNDIS_PACKET) pNewPacket;
pRxCell->DmaBuf.AllocVa = AllocVa;
pRxCell->DmaBuf.AllocPa = AllocPa;
/* update SDP0 to new buffer of rx packet */
pRxD->SDP0 = AllocPa;
}
else
{
//DBGPRINT(RT_DEBUG_TRACE,("No Rx Buffer\n"));
pRxPacket = NULL;
bReschedule = TRUE;
}
pRxD->DDONE = 0;
// had handled one rx packet
*pRxPending = *pRxPending - 1;
// update rx descriptor and kick rx
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxD, (PUCHAR)pRxD, FALSE, TYPE_RXD);
#endif
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
done:
RTMP_SEM_UNLOCK(&pAd->RxRingLock);
*pbReschedule = bReschedule;
return pRxPacket;
}
NDIS_STATUS MlmeHardTransmitTxRing(
IN PRTMP_ADAPTER pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket)
{
PACKET_INFO PacketInfo;
PUCHAR pSrcBufVA;
UINT SrcBufLen;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PHEADER_802_11 pHeader_802_11;
BOOLEAN bAckRequired, bInsertTimestamp;
ULONG SrcBufPA;
UCHAR MlmeRate;
ULONG SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
PTXWI_STRUC pFirstTxWI;
ULONG FreeNum;
MAC_TABLE_ENTRY *pMacEntry = NULL;
RTMP_QueryPacketInfo(pPacket, &PacketInfo, &pSrcBufVA, &SrcBufLen);
if (pSrcBufVA == NULL)
{
return NDIS_STATUS_FAILURE;
}
FreeNum = GET_TXRING_FREENO(pAd, QueIdx);
if (FreeNum == 0)
{
return NDIS_STATUS_FAILURE;
}
SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC)pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
if (pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket)
{
DBGPRINT(RT_DEBUG_OFF, ("MlmeHardTransmit Error\n"));
return NDIS_STATUS_FAILURE;
}
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
AsicForceWakeup(pAd, TRUE);
}
#endif
pFirstTxWI =(PTXWI_STRUC)pSrcBufVA;
pHeader_802_11 = (PHEADER_802_11) (pSrcBufVA + TXWI_SIZE);
if (pHeader_802_11->Addr1[0] & 0x01)
{
MlmeRate = pAd->CommonCfg.BasicMlmeRate;
}
else
{
MlmeRate = pAd->CommonCfg.MlmeRate;
}
if ((pHeader_802_11->FC.Type == BTYPE_DATA) &&
(pHeader_802_11->FC.SubType == SUBTYPE_QOS_NULL))
{
pMacEntry = MacTableLookup(pAd, pHeader_802_11->Addr1);
}
if ((pAd->LatchRfRegs.Channel > 14) && (MlmeRate < RATE_6))
MlmeRate = RATE_6;
#ifdef CONFIG_STA_SUPPORT
if (pHeader_802_11->FC.Type != BTYPE_DATA)
{
if ((pHeader_802_11->FC.SubType == SUBTYPE_PROBE_REQ) || !(pAd->CommonCfg.bAPSDCapable && pAd->CommonCfg.APEdcaParm.bAPSDCapable))
{
pHeader_802_11->FC.PwrMgmt = PWR_ACTIVE;
}
else
{
pHeader_802_11->FC.PwrMgmt = pAd->CommonCfg.bAPSDForcePowerSave;
}
}
#endif
bInsertTimestamp = FALSE;
if (pHeader_802_11->FC.Type == BTYPE_CNTL)
{
bAckRequired = FALSE;
}
else
{
if (pHeader_802_11->Addr1[0] & 0x01)
{
bAckRequired = FALSE;
pHeader_802_11->Duration = 0;
}
else
{
bAckRequired = TRUE;
pHeader_802_11->Duration = RTMPCalcDuration(pAd, MlmeRate, 14);
if (pHeader_802_11->FC.SubType == SUBTYPE_PROBE_RSP)
{
bInsertTimestamp = TRUE;
}
}
}
pHeader_802_11->Sequence = pAd->Sequence++;
if (pAd->Sequence > 0xfff)
pAd->Sequence = 0;
if ((pHeader_802_11->FC.SubType != SUBTYPE_PROBE_REQ)
&& (pAd->CommonCfg.bIEEE80211H == 1)
&& (pAd->CommonCfg.RadarDetect.RDMode != RD_NORMAL_MODE))
{
DBGPRINT(RT_DEBUG_ERROR,("MlmeHardTransmit --> radar detect not in normal mode !!!\n"));
return (NDIS_STATUS_FAILURE);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader_802_11, DIR_WRITE, FALSE);
#endif
if (pMacEntry == NULL)
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE, bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, RESERVED_WCID, (SrcBufLen - TXWI_SIZE), PID_MGMT, 0, (UCHAR)pAd->CommonCfg.MlmeTransmit.field.MCS, IFS_BACKOFF, FALSE, &pAd->CommonCfg.MlmeTransmit);
}
else
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE,
bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, pMacEntry->Aid, (SrcBufLen - TXWI_SIZE),
pMacEntry->MaxHTPhyMode.field.MCS, 0,
(UCHAR)pMacEntry->MaxHTPhyMode.field.MCS,
IFS_BACKOFF, FALSE, &pMacEntry->MaxHTPhyMode);
}
pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket = pPacket;
pAd->TxRing[QueIdx].Cell[SwIdx].pNextNdisPacket = NULL;
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)pFirstTxWI, TYPE_TXWI);
#endif
SrcBufPA = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_EDCA);
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 1;
pTxD->SDLen0 = SrcBufLen;
pTxD->SDLen1 = 0;
pTxD->SDPtr0 = SrcBufPA;
pTxD->DMADONE = 0;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
INC_RING_INDEX(pAd->TxRing[QueIdx].TxCpuIdx, TX_RING_SIZE);
RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QueIdx*0x10, pAd->TxRing[QueIdx].TxCpuIdx);
return NDIS_STATUS_SUCCESS;
}
/*
Must be run in Interrupt context
This function handle PCI specific TxDesc and cpu index update and kick the packet out.
*/
int RtmpPCIMgmtKickOut(
IN RTMP_ADAPTER *pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket,
IN PUCHAR pSrcBufVA,
IN UINT SrcBufLen)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
ULONG SwIdx = pAd->MgmtRing.TxCpuIdx;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC)pAd->MgmtRing.Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) pAd->MgmtRing.Cell[SwIdx].AllocVa;
#endif
pAd->MgmtRing.Cell[SwIdx].pNdisPacket = pPacket;
pAd->MgmtRing.Cell[SwIdx].pNextNdisPacket = NULL;
RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_MGMT);
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 1;
pTxD->DMADONE = 0;
pTxD->SDLen1 = 0;
pTxD->SDPtr0 = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
pTxD->SDLen0 = SrcBufLen;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
//==================================================================
/* DBGPRINT_RAW(RT_DEBUG_TRACE, ("MLMEHardTransmit\n"));
for (i = 0; i < (TXWI_SIZE+24); i++)
{
DBGPRINT_RAW(RT_DEBUG_TRACE, ("%x:", *(pSrcBufVA+i)));
if ( i%4 == 3)
DBGPRINT_RAW(RT_DEBUG_TRACE, (" :: "));
if ( i%16 == 15)
DBGPRINT_RAW(RT_DEBUG_TRACE, ("\n "));
}
DBGPRINT_RAW(RT_DEBUG_TRACE, ("\n "));*/
//=======================================================================
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
// Increase TX_CTX_IDX, but write to register later.
INC_RING_INDEX(pAd->MgmtRing.TxCpuIdx, MGMT_RING_SIZE);
RTMP_IO_WRITE32(pAd, TX_MGMTCTX_IDX, pAd->MgmtRing.TxCpuIdx);
return 0;
}
PNDIS_PACKET GetPacketFromRxRing(
IN PRTMP_ADAPTER pAd,
OUT PRT28XX_RXD_STRUC pSaveRxD,
OUT BOOLEAN *pbReschedule,
IN OUT UINT32 *pRxPending)
{
PRXD_STRUC pRxD;
#ifdef RT_BIG_ENDIAN
PRXD_STRUC pDestRxD;
RXD_STRUC RxD;
#endif
PNDIS_PACKET pRxPacket = NULL;
PNDIS_PACKET pNewPacket;
PVOID AllocVa;
NDIS_PHYSICAL_ADDRESS AllocPa;
BOOLEAN bReschedule = FALSE;
RTMP_DMACB *pRxCell;
RTMP_SEM_LOCK(&pAd->RxRingLock);
if (*pRxPending == 0)
{
/* Get how may packets had been received*/
RTMP_IO_READ32(pAd, RX_DRX_IDX , &pAd->RxRing.RxDmaIdx);
if (pAd->RxRing.RxSwReadIdx == pAd->RxRing.RxDmaIdx)
{
/* no more rx packets*/
bReschedule = FALSE;
goto done;
}
/* get rx pending count*/
if (pAd->RxRing.RxDmaIdx > pAd->RxRing.RxSwReadIdx)
*pRxPending = pAd->RxRing.RxDmaIdx - pAd->RxRing.RxSwReadIdx;
else
*pRxPending = pAd->RxRing.RxDmaIdx + RX_RING_SIZE - pAd->RxRing.RxSwReadIdx;
#ifdef DESC_32B_SUPPORT
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx];
dma_cache_sync(NULL, pRxCell->AllocVa, RXD_SIZE, DMA_FROM_DEVICE);
#endif /* DESC_32B_SUPPORT */
}
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx];
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pRxCell->AllocPa, RXD_SIZE);
#ifdef RT_BIG_ENDIAN
pDestRxD = (PRXD_STRUC) pRxCell->AllocVa;
RxD = *pDestRxD;
pRxD = &RxD;
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
#else
/* Point to Rx indexed rx ring descriptor*/
pRxD = (PRXD_STRUC) pRxCell->AllocVa;
#endif
if (pRxD->DDONE == 0)
{
*pRxPending = 0;
/* DMAIndx had done but DDONE bit not ready*/
bReschedule = TRUE;
goto done;
}
#ifdef DESC_32B_SUPPORT
prefetch(&pAd->RxRing.Cell[(pAd->RxRing.RxSwReadIdx + 1) % RX_RING_SIZE].AllocVa);
#endif /* DESC_32B_SUPPORT */
/* return rx descriptor*/
NdisMoveMemory(pSaveRxD, pRxD, RXD_SIZE);
pNewPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev, RX_BUFFER_AGGRESIZE, FALSE, &AllocVa, &AllocPa);
if (pNewPacket)
{
/* unmap the rx buffer*/
PCI_UNMAP_SINGLE(pAd, pRxCell->DmaBuf.AllocPa,
pRxCell->DmaBuf.AllocSize, RTMP_PCI_DMA_FROMDEVICE);
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pRxCell->DmaBuf.AllocPa, pRxCell->DmaBuf.AllocSize);
pRxPacket = pRxCell->pNdisPacket;
pRxCell->DmaBuf.AllocSize = RX_BUFFER_AGGRESIZE;
pRxCell->pNdisPacket = (PNDIS_PACKET) pNewPacket;
pRxCell->DmaBuf.AllocVa = AllocVa;
pRxCell->DmaBuf.AllocPa = AllocPa;
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pRxCell->DmaBuf.AllocPa, pRxCell->DmaBuf.AllocSize);
/* update SDP0 to new buffer of rx packet */
pRxD->SDP0 = AllocPa;
#ifdef RX_DMA_SCATTER
pRxD->SDL0 = RX_BUFFER_AGGRESIZE;
#endif /* RX_DMA_SCATTER */
}
else
{
/*DBGPRINT(RT_DEBUG_TRACE,("No Rx Buffer\n"));*/
pRxPacket = NULL;
bReschedule = TRUE;
}
/* had handled one rx packet*/
*pRxPending = *pRxPending - 1;
#ifndef CACHE_LINE_32B
pRxD->DDONE = 0;
/* update rx descriptor and kick rx */
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxD, (PUCHAR)pRxD, FALSE, TYPE_RXD);
#endif
#ifdef DESC_32B_SUPPORT
dma_cache_sync(NULL, pRxCell->AllocVa, RXD_SIZE, DMA_TO_DEVICE);
#endif /* DESC_32B_SUPPORT */
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
#else /* CACHE_LINE_32B */
/*
Because our RXD_SIZE is 16B, but if the cache line size is 32B, we
will suffer a problem as below:
1. We flush RXD 0, start address of RXD 0 is 32B-align.
Nothing occurs.
2. We flush RXD 1, start address of RXD 1 is 16B-align.
Because cache line size is 32B, cache must flush 32B, cannot flush
16B only, so RXD0 and RXD1 will be flushed.
But when traffic is busy, maybe RXD0 is updated by MAC, i.e.
DDONE bit is 1, so when the cache flushs RXD0, the DDONE bit will
be cleared to 0.
3. Then when we handle RXD0 in the future, we will find the DDONE bit
is 0 and we will wait for MAC to set it to 1 forever.
*/
if (pAd->RxRing.RxSwReadIdx & 0x01)
{
RTMP_DMACB *pRxCellLast;
#ifdef RT_BIG_ENDIAN
PRXD_STRUC pDestRxDLast;
#endif
/* 16B-align */
/* update last BD 32B-align, DMA Done bit = 0 */
pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].LastBDInfo.DDONE = 0;
#ifdef RT_BIG_ENDIAN
pRxCellLast = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx - 1];
pDestRxDLast = (PRXD_STRUC) pRxCellLast->AllocVa;
RTMPDescriptorEndianChange((PUCHAR)&pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].LastBDInfo, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxDLast, (PUCHAR)&pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].LastBDInfo, FALSE, TYPE_RXD);
#endif
/* update current BD 16B-align, DMA Done bit = 0 */
pRxD->DDONE = 0;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxD, (PUCHAR)pRxD, FALSE, TYPE_RXD);
#endif
/* flush cache from last BD */
RTMP_DCACHE_FLUSH(pRxCellLast->AllocPa, 32); /* use RXD_SIZE should be OK */
/* update SW read and CPU index */
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
}
else
{
/* 32B-align */
/* do not set DDONE bit and backup it */
if (pAd->RxRing.RxSwReadIdx >= (RX_RING_SIZE-1))
{
DBGPRINT(RT_DEBUG_TRACE,
("Please change RX_RING_SIZE to mutiple of 2!\n"));
/* flush cache from current BD */
RTMP_DCACHE_FLUSH(pRxCell->AllocPa, RXD_SIZE);
/* update SW read and CPU index */
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
}
else
{
/* backup current BD */
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx + 1];
pRxCell->LastBDInfo = *pRxD;
/* update CPU index */
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
}
}
#endif /* CACHE_LINE_32B */
done:
RTMP_SEM_UNLOCK(&pAd->RxRingLock);
*pbReschedule = bReschedule;
return pRxPacket;
}
BOOLEAN RTMPFreeTXDUponTxDmaDone(
IN PRTMP_ADAPTER pAd,
IN UCHAR QueIdx)
{
PRTMP_TX_RING pTxRing;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
#endif
PNDIS_PACKET pPacket;
UCHAR FREE = 0;
TXD_STRUC TxD, *pOriTxD;
//ULONG IrqFlags;
BOOLEAN bReschedule = FALSE;
ASSERT(QueIdx < NUM_OF_TX_RING);
pTxRing = &pAd->TxRing[QueIdx];
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF, &pTxRing->TxDmaIdx);
while (pTxRing->TxSwFreeIdx != pTxRing->TxDmaIdx)
{
// RTMP_IRQ_LOCK(&pAd->irq_lock, IrqFlags);
#ifdef RALINK_ATE
#ifdef RALINK_QA
PHEADER_802_11 pHeader80211;
if ((ATE_ON(pAd)) && (pAd->ate.bQATxStart == TRUE))
{
if (pAd->ate.QID == QueIdx)
{
pAd->ate.TxDoneCount++;
pAd->RalinkCounters.KickTxCount++;
/* always use QID_AC_BE and FIFO_EDCA */
ASSERT(pAd->ate.QID == 0);
pAd->ate.TxAc0++;
FREE++;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
pHeader80211 = pTxRing->Cell[pTxRing->TxSwFreeIdx].DmaBuf.AllocVa + sizeof(TXWI_STRUC);
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader80211, DIR_READ, FALSE);
#endif
pHeader80211->Sequence = ++pAd->ate.seq;
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader80211, DIR_WRITE, FALSE);
#endif
if ((pAd->ate.bQATxStart == TRUE) && (pAd->ate.Mode & ATE_TXFRAME) && (pAd->ate.TxDoneCount < pAd->ate.TxCount))
{
pAd->RalinkCounters.TransmittedByteCount.QuadPart += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecTransmittedByteCount += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecDmaDoneCount[QueIdx] ++;
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
/* get TX_DTX_IDX again */
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF , &pTxRing->TxDmaIdx);
goto kick_out;
}
else if ((pAd->ate.TxStatus == 1)/* or (pAd->ate.bQATxStart == TRUE) ??? */ && (pAd->ate.TxDoneCount == pAd->ate.TxCount))
{
DBGPRINT(RT_DEBUG_TRACE,("all Tx is done\n"));
// Tx status enters idle mode.
pAd->ate.TxStatus = 0;
}
else if (!(pAd->ate.Mode & ATE_TXFRAME))
{
/* not complete sending yet, but someone press the Stop TX botton */
DBGPRINT(RT_DEBUG_INFO,("not complete sending yet, but someone pressed the Stop TX bottom\n"));
DBGPRINT(RT_DEBUG_INFO,("pAd->ate.Mode = 0x%02x\n", pAd->ate.Mode));
}
else
{
DBGPRINT(RT_DEBUG_OFF,("pTxRing->TxSwFreeIdx = %d\n", pTxRing->TxSwFreeIdx));
}
#ifndef RT_BIG_ENDIAN
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#else
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#endif // RT_BIG_ENDIAN //
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
continue;
}
}
#endif // RALINK_QA //
#endif // RALINK_ATE //
// static rate also need NICUpdateFifoStaCounters() function.
//if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED))
#ifdef VENDOR_FEATURE1_SUPPORT
/*
Note:
Can not take off the NICUpdateFifoStaCounters(); Or the
FIFO overflow rate will be high, i.e. > 3%
(see the rate by "iwpriv ra0 show stainfo")
Based on different platform, try to find the best value to
replace '4' here (overflow rate target is about 0%).
*/
if (++pAd->FifoUpdateRx >= 4)
{
NICUpdateFifoStaCounters(pAd);
pAd->FifoUpdateRx = 0;
}
#else
NICUpdateFifoStaCounters(pAd);
#endif // VENDOR_FEATURE1_SUPPORT //
/* Note : If (pAd->ate.bQATxStart == TRUE), we will never reach here. */
FREE++;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
#ifdef CONFIG_AP_SUPPORT
#ifdef UAPSD_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
UAPSD_SP_PacketCheck(pAd,
pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket,
((UCHAR *)pTxRing->Cell[\
pTxRing->TxSwFreeIdx].DmaBuf.AllocVa)+TXWI_SIZE);
}
#endif // UAPSD_AP_SUPPORT //
#endif // CONFIG_AP_SUPPORT //
#ifdef RALINK_ATE
/* Execution of this block is not allowed when ATE is running. */
if (!(ATE_ON(pAd)))
#endif // RALINK_ATE //
{
pPacket = pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket;
if (pPacket)
{
#ifdef CONFIG_5VT_ENHANCE
if (RTMP_GET_PACKET_5VT(pPacket))
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, 16, PCI_DMA_TODEVICE);
else
#endif // CONFIG_5VT_ENHANCE //
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
//Always assign pNdisPacket as NULL after clear
pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket = NULL;
pPacket = pTxRing->Cell[pTxRing->TxSwFreeIdx].pNextNdisPacket;
if (pPacket)
{
#ifdef CONFIG_5VT_ENHANCE
if (RTMP_GET_PACKET_5VT(pPacket))
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, 16, PCI_DMA_TODEVICE);
else
#endif // CONFIG_5VT_ENHANCE //
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
//Always assign pNextNdisPacket as NULL after clear
pTxRing->Cell[pTxRing->TxSwFreeIdx].pNextNdisPacket = NULL;
}
pAd->RalinkCounters.TransmittedByteCount.QuadPart += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecTransmittedByteCount += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecDmaDoneCount[QueIdx] ++;
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
/* get tx_tdx_idx again */
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF , &pTxRing->TxDmaIdx);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#else
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#endif
#ifdef RALINK_ATE
#ifdef RALINK_QA
kick_out:
#endif // RALINK_QA //
/*
ATE_TXCONT mode also need to send some normal frames, so let it in.
ATE_STOP must be changed not to be 0xff
to prevent it from running into this block.
*/
if ((pAd->ate.Mode & ATE_TXFRAME) && (pAd->ate.QID == QueIdx))
{
// TxDoneCount++ has been done if QA is used.
if (pAd->ate.bQATxStart == FALSE)
{
pAd->ate.TxDoneCount++;
}
if (((pAd->ate.TxCount - pAd->ate.TxDoneCount + 1) >= TX_RING_SIZE))
{
/* Note : We increase TxCpuIdx here, not TxSwFreeIdx ! */
INC_RING_INDEX(pAd->TxRing[QueIdx].TxCpuIdx, TX_RING_SIZE);
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pAd->TxRing[QueIdx].TxCpuIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pAd->TxRing[QueIdx].TxCpuIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
#ifndef RT_BIG_ENDIAN
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#else
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#endif
// kick Tx-Ring
RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QueIdx * RINGREG_DIFF, pAd->TxRing[QueIdx].TxCpuIdx);
pAd->RalinkCounters.KickTxCount++;
}
}
#endif // RALINK_ATE //
// RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags);
}
return bReschedule;
}
NDIS_STATUS MlmeHardTransmitTxRing(
IN PRTMP_ADAPTER pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket)
{
PACKET_INFO PacketInfo;
PUCHAR pSrcBufVA;
UINT SrcBufLen;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PHEADER_802_11 pHeader_802_11;
BOOLEAN bAckRequired, bInsertTimestamp;
ULONG SrcBufPA;
/*UCHAR TxBufIdx;*/
UCHAR MlmeRate;
ULONG SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
PTXWI_STRUC pFirstTxWI;
/*ULONG i;*/
/*HTTRANSMIT_SETTING MlmeTransmit; Rate for this MGMT frame.*/
ULONG FreeNum;
MAC_TABLE_ENTRY *pMacEntry = NULL;
UINT8 TXWISize = pAd->chipCap.TXWISize;
#ifdef CONFIG_AP_SUPPORT
#ifdef SPECIFIC_TX_POWER_SUPPORT
UCHAR TxPwrAdj = 0;
#endif /* SPECIFIC_TX_POWER_SUPPORT */
#endif /* CONFIG_AP_SUPPORT */
RTMP_QueryPacketInfo(pPacket, &PacketInfo, &pSrcBufVA, &SrcBufLen);
if (pSrcBufVA == NULL)
{
/* The buffer shouldn't be NULL*/
return NDIS_STATUS_FAILURE;
}
/* Make sure MGMT ring resource won't be used by other threads*/
/*NdisAcquireSpinLock(&pAd->TxRingLock);*/
FreeNum = GET_TXRING_FREENO(pAd, QueIdx);
if (FreeNum == 0)
{
/*NdisReleaseSpinLock(&pAd->TxRingLock);*/
return NDIS_STATUS_FAILURE;
}
SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC)pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
#endif
if (pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket)
{
DBGPRINT(RT_DEBUG_OFF, ("MlmeHardTransmit Error\n"));
/*NdisReleaseSpinLock(&pAd->TxRingLock);*/
return NDIS_STATUS_FAILURE;
}
pFirstTxWI =(PTXWI_STRUC)(pSrcBufVA + TXINFO_SIZE);
pHeader_802_11 = (PHEADER_802_11)(pSrcBufVA + TXINFO_SIZE + TXWISize);
if (pHeader_802_11->Addr1[0] & 0x01)
{
MlmeRate = pAd->CommonCfg.BasicMlmeRate;
}
else
{
MlmeRate = pAd->CommonCfg.MlmeRate;
}
if ((pHeader_802_11->FC.Type == BTYPE_DATA) &&
(pHeader_802_11->FC.SubType == SUBTYPE_QOS_NULL))
{
pMacEntry = MacTableLookup(pAd, pHeader_802_11->Addr1);
}
/* Verify Mlme rate for a / g bands.*/
if ((pAd->LatchRfRegs.Channel > 14) && (MlmeRate < RATE_6)) /* 11A band*/
MlmeRate = RATE_6;
/*
Should not be hard code to set PwrMgmt to 0 (PWR_ACTIVE)
Snice it's been set to 0 while on MgtMacHeaderInit
By the way this will cause frame to be send on PWR_SAVE failed.
*/
/* In WMM-UAPSD, mlme frame should be set psm as power saving but probe request frame*/
bInsertTimestamp = FALSE;
if (pHeader_802_11->FC.Type == BTYPE_CNTL) /* must be PS-POLL*/
{
bAckRequired = FALSE;
}
else /* BTYPE_MGMT or BTYPE_DATA(must be NULL frame)*/
{
if (pHeader_802_11->Addr1[0] & 0x01) /* MULTICAST, BROADCAST*/
{
bAckRequired = FALSE;
pHeader_802_11->Duration = 0;
}
else
{
bAckRequired = TRUE;
pHeader_802_11->Duration = RTMPCalcDuration(pAd, MlmeRate, 14);
if (pHeader_802_11->FC.SubType == SUBTYPE_PROBE_RSP)
{
bInsertTimestamp = TRUE;
#ifdef CONFIG_AP_SUPPORT
#ifdef SPECIFIC_TX_POWER_SUPPORT
/* Find which MBSSID to be send this probeRsp */
UINT32 apidx;
for (apidx=0; apidx<pAd->ApCfg.BssidNum; apidx++)
{
if (RTMPEqualMemory(pHeader_802_11->Addr2, pAd->ApCfg.MBSSID[apidx].Bssid, MAC_ADDR_LEN))
break;
}
if (!(apidx >= pAd->ApCfg.BssidNum) &&
(pAd->ApCfg.MBSSID[apidx].TxPwrAdj != -1) &&
(pAd->CommonCfg.MlmeTransmit.field.MODE == MODE_CCK) &&
(pAd->CommonCfg.MlmeTransmit.field.MCS == RATE_1))
{
TxPwrAdj = pAd->ApCfg.MBSSID[apidx].TxPwrAdj;
}
#endif /* SPECIFIC_TX_POWER_SUPPORT */
#endif /* CONFIG_AP_SUPPORT */
}
}
}
pHeader_802_11->Sequence = pAd->Sequence++;
if (pAd->Sequence > 0xfff)
pAd->Sequence = 0;
/* Before radar detection done, mgmt frame can not be sent but probe req*/
/* Because we need to use probe req to trigger driver to send probe req in passive scan*/
if ((pHeader_802_11->FC.SubType != SUBTYPE_PROBE_REQ)
&& (pAd->CommonCfg.bIEEE80211H == 1)
&& (pAd->Dot11_H.RDMode != RD_NORMAL_MODE))
{
DBGPRINT(RT_DEBUG_ERROR,("MlmeHardTransmit --> radar detect not in normal mode !!!\n"));
/*NdisReleaseSpinLock(&pAd->TxRingLock);*/
return (NDIS_STATUS_FAILURE);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader_802_11, DIR_WRITE, FALSE);
#endif
/*
Fill scatter-and-gather buffer list into TXD. Internally created NDIS PACKET
should always has only one ohysical buffer, and the whole frame size equals
to the first scatter buffer size
*/
/*
Initialize TX Descriptor
For inter-frame gap, the number is for this frame and next frame
For MLME rate, we will fix as 2Mb to match other vendor's implement
*/
/* pAd->CommonCfg.MlmeTransmit.field.MODE = 1;*/
/* management frame doesn't need encryption. so use RESERVED_WCID no matter u are sending to specific wcid or not.*/
/* Only beacon use Nseq=TRUE. So here we use Nseq=FALSE.*/
if (pMacEntry == NULL)
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE, bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, RESERVED_WCID, (SrcBufLen - TXINFO_SIZE - TXWISize), PID_MGMT, 0, (UCHAR)pAd->CommonCfg.MlmeTransmit.field.MCS, IFS_BACKOFF, FALSE, &pAd->CommonCfg.MlmeTransmit);
#ifdef SPECIFIC_TX_POWER_SUPPORT
if (IS_RT6352(pAd))
pFirstTxWI->TxPwrAdj = TxPwrAdj;
#endif /* SPECIFIC_TX_POWER_SUPPORT */
}
else
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE,
bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, pMacEntry->Aid, (SrcBufLen - TXINFO_SIZE - TXWISize),
pMacEntry->MaxHTPhyMode.field.MCS, 0,
(UCHAR)pMacEntry->MaxHTPhyMode.field.MCS,
IFS_BACKOFF, FALSE, &pMacEntry->MaxHTPhyMode);
}
pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket = pPacket;
pAd->TxRing[QueIdx].Cell[SwIdx].pNextNdisPacket = NULL;
/* pFirstTxWI->MPDUtotalByteCount = SrcBufLen - TXWI_SIZE;*/
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)pFirstTxWI, TYPE_TXWI);
#endif
SrcBufPA = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, RTMP_PCI_DMA_TODEVICE);
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 0;
pTxD->SDLen1 = 0;
pTxD->SDPtr0 = SrcBufPA;
pTxD->SDLen0 = SrcBufLen;
RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(SrcBufPA, SrcBufLen);
RTMP_DCACHE_FLUSH(pAd->TxRing[QueIdx].Cell[SwIdx].AllocPa, RXD_SIZE);
/* Increase TX_CTX_IDX, but write to register later.*/
INC_RING_INDEX(pAd->TxRing[QueIdx].TxCpuIdx, TX_RING_SIZE);
RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QueIdx*0x10, pAd->TxRing[QueIdx].TxCpuIdx);
/* Make sure to release MGMT ring resource*/
/* NdisReleaseSpinLock(&pAd->TxRingLock);*/
return NDIS_STATUS_SUCCESS;
}
/*
Must be run in Interrupt context
This function handle RT2870 specific TxDesc and cpu index update and kick the packet out.
*/
int RtmpUSBMgmtKickOut(
IN RTMP_ADAPTER *pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket,
IN UCHAR *pSrcBufVA,
IN UINT SrcBufLen)
{
TXINFO_STRUC *pTxInfo;
ULONG BulkOutSize;
UCHAR padLen;
PUCHAR pDest;
ULONG SwIdx = pAd->MgmtRing.TxCpuIdx;
TX_CONTEXT *pMLMEContext = (PTX_CONTEXT)pAd->MgmtRing.Cell[SwIdx].AllocVa;
ULONG IrqFlags;
pTxInfo = (TXINFO_STRUC *)(pSrcBufVA);
/* Build our URB for USBD*/
BulkOutSize = (SrcBufLen + 3) & (~3);
rlt_usb_write_txinfo(pAd, pTxInfo, (USHORT)(BulkOutSize - TXINFO_SIZE), TRUE, EpToQueue[MGMTPIPEIDX], FALSE, FALSE);
BulkOutSize += 4; /* Always add 4 extra bytes at every packet.*/
//+++Add by shiang for debug
if (0) {
DBGPRINT(RT_DEBUG_OFF, ("-->%s():shiang-6590, QueIdx=%d, SrcBufLen=%d\n", __FUNCTION__, QueIdx, SrcBufLen));
dump_txinfo(pAd, pTxInfo);
dumpTxWI(pAd, (TXWI_STRUC *)(pSrcBufVA + TXINFO_SIZE));
}
//---Add by shiang for debug
/* WY , it cause Tx hang on Amazon_SE , Max said the padding is useless*/
/* If BulkOutSize is multiple of BulkOutMaxPacketSize, add extra 4 bytes again.*/
/* if ((BulkOutSize % pAd->BulkOutMaxPacketSize) == 0)*/
/* BulkOutSize += 4;*/
padLen = BulkOutSize - SrcBufLen;
ASSERT((padLen <= RTMP_PKT_TAIL_PADDING));
/* Now memzero all extra padding bytes.*/
pDest = (PUCHAR)(pSrcBufVA + SrcBufLen);
OS_PKT_TAIL_BUF_EXTEND(pPacket, padLen);
NdisZeroMemory(pDest, padLen);
RTMP_IRQ_LOCK(&pAd->MLMEBulkOutLock, IrqFlags);
pAd->MgmtRing.Cell[pAd->MgmtRing.TxCpuIdx].pNdisPacket = pPacket;
pMLMEContext->TransferBuffer = (PTX_BUFFER)(GET_OS_PKT_DATAPTR(pPacket));
/* Length in TxInfo should be 8 less than bulkout size.*/
pMLMEContext->BulkOutSize = BulkOutSize;
pMLMEContext->InUse = TRUE;
pMLMEContext->bWaitingBulkOut = TRUE;
#ifdef UAPSD_SUPPORT
/*
If the packet is QoS Null frame, we mark the packet with its WCID;
If not, we mark the packet with bc/mc WCID = 0.
We will handle it in rtusb_mgmt_dma_done_tasklet().
Even AP send a QoS Null frame but not EOSP frame in USB mode,
then we will call UAPSD_SP_Close() and we will check
pEntry->bAPSDFlagSPStart() so do not worry about it.
*/
#endif /* UAPSD_SUPPORT */
/*hex_dump("RtmpUSBMgmtKickOut", &pMLMEContext->TransferBuffer->field.WirelessPacket[0], (pMLMEContext->BulkOutSize > 16 ? 16 : pMLMEContext->BulkOutSize));*/
/*
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
if (pAd->MgmtRing.TxSwFreeIdx == MGMT_RING_SIZE)
needKickOut = TRUE;
*/
/* Decrease the TxSwFreeIdx and Increase the TX_CTX_IDX*/
pAd->MgmtRing.TxSwFreeIdx--;
INC_RING_INDEX(pAd->MgmtRing.TxCpuIdx, MGMT_RING_SIZE);
RTMP_IRQ_UNLOCK(&pAd->MLMEBulkOutLock, IrqFlags);
RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_MLME);
/*if (needKickOut)*/
RTUSBKickBulkOut(pAd);
return 0;
}
USHORT RtmpPCI_WriteMultiTxResource(
IN PRTMP_ADAPTER pAd,
IN TX_BLK *pTxBlk,
IN UCHAR frameNum,
OUT USHORT *FreeNumber)
{
BOOLEAN bIsLast;
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHdrLen;
UINT32 firstDMALen;
UINT8 TXWISize = pAd->chipCap.TXWISize;
bIsLast = ((frameNum == (pTxBlk->TotalFrameNum - 1)) ? 1 : 0);
/* get Tx Ring Resource*/
pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
BufBasePaLow = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
if (frameNum == 0)
{
/* copy TXINFO + TXWI + WLAN Header + LLC into DMA Header Buffer*/
if (pTxBlk->TxFrameType == TX_AMSDU_FRAME)
/*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen-LENGTH_AMSDU_SUBFRAMEHEAD, 4)+LENGTH_AMSDU_SUBFRAMEHEAD;*/
hwHdrLen = pTxBlk->MpduHeaderLen - LENGTH_AMSDU_SUBFRAMEHEAD + pTxBlk->HdrPadLen + LENGTH_AMSDU_SUBFRAMEHEAD;
else if (pTxBlk->TxFrameType == TX_RALINK_FRAME)
/*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen-LENGTH_ARALINK_HEADER_FIELD, 4)+LENGTH_ARALINK_HEADER_FIELD;*/
hwHdrLen = pTxBlk->MpduHeaderLen - LENGTH_ARALINK_HEADER_FIELD + pTxBlk->HdrPadLen + LENGTH_ARALINK_HEADER_FIELD;
else
/*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4);*/
hwHdrLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
firstDMALen = TXINFO_SIZE + TXWISize + hwHdrLen;
}
else
{
firstDMALen = pTxBlk->MpduHeaderLen;
}
NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf, firstDMALen);
pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
/* build Tx Descriptor*/
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
NdisZeroMemory(pTxD, TXD_SIZE);
pTxD->SDPtr0 = BufBasePaLow;
pTxD->SDLen0 = firstDMALen; /* include padding*/
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, RTMP_PCI_DMA_TODEVICE);;
pTxD->SDLen1 = pTxBlk->SrcBufLen;
pTxD->LastSec0 = !(pTxD->SDLen1);
pTxD->LastSec1 = (bIsLast && pTxD->SDLen1) ? 1 : 0;
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
if (frameNum == 0)
RTMPFrameEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA+ TXINFO_SIZE + TXWISize), DIR_WRITE, FALSE);
if (frameNum != 0)
RTMPWIEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE), TYPE_TXWI);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif /* RT_BIG_ENDIAN */
RetTxIdx = TxIdx;
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pTxRing->Cell[TxIdx].DmaBuf.AllocPa, pTxD->SDLen0);
RTMP_DCACHE_FLUSH(pTxBlk->pSrcBufData, pTxBlk->SrcBufLen);
RTMP_DCACHE_FLUSH(pTxRing->Cell[TxIdx].AllocPa, RXD_SIZE);
/* Update Tx index*/
INC_RING_INDEX(TxIdx, TX_RING_SIZE);
pTxRing->TxCpuIdx = TxIdx;
*FreeNumber -= 1;
return RetTxIdx;
}
int RtmpUSBMgmtKickOut(
IN RTMP_ADAPTER *pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket,
IN PUCHAR pSrcBufVA,
IN UINT SrcBufLen)
{
PTXINFO_STRUC pTxInfo;
ULONG BulkOutSize;
UCHAR padLen;
PUCHAR pDest;
ULONG SwIdx = pAd->MgmtRing.TxCpuIdx;
PTX_CONTEXT pMLMEContext = (PTX_CONTEXT)pAd->MgmtRing.Cell[SwIdx].AllocVa;
unsigned long IrqFlags;
pTxInfo = (PTXINFO_STRUC)(pSrcBufVA);
BulkOutSize = SrcBufLen;
BulkOutSize = (BulkOutSize + 3) & (~3);
RTMPWriteTxInfo(pAd, pTxInfo, (USHORT)(BulkOutSize - TXINFO_SIZE), TRUE, EpToQueue[MGMTPIPEIDX], FALSE, FALSE);
BulkOutSize += 4;
if ((BulkOutSize % pAd->BulkOutMaxPacketSize) == 0)
BulkOutSize += 4;
padLen = BulkOutSize - SrcBufLen;
ASSERT((padLen <= RTMP_PKT_TAIL_PADDING));
pDest = (PUCHAR)(pSrcBufVA + SrcBufLen);
skb_put(GET_OS_PKT_TYPE(pPacket), padLen);
NdisZeroMemory(pDest, padLen);
RTMP_IRQ_LOCK(&pAd->MLMEBulkOutLock, IrqFlags);
pAd->MgmtRing.Cell[pAd->MgmtRing.TxCpuIdx].pNdisPacket = pPacket;
pMLMEContext->TransferBuffer = (PTX_BUFFER)(GET_OS_PKT_DATAPTR(pPacket));
pMLMEContext->BulkOutSize = BulkOutSize;
pMLMEContext->InUse = TRUE;
pMLMEContext->bWaitingBulkOut = TRUE;
pAd->MgmtRing.TxSwFreeIdx--;
INC_RING_INDEX(pAd->MgmtRing.TxCpuIdx, MGMT_RING_SIZE);
RTMP_IRQ_UNLOCK(&pAd->MLMEBulkOutLock, IrqFlags);
RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_MLME);
RTUSBKickBulkOut(pAd);
return 0;
}
USHORT RtmpPCI_WriteFragTxResource(
IN PRTMP_ADAPTER pAd,
IN TX_BLK *pTxBlk,
IN UCHAR fragNum,
OUT USHORT *FreeNumber)
{
UCHAR *pDMAHeaderBufVA;
USHORT TxIdx, RetTxIdx;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
UINT32 BufBasePaLow;
PRTMP_TX_RING pTxRing;
USHORT hwHeaderLen;
UINT32 firstDMALen;
UINT8 TXWISize = pAd->chipCap.TXWISize;
/* Get Tx Ring Resource*/
pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
BufBasePaLow = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
/* Copy TXINFO + TXWI + WLAN Header + LLC into DMA Header Buffer*/
/*hwHeaderLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4);*/
hwHeaderLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
firstDMALen = TXINFO_SIZE + TXWISize + hwHeaderLen;
NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf, firstDMALen);
/* Build Tx Descriptor*/
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif
NdisZeroMemory(pTxD, TXD_SIZE);
if (fragNum == pTxBlk->TotalFragNum)
{
pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
}
pTxD->SDPtr0 = BufBasePaLow;
pTxD->SDLen0 = firstDMALen; /* include padding*/
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, RTMP_PCI_DMA_TODEVICE);
pTxD->SDLen1 = pTxBlk->SrcBufLen;
if (pTxD->SDLen1 > 0)
{
pTxD->LastSec0 = 0;
pTxD->LastSec1 = 1;
}
else
{
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 0;
}
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE), TYPE_TXWI);
RTMPFrameEndianChange(pAd, (PUCHAR)(pDMAHeaderBufVA + TXINFO_SIZE + TXWISize), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif /* RT_BIG_ENDIAN */
RetTxIdx = TxIdx;
pTxBlk->Priv += pTxBlk->SrcBufLen;
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pTxRing->Cell[TxIdx].DmaBuf.AllocPa, pTxD->SDLen0);
RTMP_DCACHE_FLUSH(pTxBlk->pSrcBufData, pTxBlk->SrcBufLen);
RTMP_DCACHE_FLUSH(pTxRing->Cell[TxIdx].AllocPa, RXD_SIZE);
/* Update Tx index*/
INC_RING_INDEX(TxIdx, TX_RING_SIZE);
pTxRing->TxCpuIdx = TxIdx;
*FreeNumber -= 1;
return RetTxIdx;
}
