void platform_init_interrupts(void)
{
unsigned int i;
// reset the controller
*REG32(INTC_SYSCONFIG) = 0x2; // start a reset
while ((*REG32(INTC_SYSSTATUS) & 0x1) == 0)
;
// mask all interrupts
*REG32(INTC_MIR(0)) = 0xffffffff;
*REG32(INTC_MIR(1)) = 0xffffffff;
*REG32(INTC_MIR(2)) = 0xffffffff;
// set up each of the interrupts
for (i = 0; i < INT_VECTORS; i++) {
// set each vector up as high priority IRQ
*REG32(INTC_ILR(i)) = 0;
//*ICReg(i / 32, INTCON_ILR_BASE + 4*(i%32)) = ((level_trigger[i/32] & (1<<(i%32))) ? (1<<1) : (0<<1)) | 0;
}
// disable the priority threshold
*REG32(INTC_THRESHOLD) = 0xff;
// clear any pending sw interrupts
*REG32(INTC_ISR_CLEAR(0)) = 0xffffffff;
*REG32(INTC_ISR_CLEAR(1)) = 0xffffffff;
*REG32(INTC_ISR_CLEAR(2)) = 0xffffffff;
// globally unmask interrupts
*REG32(INTC_CONTROL) = 3; // reset and enable the controller
}
static void intc_mask(struct vmm_host_irq *irq)
{
intc_write(INTC_MIR((irq->num / INTC_BITS_PER_REG)),
0x1 << (irq->num & (INTC_BITS_PER_REG - 1)));
}
